JPH1197328A - Method for forming resist pattern - Google Patents

Method for forming resist pattern

Info

Publication number
JPH1197328A
JPH1197328A JP25218997A JP25218997A JPH1197328A JP H1197328 A JPH1197328 A JP H1197328A JP 25218997 A JP25218997 A JP 25218997A JP 25218997 A JP25218997 A JP 25218997A JP H1197328 A JPH1197328 A JP H1197328A
Authority
JP
Japan
Prior art keywords
resist
resist pattern
pattern
processed
resist layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25218997A
Other languages
Japanese (ja)
Inventor
Takashi Suzuki
木 隆 鈴
Yoshiaki Kitaura
浦 義 昭 北
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP25218997A priority Critical patent/JPH1197328A/en
Publication of JPH1197328A publication Critical patent/JPH1197328A/en
Pending legal-status Critical Current

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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Electron Beam Exposure (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PROBLEM TO BE SOLVED: To make a high precision lift-off fine resist pattern with excellent resolution, by a method wherein, after first and second resist layers having different sensitivities are sequently formed on a processed substrate, exposure and development processes are performed to form a resist pattern. SOLUTION: After a resist film 3 is formed on a processed film of a processed substrate 1 such as a GaAs substrate, etc., in which a processed film such as SiO2 , etc., is formed, it is prebaked in a specified manner to carry out a crosslinking reaction. Next, after electron beams are irradiated on specified conditions and a space pattern of a specified dimension is drawn, a bake process after exposure is performed in the atmosphere by use of a hot plate at a specified temperature. Further, for example, the to-be-processed substrate is dipped in a developer based on tetraammonium hydroxide with alkali concentration 0.27, developing is performed to form a lift-off fine resist pattern 6. A resist layer of an upper layer with a large crosslinking rate is finished as a substantially prescribed dimension.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、リフトオフ用のレ
ジストパターンを形成するレジストパターンの形成方法
に関する。
The present invention relates to a method for forming a resist pattern for forming a lift-off resist pattern.

【0002】[0002]

【従来の技術】現在、GaAs集積回路の高集積化、高
速化に伴い、リソグラフィー技術においては、微細でし
かも寸法制御性に優れたレジストパターンの形成技術が
要求されている。
2. Description of the Related Art At present, as GaAs integrated circuits become more highly integrated and operate at higher speeds, there is a demand in lithography technology for forming resist patterns which are fine and have excellent dimensional controllability.

【0003】GaAs集積回路の配線には、オーミック
金属との整合性から通常、Au系の金属が用いられてい
る。しかし、この金属はRIE(Reactive Ion-Etchin
g)法を用いて加工するのが極めて困難であり、加工に
はリフトオフ法が用いられている。
For the wiring of the GaAs integrated circuit, an Au-based metal is usually used because of its compatibility with the ohmic metal. However, this metal is RIE (Reactive Ion-Etchin
It is extremely difficult to process using the g) method, and the lift-off method is used for the processing.

【0004】従来、このリフトオフ法を用いてレジスト
パターンを形成する場合には、イメージリバースレジス
トに染料が添加される。この染料が添加されたことによ
って、露光光(例えばg線)に対するレジストの透過率
を大幅に低減させるとともにレジスト表面での光の吸収
を大きくする。この状態でパターンを露光し、露光後に
リバーサルベークを行い、現像処理することによってリ
フトオフに適した逆テーパ状のレジストパターンを形成
していた。
Conventionally, when a resist pattern is formed using this lift-off method, a dye is added to an image reverse resist. The addition of this dye greatly reduces the transmittance of the resist to exposure light (eg, g-line) and increases the light absorption on the resist surface. In this state, the pattern is exposed, reversal baking is performed after the exposure, and development processing is performed to form an inversely tapered resist pattern suitable for lift-off.

【0005】[0005]

【発明が解決しようとする課題】従来、上述のように、
リフトオフ用のレジストパターンを形成する場合は染料
が添加されたイメージリバースレジストを用いられてい
た。このイメージリバースレジスを用いて形成されたパ
ターンは逆テーパ形状となるため、パターン寸法を微細
化すると、パターン倒れ等が発生して解像性が著しく低
下し、リフトオフ用の微細レジストパターンを形成する
のが極めて困難となる問題が生じる。
Conventionally, as described above,
When a resist pattern for lift-off is formed, an image reverse resist to which a dye is added has been used. Since the pattern formed by using this image reverse resist has an inverse tapered shape, when the pattern size is reduced, pattern collapse or the like occurs, the resolution is significantly reduced, and a fine resist pattern for lift-off is formed. There is a problem that is extremely difficult.

【0006】本発明は上記事情を考慮してなされたもの
であって、解像性に優れた高精度なリフトオフ用の微細
なレジストパターンを形成することのできるレジストパ
ターンの形成方法を提供することを目的とする。
The present invention has been made in consideration of the above circumstances, and provides a method of forming a resist pattern capable of forming a fine resist pattern for lift-off with excellent resolution and high accuracy. With the goal.

【0007】[0007]

【課題を解決するための手段】本発明によるレジストパ
ターンの形成方法は、被処理基板上に感度の異なる第1
および第2のレジスト層を順次形成する工程と、露光お
よび現像処理する工程と、を備えていることを特徴とす
る。
According to the method of forming a resist pattern according to the present invention, first resist patterns having different sensitivities are formed on a substrate to be processed.
And a step of sequentially forming a second resist layer, and a step of performing exposure and development processing.

【0008】また、前記第1のレジスト層は被処理基板
にレジストを塗布した後、第1の所定温度の雰囲気中で
プリベークを行うことによって形成し、前記第2のレジ
スト層は前記第1のレジスト層上にレジストを塗布した
後、前記第1の所定温度よりも低い第2の所定温度の雰
囲気中でプリベークを行って形成するように構成しても
良い。
Further, the first resist layer is formed by applying a resist to a substrate to be processed and then performing a pre-bake in an atmosphere at a first predetermined temperature, and the second resist layer is formed by the first resist layer. After applying a resist on the resist layer, the resist layer may be formed by performing pre-baking in an atmosphere at a second predetermined temperature lower than the first predetermined temperature.

【0009】[0009]

【発明の実施の形態】本発明によるレジストパターンの
形成方法の一実施の形態を図1を参照して説明する。図
1は上記実施の形態のレジストパターン形成の工程断面
図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method for forming a resist pattern according to the present invention will be described with reference to FIG. FIG. 1 is a sectional view showing a process of forming a resist pattern according to the embodiment.

【0010】まず被加工膜(例えばSiO2 )が形成さ
れた被処理基板(例えばGaAs基板)1の上記被加工
膜上に化学増幅系ネガ型電子線レジスト(例えばシプレ
ー社製SAL601)を塗布し、例えば2μmの厚さの
レジスト層3を形成する(図1(a)参照)。続いて1
45℃の雰囲気中で1分間程度のプリベークを行う。化
学増幅系のレジストには酸が含まれており、ベークされ
ると上記酸を触媒にして架橋反応が連続的に生じる。
First, a chemically amplified negative electron beam resist (for example, SAL601 manufactured by Shipley Co.) is applied on the above-mentioned processed film of a substrate (for example, GaAs substrate) 1 on which a processed film (for example, SiO 2 ) is formed. For example, a resist layer 3 having a thickness of, for example, 2 μm is formed (see FIG. 1A). Then 1
Pre-baking is performed for about 1 minute in an atmosphere of 45 ° C. The chemically amplified resist contains an acid, and when baked, a cross-linking reaction occurs continuously using the acid as a catalyst.

【0011】次に上記レジスト層上に、化学増幅系ネガ
型電子線レジストを塗布し、例えば0.5μmの膜厚の
レジスト層5を形成する(図1(b)参照)。続いて6
5℃の雰囲気中で1分間程度のプリベークを行う。
Next, a chemically amplified negative electron beam resist is applied on the resist layer to form a resist layer 5 having a thickness of, for example, 0.5 μm (see FIG. 1B). Then 6
Pre-bake is performed for about 1 minute in an atmosphere at 5 ° C.

【0012】次に加速電圧が50KVの電子線を用い
て、照射量15μC/cm2 の条件でパターン寸法0.2
μmのスペースパターンを描画する(図1(c)参
照)。その後、115℃に設定されたホットプレートを
用い、大気中で2分間程度の露光後ベーク処理を行う。
[0012] Next acceleration voltage by using an electron beam of 50 KV, pattern size 0.2 under the conditions of irradiation dose 15 .mu.C / cm 2
A space pattern of μm is drawn (see FIG. 1C). Thereafter, using a hot plate set at 115 ° C., a post-exposure bake process is performed in the air for about 2 minutes.

【0013】次に、例えばアルカリ濃度が0.27のテ
トラメチルアンモニュウムハイドロオキサイドベースの
現像液中に上記被処理基板を10分間浸漬することによ
り現像処理を行い、リフトオフ用の微細レジストパター
ン6を形成する(図1(d)参照)。
Next, the substrate is immersed in, for example, a tetramethylammonium hydroxide-based developer having an alkali concentration of 0.27 for 10 minutes to carry out a development process, thereby forming a fine resist pattern 6 for lift-off. (See FIG. 1D).

【0014】上述のように本実施の形態においては、下
層のレジスト層3を比較的高温(例えば145℃)でプ
リベークし、上層のレジスト層5を比較的低温(例えば
65℃)でプリベークしたことにより、下層レジストの
架橋率が小さくなって感度が低くなり、また上層のレジ
スト層5の架橋率が大きくなって感度が高くなる。この
状態で露光し、現像した場合には、架橋率の小さい下層
のレジスト層3の方が溶解速度が大きくなり、設計寸法
(露光寸法)よりも仕上がり寸法が大幅に減少する(図
1(c)、(d)参照)。しかし架橋率の大きい上層の
レジスト層ではほぼ設計寸法通りに仕上がる。このた
め、パターン倒れが生じぜず解像性に優れた高精度なリ
フトオフ用の微細なレジストパターンを形成することが
できる。
As described above, in the present embodiment, the lower resist layer 3 is prebaked at a relatively high temperature (for example, 145 ° C.), and the upper resist layer 5 is prebaked at a relatively low temperature (for example, 65 ° C.). Accordingly, the cross-linking rate of the lower resist is reduced to lower the sensitivity, and the cross-linking rate of the upper resist layer 5 is increased to increase the sensitivity. When exposed and developed in this state, the lower resist layer 3 having a lower crosslinking rate has a higher dissolution rate, and the finished dimension is significantly reduced from the designed dimension (exposure dimension) (FIG. 1 (c)). ), (D)). However, the upper resist layer having a high cross-linking rate is almost finished as designed. For this reason, it is possible to form a fine resist pattern for lift-off with high accuracy and excellent resolution without pattern collapse.

【0015】なお、上記実施の形態においてレジスト層
3のプリベーク温度としては140〜150℃の範囲で
あれば同様の効果を得ることができる。またレジスト層
5のプリベーク温度としては60〜70℃の範囲であれ
ば同様の効果を得ることができる。
In the above embodiment, the same effect can be obtained if the pre-bake temperature of the resist layer 3 is in the range of 140 to 150 ° C. The same effect can be obtained if the pre-bake temperature of the resist layer 5 is in the range of 60 to 70 ° C.

【0016】なお、上記実施の形態においては、レジス
トとして化学増幅系がネガ型電子線レジストを用いた
が、化学増幅系に限らず、電子線に感度を有するネガ型
レジストを用いても良いことは云うまでもない。
In the above embodiment, a negative electron beam resist is used as the resist in the chemical amplification system. However, the present invention is not limited to the chemical amplification system, and a negative resist having sensitivity to electron beams may be used. Needless to say.

【0017】[0017]

【発明の効果】以上述べたように本発明によれば、解像
性に優れた高精度なリフトオフ用の微細なレジストパタ
ーンを形成するとができる。
As described above, according to the present invention, it is possible to form a fine resist pattern for lift-off with excellent resolution and high accuracy.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるレジストパターンの形成方法の一
実施の形態の構成を示す工程断面図。
FIG. 1 is a process sectional view showing a configuration of an embodiment of a method for forming a resist pattern according to the present invention.

【符号の説明】[Explanation of symbols]

1 被処理基板 3 レジスト層 5 レジスト層 6 レジストパターン Reference Signs List 1 substrate to be processed 3 resist layer 5 resist layer 6 resist pattern

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】被処理基板上に感度の異なる第1および第
2のレジスト層を順次形成する工程と、 露光および現像処理する工程と、 を備えていることを特徴とするレジストパターンの形成
方法。
1. A method for forming a resist pattern, comprising: a step of sequentially forming first and second resist layers having different sensitivities on a substrate to be processed; and a step of exposing and developing. .
【請求項2】前記第1のレジスト層は被処理基板にレジ
ストを塗布した後、第1の所定温度の雰囲気中でプリベ
ークを行うことによって形成し、前記第2のレジスト層
は前記第1のレジスト層上にレジストを塗布した後、前
記第1の所定温度よりも低い第2の所定温度の雰囲気中
でプリベークを行って形成することを特徴とする請求項
1記載のレジストパターンの形成方法。
2. The first resist layer is formed by applying a resist on a substrate to be processed and then performing a pre-bake in an atmosphere at a first predetermined temperature, and the second resist layer is formed by applying the first resist layer to the first resist layer. 2. The method according to claim 1, wherein after the resist is applied on the resist layer, the resist pattern is formed by pre-baking in an atmosphere at a second predetermined temperature lower than the first predetermined temperature.
【請求項3】前記レジスト層の形成にネガ型電子線レジ
ストが用いられることを特徴とする請求項1または2記
載のレジストパターン形成方法。
3. The method according to claim 1, wherein a negative electron beam resist is used for forming the resist layer.
JP25218997A 1997-09-17 1997-09-17 Method for forming resist pattern Pending JPH1197328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25218997A JPH1197328A (en) 1997-09-17 1997-09-17 Method for forming resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25218997A JPH1197328A (en) 1997-09-17 1997-09-17 Method for forming resist pattern

Publications (1)

Publication Number Publication Date
JPH1197328A true JPH1197328A (en) 1999-04-09

Family

ID=17233747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25218997A Pending JPH1197328A (en) 1997-09-17 1997-09-17 Method for forming resist pattern

Country Status (1)

Country Link
JP (1) JPH1197328A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002139842A (en) * 2000-11-01 2002-05-17 Fujitsu Ltd Pattern forming method and semiconductor device
WO2002080239A2 (en) * 2001-03-28 2002-10-10 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features
US6589709B1 (en) 2001-03-28 2003-07-08 Advanced Micro Devices, Inc. Process for preventing deformation of patterned photoresist features
US6653231B2 (en) 2001-03-28 2003-11-25 Advanced Micro Devices, Inc. Process for reducing the critical dimensions of integrated circuit device features
EP1372191A2 (en) * 2002-06-14 2003-12-17 Filtronic Compound Semiconductor Limited Method for depositing a device feature on a substrate
US6716571B2 (en) 2001-03-28 2004-04-06 Advanced Micro Devices, Inc. Selective photoresist hardening to facilitate lateral trimming
US6774365B2 (en) 2001-03-28 2004-08-10 Advanced Micro Devices, Inc. SEM inspection and analysis of patterned photoresist features
US6815359B2 (en) 2001-03-28 2004-11-09 Advanced Micro Devices, Inc. Process for improving the etch stability of ultra-thin photoresist
KR100995313B1 (en) * 2008-02-28 2010-11-19 재단법인서울대학교산학협력재단 Fabricating method of mold for coloring body using nanoscale structure
JP2016127234A (en) * 2015-01-08 2016-07-11 株式会社アルバック Production method for resist structure

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002139842A (en) * 2000-11-01 2002-05-17 Fujitsu Ltd Pattern forming method and semiconductor device
US6774365B2 (en) 2001-03-28 2004-08-10 Advanced Micro Devices, Inc. SEM inspection and analysis of patterned photoresist features
WO2002080239A3 (en) * 2001-03-28 2002-12-12 Advanced Micro Devices Inc Process for forming sub-lithographic photoresist features
US6589709B1 (en) 2001-03-28 2003-07-08 Advanced Micro Devices, Inc. Process for preventing deformation of patterned photoresist features
US6630288B2 (en) 2001-03-28 2003-10-07 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features by modification of the photoresist surface
US6653231B2 (en) 2001-03-28 2003-11-25 Advanced Micro Devices, Inc. Process for reducing the critical dimensions of integrated circuit device features
US6716571B2 (en) 2001-03-28 2004-04-06 Advanced Micro Devices, Inc. Selective photoresist hardening to facilitate lateral trimming
WO2002080239A2 (en) * 2001-03-28 2002-10-10 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features
US6815359B2 (en) 2001-03-28 2004-11-09 Advanced Micro Devices, Inc. Process for improving the etch stability of ultra-thin photoresist
KR100836948B1 (en) 2001-03-28 2008-06-11 어드밴스드 마이크로 디바이시즈, 인코포레이티드 Process for forming sub-lithographic photoresist features
EP1372191A2 (en) * 2002-06-14 2003-12-17 Filtronic Compound Semiconductor Limited Method for depositing a device feature on a substrate
EP1372191A3 (en) * 2002-06-14 2004-04-07 Filtronic Compound Semiconductor Limited Method for depositing a device feature on a substrate
KR100995313B1 (en) * 2008-02-28 2010-11-19 재단법인서울대학교산학협력재단 Fabricating method of mold for coloring body using nanoscale structure
JP2016127234A (en) * 2015-01-08 2016-07-11 株式会社アルバック Production method for resist structure

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