JPH1197328A - Method for forming resist pattern - Google Patents

Method for forming resist pattern

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Publication number
JPH1197328A
JPH1197328A JP25218997A JP25218997A JPH1197328A JP H1197328 A JPH1197328 A JP H1197328A JP 25218997 A JP25218997 A JP 25218997A JP 25218997 A JP25218997 A JP 25218997A JP H1197328 A JPH1197328 A JP H1197328A
Authority
JP
Japan
Prior art keywords
resist
resist pattern
processed
pattern
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25218997A
Other languages
Japanese (ja)
Inventor
Yoshiaki Kitaura
Takashi Suzuki
浦 義 昭 北
木 隆 鈴
Original Assignee
Toshiba Corp
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP25218997A priority Critical patent/JPH1197328A/en
Publication of JPH1197328A publication Critical patent/JPH1197328A/en
Application status is Pending legal-status Critical

Links

Abstract

PROBLEM TO BE SOLVED: To make a high precision lift-off fine resist pattern with excellent resolution, by a method wherein, after first and second resist layers having different sensitivities are sequently formed on a processed substrate, exposure and development processes are performed to form a resist pattern. SOLUTION: After a resist film 3 is formed on a processed film of a processed substrate 1 such as a GaAs substrate, etc., in which a processed film such as SiO2 , etc., is formed, it is prebaked in a specified manner to carry out a crosslinking reaction. Next, after electron beams are irradiated on specified conditions and a space pattern of a specified dimension is drawn, a bake process after exposure is performed in the atmosphere by use of a hot plate at a specified temperature. Further, for example, the to-be-processed substrate is dipped in a developer based on tetraammonium hydroxide with alkali concentration 0.27, developing is performed to form a lift-off fine resist pattern 6. A resist layer of an upper layer with a large crosslinking rate is finished as a substantially prescribed dimension.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、リフトオフ用のレジストパターンを形成するレジストパターンの形成方法に関する。 The present invention relates to the method for forming a resist pattern for forming a resist pattern for lift-off.

【0002】 [0002]

【従来の技術】現在、GaAs集積回路の高集積化、高速化に伴い、リソグラフィー技術においては、微細でしかも寸法制御性に優れたレジストパターンの形成技術が要求されている。 At present, high integration of GaAs integrated circuits, along with the speed, in the lithography techniques, a technique for forming excellent resist pattern fine, yet dimensional controllability is required.

【0003】GaAs集積回路の配線には、オーミック金属との整合性から通常、Au系の金属が用いられている。 [0003] wiring GaAs integrated circuits, usually from the consistency between the ohmic metal, Au-based metal is used. しかし、この金属はRIE(Reactive Ion-Etchin However, the metal RIE (Reactive Ion-Etchin
g)法を用いて加工するのが極めて困難であり、加工にはリフトオフ法が用いられている。 g) method is extremely difficult to process using a lift-off method is used for the machining.

【0004】従来、このリフトオフ法を用いてレジストパターンを形成する場合には、イメージリバースレジストに染料が添加される。 Conventionally, when forming a resist pattern using the lift-off method, the dye is added to the image reverse resist. この染料が添加されたことによって、露光光(例えばg線)に対するレジストの透過率を大幅に低減させるとともにレジスト表面での光の吸収を大きくする。 By this dye has been added, to increase the absorption of light at the resist surface with greatly reduced resist transmittance to the exposure light (e.g., g-line). この状態でパターンを露光し、露光後にリバーサルベークを行い、現像処理することによってリフトオフに適した逆テーパ状のレジストパターンを形成していた。 Exposing a pattern in this state, subjected to reversal baking after exposure was to form a reverse tapered resist pattern suitable for lift-off by development.

【0005】 [0005]

【発明が解決しようとする課題】従来、上述のように、 [Problems that the Invention is to Solve] Conventionally, as described above,
リフトオフ用のレジストパターンを形成する場合は染料が添加されたイメージリバースレジストを用いられていた。 When forming a resist pattern for lift-off has been used an image reverse resist dye has been added. このイメージリバースレジスを用いて形成されたパターンは逆テーパ形状となるため、パターン寸法を微細化すると、パターン倒れ等が発生して解像性が著しく低下し、リフトオフ用の微細レジストパターンを形成するのが極めて困難となる問題が生じる。 Therefore the image pattern formed by using a reverse Regis a reverse tapered shape, the finer the pattern size, collapse etc. resolution is remarkably reduced in generation pattern, thereby forming a fine resist pattern for lift-off It arises the problem that is extremely difficult.

【0006】本発明は上記事情を考慮してなされたものであって、解像性に優れた高精度なリフトオフ用の微細なレジストパターンを形成することのできるレジストパターンの形成方法を提供することを目的とする。 The present invention was made in view of these circumstances, to provide a method of forming a resist pattern capable of forming a fine resist pattern for accurate lift-off with excellent resolution With the goal.

【0007】 [0007]

【課題を解決するための手段】本発明によるレジストパターンの形成方法は、被処理基板上に感度の異なる第1 Method of forming a resist pattern according to the invention According to an aspect of the first different sensitivities on the substrate to be processed
および第2のレジスト層を順次形成する工程と、露光および現像処理する工程と、を備えていることを特徴とする。 A and sequentially forming a second resist layer, characterized in that it and a step of exposing and developing process.

【0008】また、前記第1のレジスト層は被処理基板にレジストを塗布した後、第1の所定温度の雰囲気中でプリベークを行うことによって形成し、前記第2のレジスト層は前記第1のレジスト層上にレジストを塗布した後、前記第1の所定温度よりも低い第2の所定温度の雰囲気中でプリベークを行って形成するように構成しても良い。 Further, after the first resist layer is coated with resist on a substrate to be processed, in an atmosphere of a first predetermined temperature to form by performing prebaking, the second resist layer is the first a resist was applied onto the resist layer, in an atmosphere of said lower than the first predetermined temperature the second predetermined temperature may be configured to form prebaked.

【0009】 [0009]

【発明の実施の形態】本発明によるレジストパターンの形成方法の一実施の形態を図1を参照して説明する。 An embodiment of the method for forming a resist pattern according to the embodiment of the present invention will be described with reference to FIG. 図1は上記実施の形態のレジストパターン形成の工程断面図である。 Figure 1 is a process cross-sectional view of a resist pattern formed in the above embodiment.

【0010】まず被加工膜(例えばSiO 2 )が形成された被処理基板(例えばGaAs基板)1の上記被加工膜上に化学増幅系ネガ型電子線レジスト(例えばシプレー社製SAL601)を塗布し、例えば2μmの厚さのレジスト層3を形成する(図1(a)参照)。 Firstly coated film to be processed (e.g., SiO 2) chemical amplification negative type electron beam resist is treated substrate formed (for example, GaAs substrate) 1 of the film to be processed on (e.g. manufactured by Shipley SAL601) , for example, a resist layer 3 having a thickness of 2 [mu] m (see Figure 1 (a)). 続いて1 Followed by 1
45℃の雰囲気中で1分間程度のプリベークを行う。 Prebaked for about 1 minute in an atmosphere of 45 ° C.. 化学増幅系のレジストには酸が含まれており、ベークされると上記酸を触媒にして架橋反応が連続的に生じる。 The resist chemical amplification includes the acid, the crosslinking reaction by the acid catalyst occurs continuously when it is baked.

【0011】次に上記レジスト層上に、化学増幅系ネガ型電子線レジストを塗布し、例えば0.5μmの膜厚のレジスト層5を形成する(図1(b)参照)。 [0011] Then on the resist layer, by applying a chemical amplification negative electron beam resist, for example, a resist layer 5 of 0.5μm in thickness (see Figure 1 (b)). 続いて6 Followed by 6
5℃の雰囲気中で1分間程度のプリベークを行う。 Prebaked for about 1 minute in an atmosphere of 5 ° C..

【0012】次に加速電圧が50KVの電子線を用いて、照射量15μC/cm 2の条件でパターン寸法0.2 [0012] Next acceleration voltage by using an electron beam of 50 KV, pattern size 0.2 under the conditions of irradiation dose 15 .mu.C / cm 2
μmのスペースパターンを描画する(図1(c)参照)。 Drawing a space pattern of [mu] m (see FIG. 1 (c)). その後、115℃に設定されたホットプレートを用い、大気中で2分間程度の露光後ベーク処理を行う。 Then, using the set hotplate 115 ° C., performing post exposure baked for about 2 minutes in the air.

【0013】次に、例えばアルカリ濃度が0.27のテトラメチルアンモニュウムハイドロオキサイドベースの現像液中に上記被処理基板を10分間浸漬することにより現像処理を行い、リフトオフ用の微細レジストパターン6を形成する(図1(d)参照)。 [0013] Then, for example, the alkali concentration is followed by development with the substrate to be processed by immersing 10 minutes in the developer of tetramethyl methyl ammonium hydroxide-based 0.27, forming a fine resist pattern 6 for lift-off (refer to FIG. 1 (d)).

【0014】上述のように本実施の形態においては、下層のレジスト層3を比較的高温(例えば145℃)でプリベークし、上層のレジスト層5を比較的低温(例えば65℃)でプリベークしたことにより、下層レジストの架橋率が小さくなって感度が低くなり、また上層のレジスト層5の架橋率が大きくなって感度が高くなる。 [0014] It in the present embodiment as described above, the pre-baked lower resist layer 3 at a relatively high temperature (e.g. 145 ° C.), it was pre-baked resist layer 5 of the upper layer at a relatively low temperature (e.g. 65 ° C.) Accordingly, the sensitivity is lowered lower resist crosslinking rate becomes smaller, the sensitivity is high crosslinking ratio of the upper resist layer 5 is increased. この状態で露光し、現像した場合には、架橋率の小さい下層のレジスト層3の方が溶解速度が大きくなり、設計寸法(露光寸法)よりも仕上がり寸法が大幅に減少する(図1(c)、(d)参照)。 Exposed in this state, when development is dissolution rate towards the smaller lower resist layer 3 having the crosslinking rate is increased, the finished dimension than the design dimension (exposure dimension) is significantly reduced (FIG. 1 (c ), (d) reference). しかし架橋率の大きい上層のレジスト層ではほぼ設計寸法通りに仕上がる。 However it finished large almost design dimension as the upper resist layer of crosslinking ratio. このため、パターン倒れが生じぜず解像性に優れた高精度なリフトオフ用の微細なレジストパターンを形成することができる。 Therefore, it is possible to form a fine resist pattern for accurate lift-off pattern collapse was excellent resolution without ze occur.

【0015】なお、上記実施の形態においてレジスト層3のプリベーク温度としては140〜150℃の範囲であれば同様の効果を得ることができる。 [0015] Note that the pre-baking temperature of the resist layer 3 in the above embodiment can obtain the same effect as long as the range of 140 to 150 ° C.. またレジスト層5のプリベーク温度としては60〜70℃の範囲であれば同様の効果を得ることができる。 As the pre-bake temperature of the resist layer 5 can achieve the same effect as long as the range of 60 to 70 ° C..

【0016】なお、上記実施の形態においては、レジストとして化学増幅系がネガ型電子線レジストを用いたが、化学増幅系に限らず、電子線に感度を有するネガ型レジストを用いても良いことは云うまでもない。 [0016] In the above embodiment, although chemically amplified system using a negative type electron beam resist as a resist is not limited to the chemical amplification, may also be using a negative resist having a sensitivity to an electron beam it is needless to say is.

【0017】 [0017]

【発明の効果】以上述べたように本発明によれば、解像性に優れた高精度なリフトオフ用の微細なレジストパターンを形成するとができる。 According to the present invention as described above, according to the present invention, it is to form a fine resist pattern for accurate lift-off with excellent resolution.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明によるレジストパターンの形成方法の一実施の形態の構成を示す工程断面図。 Sectional views illustrating the configuration of an embodiment of a method for forming a resist pattern according to the invention; FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 被処理基板 3 レジスト層 5 レジスト層 6 レジストパターン 1 the processed substrate 3 resist layer 5 resist layer 6 resist pattern

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】被処理基板上に感度の異なる第1および第2のレジスト層を順次形成する工程と、 露光および現像処理する工程と、 を備えていることを特徴とするレジストパターンの形成方法。 1. A forming the first and second resist layer different speeds on the substrate to be processed sequentially, the resist pattern forming method characterized by comprising the the steps of exposure and development process .
  2. 【請求項2】前記第1のレジスト層は被処理基板にレジストを塗布した後、第1の所定温度の雰囲気中でプリベークを行うことによって形成し、前記第2のレジスト層は前記第1のレジスト層上にレジストを塗布した後、前記第1の所定温度よりも低い第2の所定温度の雰囲気中でプリベークを行って形成することを特徴とする請求項1記載のレジストパターンの形成方法。 Wherein after the first resist layer is coated with resist on a substrate to be processed, formed by performing prebaking in an atmosphere of a first predetermined temperature, the second resist layer is the first after a resist is applied to the resist layer, the first method of forming a resist pattern according to claim 1, wherein the formed prebaked in an atmosphere of a second predetermined temperature lower than a predetermined temperature.
  3. 【請求項3】前記レジスト層の形成にネガ型電子線レジストが用いられることを特徴とする請求項1または2記載のレジストパターン形成方法。 3. A resist pattern forming method according to claim 1 or 2, wherein the negative electron beam resist is used for forming the resist layer.
JP25218997A 1997-09-17 1997-09-17 Method for forming resist pattern Pending JPH1197328A (en)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002139842A (en) * 2000-11-01 2002-05-17 Fujitsu Ltd Pattern forming method and semiconductor device
WO2002080239A2 (en) * 2001-03-28 2002-10-10 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features
US6589709B1 (en) 2001-03-28 2003-07-08 Advanced Micro Devices, Inc. Process for preventing deformation of patterned photoresist features
US6653231B2 (en) 2001-03-28 2003-11-25 Advanced Micro Devices, Inc. Process for reducing the critical dimensions of integrated circuit device features
EP1372191A2 (en) * 2002-06-14 2003-12-17 Filtronic Compound Semiconductor Limited Method for depositing a device feature on a substrate
US6716571B2 (en) 2001-03-28 2004-04-06 Advanced Micro Devices, Inc. Selective photoresist hardening to facilitate lateral trimming
US6774365B2 (en) 2001-03-28 2004-08-10 Advanced Micro Devices, Inc. SEM inspection and analysis of patterned photoresist features
US6815359B2 (en) 2001-03-28 2004-11-09 Advanced Micro Devices, Inc. Process for improving the etch stability of ultra-thin photoresist
KR100995313B1 (en) * 2008-02-28 2010-11-19 (주)이모트 Fabricating method of mold for coloring body using nanoscale structure
JP2016127234A (en) * 2015-01-08 2016-07-11 株式会社アルバック Production method for resist structure

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002139842A (en) * 2000-11-01 2002-05-17 Fujitsu Ltd Pattern forming method and semiconductor device
US6716571B2 (en) 2001-03-28 2004-04-06 Advanced Micro Devices, Inc. Selective photoresist hardening to facilitate lateral trimming
WO2002080239A3 (en) * 2001-03-28 2002-12-12 Advanced Micro Devices Inc Process for forming sub-lithographic photoresist features
US6589709B1 (en) 2001-03-28 2003-07-08 Advanced Micro Devices, Inc. Process for preventing deformation of patterned photoresist features
US6630288B2 (en) 2001-03-28 2003-10-07 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features by modification of the photoresist surface
US6653231B2 (en) 2001-03-28 2003-11-25 Advanced Micro Devices, Inc. Process for reducing the critical dimensions of integrated circuit device features
KR100836948B1 (en) 2001-03-28 2008-06-11 어드밴스드 마이크로 디바이시즈, 인코포레이티드 Process for forming sub-lithographic photoresist features
WO2002080239A2 (en) * 2001-03-28 2002-10-10 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features
US6815359B2 (en) 2001-03-28 2004-11-09 Advanced Micro Devices, Inc. Process for improving the etch stability of ultra-thin photoresist
US6774365B2 (en) 2001-03-28 2004-08-10 Advanced Micro Devices, Inc. SEM inspection and analysis of patterned photoresist features
EP1372191A3 (en) * 2002-06-14 2004-04-07 Filtronic Compound Semiconductor Limited Method for depositing a device feature on a substrate
EP1372191A2 (en) * 2002-06-14 2003-12-17 Filtronic Compound Semiconductor Limited Method for depositing a device feature on a substrate
KR100995313B1 (en) * 2008-02-28 2010-11-19 (주)이모트 Fabricating method of mold for coloring body using nanoscale structure
JP2016127234A (en) * 2015-01-08 2016-07-11 株式会社アルバック Production method for resist structure

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