JPH02231705A - Developing method - Google Patents

Abstract

PURPOSE:To improve resolution at the time of exposure and pattern-size controlling accuracy by performing exposures in multiple steps by using resist having the same quality. CONSTITUTION:Far ultraviolet rays 1 are projected on a substrate 4 on which resist is thinly applied. Then, exposed energy distribution which is recognized at a part 2 where the resist is not exposed and a part 3 where the resist is exposed is formed in the resist. Resist is applied thereon so that the film thickness required for keeping accuracy in etching is obtained. Far ultraviolet rays 6 having the same pattern as the far ultraviolet rays 1 are projected. Then, exposed energy distribution which is recognized at a part 7 where the resist is not exposed and a part 8 where the resist is exposed is formed in the resist. When development is performed, a resist pattern 11 is formed on the substrate 12. In this way, high resolution and excellent pattern-size controllability which are the advantages obtained from the thin resist film are obtained. The resist pattern characterized by the film thickness required for keeping accuracy in etching, high resolution and high accuracy can be formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a developing process used in integrated circuit manufacturing.
In particular, it relates to a developing method that improves the resolution during exposure and the accuracy of control of batten dimensions. [Prior Art] Generally, in the development process used in integrated circuit manufacturing, a resist of a thickness necessary to maintain accuracy during etching is applied onto the wafer, and a mask button is exposed and developed to form the wafer. A resist pattern is formed on top.

[Problem to be solved by the invention]

The conventional development method described above requires a thick resist film to maintain the accuracy of batten dimensions during etching, but conversely, the thicker the resist film is during development, the lower the resolution and the worse the batten dimension control accuracy. VLSITECHNOLOGY (Edit
d By Sze, McGRAW-HILLINT
ERNATIONAL BOOK COMPANY))
.

[Means to solve the problem]

The developing method of the present invention includes the steps of applying a thin resist on a wafer and exposing it to light, then applying the resist to a film thickness required for etching, exposing the wafer again, and then developing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the main steps of the developing process in one embodiment of the present invention. According to this embodiment, in step 1, when the substrate 4 coated with a thin resist is irradiated with the far ultraviolet light 1, the exposure energy distribution seen in the resist unexposed areas 2 and the resist exposed areas 3 is formed in the resist. . At the beginning of the process, a resist is applied on top of it to the required film thickness to maintain accuracy during etching, and when deep ultraviolet light 6 with the same pattern as deep ultraviolet light 1 is irradiated, the unexposed areas 7 of the resist and the exposed resist are irradiated. The exposure energy distribution seen in section 8 is the resist. formed within. When it is developed in step 1, a resist pattern 11 is formed on the substrate 12. FIG. 2 is a process diagram showing a conventional technique of the developing process shown in FIG. According to the conventional technology, in step 1, when far ultraviolet light 14 is irradiated onto a substrate 17 coated with a resist of a thickness necessary to maintain batting accuracy during etching, unexposed resist areas 15 and exposed resist areas 16 are exposed. An exposure energy distribution seen in the resist is formed in the resist. When it is developed in step (2), a resist pattern 19 is formed on the substrate 20.

According to this embodiment, while taking advantage of the thin resist film seen during development, the film thickness required during etching can be obtained at the same time. Therefore, the standing wave effect, which is a problem in optical lithography, is alleviated, and a decrease in batten dimension accuracy due to the thickness of the resist film can be prevented, and high resolution and excellent batten dimension controllability can be obtained.

FIG. 3 is a diagram showing the main steps of the developing process in another embodiment of the present invention. According to this embodiment, in step 1, when the electron beam 22 is incident on the substrate 25 coated with a thin resist, the exposure energy distribution seen in the resist unexposed area 23 and the resist exposed area 24 is formed in the resist. . In the process, a resist is applied on top of it to a thickness necessary to maintain accuracy during etching, and when an electron beam 27 with the same pattern as 22 is incident, a resist is seen in the unexposed areas 28 and exposed areas 29 of the resist. An exposure energy distribution is formed in the resist, which is developed in step 34 to form a resist pattern 32 on the substrate 33.

FIG. 4 is a process diagram showing a conventional technique of the developing process shown in FIG. According to the conventional technology, in step It, when the electron beam 35 is incident on the substrate 38 coated with a resist of a thickness necessary to maintain batting accuracy during etching, the resist unexposed portion 36 and the resist exposed portion 37 are exposed. A visible exposure energy distribution is created in the resist. When it is developed with process soil 1, a resist pattern 4o is formed on the substrate 41.

According to this embodiment, while taking advantage of the thin resist film seen during development, it is possible to obtain the required film thickness during etching at the same time. Therefore, it is possible to prevent the scattering effect from the substrate, which is a problem in electron beam lithography, and it is possible to obtain high resolution and excellent batten size controllability.

〔Effect of the invention〕

As explained above, in the present invention, first, a wafer coated with a thin resist is exposed. This provides high resolution and excellent pattern size controllability, which are advantages of a thin resist film. Next, a resist of a thickness necessary to maintain batten dimensional accuracy during etching is applied over the resist, and the resist is exposed and developed using the same batt. This makes it possible to form a resist pattern with a large film thickness, high resolution, and high accuracy necessary to maintain accuracy during etching.

[Brief explanation of the drawing]

FIG. 1 is a main process diagram of a developing process according to an example of the present invention. 1.6...Deep ultraviolet light, 2,7...Resist unexposed area, 3,8...Resist exposed area, 4
, 9.12...Substrate, i, upper l...Exposure step, 11...Afterimage resist, flattening...
・Development process. FIG. 2 is a process diagram showing a conventional technique of the developing process shown in FIG. l4...Deep ultraviolet light, 15...Resist unexposed area, l6...Resist exposed area, 17.2
0...Substrate, 18...Exposure process, 19
...Afterimage resist, iL...Development process. FIG. 3 is a diagram showing the main steps of the developing process in another embodiment of the present invention. 22.27...Electron beam, 23.28...
・Resist unexposed area, 24.29... Resist exposed area, 25, 30.33... Substrate, 1st process, main top... Exposure process, 32... ... Afterimage resist, 34... Development process. FIG. 4 is a process diagram showing a conventional technique of the developing process shown in FIG. 35...Electron beam, 36...Resist unexposed area, 37...Resist exposed area, 38.41
...Substrate, ■...Exposure process, 40...
...Afterimage resist, process...Development process. Agent: Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A developing method that is characterized by multiple exposures using a resist of the same quality in the developing process, which is one of the integrated circuit manufacturing processes.