GB2442030A - Resist exposure and patterning process - Google Patents
Resist exposure and patterning process Download PDFInfo
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- GB2442030A GB2442030A GB0618425A GB0618425A GB2442030A GB 2442030 A GB2442030 A GB 2442030A GB 0618425 A GB0618425 A GB 0618425A GB 0618425 A GB0618425 A GB 0618425A GB 2442030 A GB2442030 A GB 2442030A
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- 238000000034 method Methods 0.000 title claims abstract description 91
- 238000000059 patterning Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- 238000011161 development Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 18
- 230000035945 sensitivity Effects 0.000 claims description 13
- 230000001419 dependent effect Effects 0.000 claims 2
- 230000008021 deposition Effects 0.000 abstract description 7
- 238000001465 metallisation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 92
- 229920002120 photoresistant polymer Polymers 0.000 description 30
- 235000012431 wafers Nutrition 0.000 description 21
- 230000008020 evaporation Effects 0.000 description 7
- 238000001704 evaporation Methods 0.000 description 7
- 239000002356 single layer Substances 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 239000002131 composite material Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000002904 solvent Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000001883 metal evaporation Methods 0.000 description 2
- 238000000879 optical micrograph Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
A method is disclosed for forming a multi-layer resist structure on a substrate having a controlled and pre-determined amount of undercut or overcut according to whether a positive or negative tone resist is used. The amount of undercut or overcut is controlled by means of a predetermined level of pre-exposure of each underlying resist layer prior to deposition of the next resist layer and the final patterning of the top resist layer. The multi-layer resist is then developed to remove resist in a controlled manner from each layer according to the degree of exposure of the resist. Using the technique, multi-layer resist structures having very fine sub-micron details are formed. Multi-layer positive tone resist structures can be employed as a mask and combined with metal deposition and lift-off techniques for fabricating very high resolution metallic features.
Description
RESIST EXPOSURE AND PATTERNING PROCESS
Field of the Invention
The present invention relates to a process for exposing and patterning resist, and in particular a multilayer resist exposure process suitable for use with lift-off fabrication techniques.
Background to the Invention
Resists, such as photoresist, are widely used for producing templates or patterns on a substrate, which can either be transferred to an underlying layer or else provide a mask for a structure to be built on the substrate or detached therefrom.
The structures fabricated in this way often form part of a device, such as an electronic or photonic device. Typically, the resist is patterned using standard techniques such as contact mask or stepper lithography and is then developed to leave behind a resist mask" which is used to fabricate the desired structure.
Many techniques exist for removing the developed resist to leave behind the desired structure, but of particular interest here are metal structures formed by so-called lift-off" techniques in which resist is applied to a substrate, patterned and developed before metal is deposited over the resist structure, by evaporation for example. In the actual lift-off step the remaining resist is removed, together with any metal deposited on it, leaving behind a desired metal structure. This can work well for larger scale features.
However, one problem associated with this technique, particularly when fabricating small-scale features, has been residual unwanted metal left behind after lift-off. During the process there is a tendency for small amounts of metal to coat the side walls of the developed resist above desired metal feature, resulting in walls or wings' of residual metal being left attached to the feature after lift-off. The problem is particularly apparent when a single layer of positive tone resist is used. Such resists are generally preferred for these applications. Due to penetration through the layer of resist, the upper regions of the resist tend to experience greater exposure than the lower regions and so offer commensurately less resistance to subsequent development, leading to more resist material being removed leaving behind an opening with slanted sides facing outwards. As a result, there is a greater tendency for wings' of residual metal to be left attached to the desired metal feature after lift-off.
A particular approach to solving the problem of unwanted residual metal has been to produce a developed resist mask having some form of overhang with an * associated uundercutu. These so-called "undercuts' in the region of the openings are not filled by the metal during deposition and their presence reduces the likelihood of walls or wings of residual metal after lift-off, thus leading to cleaner' edges to the metal features left behind. A number of techniques have been employed to produce such undercuts.
A simple form of overhang can be realised by generating openings in the resist with slanted sides that face inwards. One way to do this has been to harden the surface of a single layer of positive tone resist by soaking the sample in a suitable solvent or else by using a deep UV exposure. The usual procedure is then followed, but the developed resist exhibits slight "overhangs' or lips at the edges of the openings. These overhangs help to prevent unwanted wings of metal, but are not completely effective. An alternative technique is to employ a single layer of a negative resist, which naturally gives rise to an overhang due to its inverse response to exposure and subsequent development. The process works reasonably well but requires the less common negative tone type of resist and may not be suitable for producing more complex structures. Moreover, the exposure and development of the negative tone resist can be quite slow, particularly as the majority of the resist surface must be exposed, with only the areas where the features are to be formed being masked off.
A more recent technique is to use a bi-layer resist comprising two different types of positive or negative tone resist located one on top of the other. The process is particularly well suited to positive tone resists, although negative tone resists may also be used. In this process, the resists are chosen to have different sensitivity such that they respond differently to pattern exposure and subsequent development. With positive tone resists, an undercut feature can be achieved by employing a resist for the lower layer with a lower resistance to development after pattern exposure. The process allows for greater control over the resist mask and therefore the feature to be formed. A disadvantage of this bi-layer resist process is that two different, but suitable resist materials must be identified. Also, it is usually necessary to employ resists with different solvents and chemistries in order to avoid intermixing, which can make the process inconsistent and lessen repeatability. Moreover, the overall processing time can be long, making it less economically viable for large-scale chip production.
Thus, as will be appreciated, there is a need for an alternative resist patterning process and, in particular, a process which facilitates reliable and repeatable fabrication of sub-micron features on a substrate by lift-off, whilst minimising the associated cost and complexity of the overall process.
Summary of the Invention
According to a first aspect of the present invention, a method for fabricating a patterned resist on a substrate comprises the steps of: depositing a first layer of a first resist on the substrate; exposing the first layer of the first resist to a predetermined level of exposure; depositing a second layer of a second resist over the pre-exposed first layer of the first resist, the second resist having substantially the same sensitivity to exposure as the first resist; and, patterning at least the second layer of resist by exposure.
Preferably, the first resist and the second resist are characterized by substantially the same chemistry for post-exposure development. This only allows development of the patterned two-layer resist using a single developing process.
More preferably, the first resist and the second resist are the same. This guarantees identical sensitivity of the two layers and an identical chemistry to subsequent development.
Preferably, the step of exposing the first layer of resist is performed uniformly across at least region of the resist to be patterned.
The resist used for each of the first and second layers may be a positive tone resist or a negative tone resist. Both types of resist can be used to produce a three-dimensional negative image of, and therefore a mask for, a desired final structure.
Positive tone resist is more suitable for a desired final structure with features that reduce in lateral dimension with distance from the substrate, whilst a negative tone resist is more suitable for a desired final structure with features that increase in lateral dimension with distance from the substrate. However, positive tone resist is preferred for many applications, including lift-off processes, due to the greater range of resist materials, faster processing time and reduced complexity as compared to negative tone resist. With positive tone resist, the patterning step involves exposing only those regions of the resist corresponding to a desired structure to be produced, thus making it very amenable to patterning by E-beam. With broad area exposure techniques, such as a stepper, overall patterning times are similar for positive and negative tone resist.
As will be appreciated, in the process of the present invention, a substantially similar or identical resist material is used for the two layers, but the first layer of resist is pre-sensitized or pre-hardened, preferably uniformly, towards subsequent development, according to whether a positive or negative tone resist is used.
Therefore, when the composite two-layer resist is subsequently patterned, there is a * differential response between the first layer and second layer of resist, thereby negating the need for two complimentary resists having different sensitivity.
As will be appreciated, the process may be extended to include further intermediate layers of pre-exposed resist.
Preferably, prior to depositing the second layer of the second resist, the method further comprises the steps of depositing a third layer of a third resist on the pre-exposed first layer of resist, the third resist having substantially the same sensitivity to exposure as the first and second resists; and, exposing the third layer of resist to a predetermined level of exposure.
Preferably, the third resist is characterized by substantially the same chemistry for post-exposure development as the first and second resists. More preferably, the first, second and third resists are the same.
Preferably, the step of exposing the third layer of resist is performed uniformly across the resist.
In this way, a further pre-sensitized or pre-hardened layer of a similar or identical resist is applied prior to deposition of the second layer of resist and subsequent patterning. Of course, an intermediate fourth layer of resist having substantially the same sensitivity could be deposited on the intermediate third layer and pre-exposed prior to deposition of the second layer, and these steps could be repeated with intermediate fifth, sixth and further layers of resist.
For the development process to remove the full thickness of positive-tone resist in a given region, that region must have received a clearing exposure dose sufficient to fully expose the resist through its depth. Preferably, the step of patterning comprises exposing regions of the second layer of resist to a level of exposure that is at least a clearing dose sufficient to fully expose at least the second layer of the second resist through its depth. In this way, a final exposure, which varies spatially across the surface of the composite multi-layer resist, pre-disposes it to forming a desired resist pattern when subsequently developed.
If each of the lower lying resist layers has been exposed to less than a clearing dose during its respective pre-exposure step, the patterning exposure may provide the additional exposure required to fully expose regions of the underlying layers of resist through their depth. This provides greater control over the degree of undercut that may be achieved during subsequent development. Alternatively, removal of resist in the lower lying layers can be assured if each layer is exposed to at least its clearing dose during its respective pre-exposure step. However, removal * of resist from these lower layers is then controlled by the duration of the development step, and there is a risk that too large an area of resist will be removed Preferably, the step of patterning further comprises developing the multi-layer resist to remove resist. With a positive tone resist the development process removes resist from areas subjected to the patterning exposure. With a negative tone resist the development process removes resist from between the areas subjected to the patterning exposure.
The development step yields a complex multilayer resist structure. For a positive tone resist the differential response leads to an undercut in the patterned regions of the multilayer resist, with a greater area of resist removed from a given layer the closer the layer is to the substrate. For a negative tone resist the differential response leads to an overcut, with a greater area of resist removed from a given layer the further the layer is from the substrate.
According to a second aspect of the present invention, a method for fabricating features on a substrate comprises the steps of: fabricating a patterned resist on the substrate using the method according to the first aspect, wherein the step of patterning comprises developing the resist; depositing a material over regions of the substrate from which the resist has been removed; and, then removing the remaining resist from the substrate.
In this way the developed multilayer resist acts as a mask for fabricating a structure on the substrate comprising features formed from the deposited material.
Typically, material is only deposited over areas of the substrate defined by the opening in the second layer of resist. However, if desired, the material may fill up the voids in the remaining resist, for a positive tone resist, including the undercut regions.
Removal of the remaining resist from the substrate, including any of the material attached to the resist, leaves behind a largely clean substrate with the exception of the desired features formed from the material deposited on the substrate through the voids in the resist.
Preferably, the remaining resist is removed by a lift-off process.
Preferably, the material is a metal. A layer of the metal may be deposited by any suitable technique, including evaporation.
As will be appreciated by those skilled in the art, the use of one or more resist materials of very similar or identical sensitivity and development chemistry, combined with the pre-exposure of lower lying layers of the resist, negates the need to find different resist materials having the correct relative sensitivities and compatibility in terms of the exposure and development processes to be employed. As such, the
S
* method according to the present invention provides a simple, cost effective method of forming a patterned resist that can be combined with standard metal deposition and lift-off techniques to form well-defined and complex multi-layer metallic structures on a substrate.
Brief Description of the Drawings
Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which: Figure 1 shows a known patterning and lift-off process with a single layer positive tone resist; Figure 2 shows a known patterning and lift-off process with a single layer negative tone resist; Figure 3 shows a known patterning and lift-off process with a bi-layer of two different resists; Figure 4 shows a patterning and lift-off process with a two-layer positive tone resist according to the present invention; Figure 5 shows a patterned threelayer positive-tone resist; Figure 6 shows a patterned three-layer negative- tone resist; Figure 7 shows the percentage of resist thickness remaining after development versus the resist exposure dose; Figure 8 shows the exposure dose matrix for two sample wafers (Wi and W2), each having a 5 x 5 array of chips; and, Figures 9A-9E illustrate some of the metal structures fabricated by patterning wafers WI and W2, followed by metal evaporation and lift-off.
Detailed Description
Figure 1 illustrates a known process for fabricating metallic features on a substrate with single layer positive tone resist lift-off. After deposition of a layer of positive tone photoresist on a substrate, the resist is patterned by exposure, as shown in Fig. 1(a), and subsequent development, as shown in figure 1(b), leading to openings.or voids in the resist, which extend to the surface of the substrate. A film of metal is then deposited by evaporation or other means, as shown in figure 1(c), covering the surface of the residual photoresist and also a region of the substrate exposed by the opening in the photoresist. Finally, the residual developed photoresist is removed by lift-off, leaving behind the desired metal feature, as shown in figure 1(d).
* In this case, the whole depth of the patterned resist has received a "flood dose" of exposure, which ensures that resist material is uniformly removed throughout its depth, yielding voids in the developed resist having vertical sidewalls.
However, if the level of exposure of the resist is such that lower lying regions do not receive the "flood dose", then the sidewalls of the voids in the resist may taper outwards towards the upper surface after development, which can lead to a corresponding trapezoidal-shaped metallic feature in vertical cross-section.
The above process works well for larger features of transverse dimension =5im, but for smaller scale features there tends to be unwanted residual metal left after lift-off in the form of extensions to the sidewalls of the desired metallic features.
In the case of a trapezoidal-shaped features, these may appear as "wings" extending from the sidewalls of the features.
Figure 2 illustrates a similar known process for fabricating metallic features on a substrate with single layer resist lift-off, which reduces the likelihood of unwanted residual metal. The process employs a negative tone resist and aims to exploit the opposite trapezoidal shaped voids that can be produced using a negative tone resist and graded exposure through the depth of the resist. After deposition of a layer of negative tone photoresist (PR) on a substrate, the resist is patterned by exposure, as shown in figure 2(a), and subsequent development, as shown in figure 2(b), leads to openings in the resist with an angled undercut. A film of metal is then deposited by evaporation or other means, as shown in figure 2(c), covering the surface of the residual photoresist and also a region of the substrate exposed by the opening in the photoresist. Finally, the residual developed photoresist is removed by lift-off, leaving behind the desired metal feature having well-defined sidewalls, as shown in figure 2(d).
Figure 3 illustrates the latter stages of another known process for fabricating metallic features on a substrate with resist lift-off using a bi-layer process. Initially, a bi-layer resist comprising two different types of resist is deposited on a substrate.
The bi-layer resist comprises a lower underlayer and an upper layer of photoresist (PR), which is precisely patterned by exposure in the manner shown in Figure 1(a).
Subsequent development with different solvents leads to a patterned resist mask with well-defined openings in the upper PR layer and a clear undercut in the underlayer.
A metal film is then deposited, as shown in figure 3(c), covering the surface of the residual photoresist and also a well-defined region of the substrate exposed by the opening in the photoresist. Finally, the residual developed photoresist is removed by lift-off, together with any metal attached to it, leaving behind the desired metal feature, as shown in figure 3(d).
* The bi-layer technique shown in figure 3 works reasonably well and allows fabrication of small-scale features. However, the technique is cumbersbme and requires that two matching resists with different sensitivities and compatible developers be identified. Moreover, the amount of undercut in the uncierlayer is not very controllable and depends on the type of resist.
In the present invention, the two problems identified above are addressed by employing a lower resist layer and an upper resist layer having very similar sensitivity and that are compatible in terms of development after exposure. Furthermore, by changing a few exposure parameters, the amount of undercut in the lower resist layer can be controlled. The basic concept is illustrated in figure 4; where a bilayer of positive tone resist is formed, comprising a lower layer of resist (Resist-I) and an upper layer of resist (Resist-2) having substantially the same sensitivity and development chemistry. This latter requirement can best be guaranteed by using the same resist matenal for both layers.
The lower layer of resist (resist-I) is first spun onto a substrate and then the whole wafer uniformly pre-exposed using a suitable energy source (UV light, E-beam or the like) to a certain, completely controllable degree, as shown in figure 4(a). This pre-sensitizes the resist to subsequent exposure and development. Subsequently, an upper layer of resist (Resist-2) is spun over the surface of the pre-exposed lower layer, after which the composite bi-layer resist is patterned to produce the desired pattern by controlled exposure using either a stepper or E-beam (for high resolution patterns), as shown in figure 4(b). The patterning pre-disposes regions of the resist bi-layer to removal during subsequent development, with the lateral extent varying between the two layers, as illustrated by the shaded regions in figure 4(b). As will be apparent from figure 4(c), it is these regions of the composite bi-layer resist that are removed during development, giving rise to an undercut in the lower resist-I layer.
The extent of this undercut (U) can be pre-determined and controlled by appropriate selection of the level of energy density to which resist-I is pre-exposed.
As illustrated in figure 4(c), the next step in the process is the deposition of a layer of metal. A substantially uniform layer of metal of thickness t is deposited by evaporation over the surface of resist-i and over the surface of those regions of the substrate exposed by the voids created in the resist by development. A thinner layer of metal will also typically be deposited on the sidewalls of the resist in the regions of the voids. However, due to the undercut, these sidewalls of metal do not extend to the metal deposited on the substrate, which forms the desired feature. The lateral extent of metal feature is largely determined by the size of the opening in the resist, but the feature will generally have a slight trapezoidal shape due to its finite depth * and the presence of the undercut. Nevertheless, the process allows for sufficiently precise definition of features at the sub-micron level In the final step, liftoff is used to remove the remaining resist and any metal attached to it, leading to a wafer having the desired metallic features, as shown in figure 4(d). The technique is quite general and could be applied to a variety of resist types for various applications.
The technique can be extended to produce a composite multi-layer patterned resist having more than two layers of similar or identical resist. Typically, each lower lying layer will be pre-exposed to a particular extent prior to the next layer of resist being spun onto it. In this way, each lower layer can be pre-sensitized to a different degree. Only after the final, upper layer of resist has been deposited is the composite resist patterned and then developed. Figure 5 shows a three-layer resist comprising a common positive tone resist that has been processed and patterned in this way. The openings in Resist-3 largely define any features subsequent fabricated, but the stepped undercuts in Resist-2 and Resist-I will also play a role. Negative tone resists can also be used to make similarly patterned multilayer resist. Figure 6 shows an example of a three-layer resist comprising a common negative tone resist.
Due to the pre-hardening effect of pre-exposure on negative-tone resist, a similar patterning exposure to that used to produce the final resist of figure 5 actually leads to the inverse of this structure, as shown in figure 6. Such patterned negative-tone multi-layer resist will not generally be used with lift-off processes, but may have other practical applications.
To demonstrate practical operation of the present Invention, a real experimental batch was set up and processed, as will be explained in the following.
Two 6-inch silicon wafers were chosen as substrate and were cleaned in fuming nitric acid. These wafers are identified as Wi and W2. Prior to the actual process, a control silicon wafer was cleaned and spun with O.8pm of SPR-660 photoresist to determine its clearing dose in the developer. The clearing dose is that energy density of exposure required to fully expose the photoresist throughout its depth such that the subsequent development process removes the full depth of resist. SPR- 660 is an i-Line photoresist from Shipley suitable for O.35pm design rules, according to the manufacturers data sheet. The wafer was subjected to flood exposure in an i-Line Stepper with doses ranging from 40-I 5OmJ/cm2.
Figure 7 shows the results obtained, plotting the percentage of photoresist thickness remaining after the standard development for this photoresist against the varying exposure dose. As can be seen, for exposure doses of less than about 75 mJ/cm2 the full thickness of photoresist remains, whereas for a dose in excess of I 2OmJ/cm2, the photoresist appears to be fully removed. Based on these results, * and to ensure that the applied clearing dose is sufficient (allowing for variations), a clearing dose of l5OmJ/cm2was selected as the baseline for the rest of the test.
Both wafers WI and W2 were spun with 0.Bpm SPR660e photoresist and were baked on a hot-plate at 120 C for 2 minutes. Each wafer was characterized by a 5 x 5 array of chips, as shown in figure 8. Using an i-Line Stepper, the wafers were subjected to flood exposure according to the exposure matrix shown in figure 8.
Chips in the same column (Dl -D5) were exposed to the same dose, thereby allowing the reliability and repeatability of the process to be assessed. Along each row (RI- R5) the chips were exposed to an increasing level of flood exposure in the range 40- 75mJ/cm2 and 90-l5OmJIcm2 for Wi and W2, respectively. For comparison purposes, the exposure doses are also expressed as a percentage of the selected baseline clearing dose.
Following the flood exposure, a second layer of SPR-660, Resist-2, was spun onto wafers Wi and W2 and baked in the usual manner. The two wafers were subjected to pattern exposure using an available reticle in an i-Line ASML stepper, to pattern the bi-layer of photoresist, and were then baked at 110 C for 90 seconds, after which they were developed in standard automatic developer for SPR-660 photoresist.
After development, the wafers were hard-baked at 120 C for 2 minutes on a hot-plate just prior to metal evaporation and, subsequently, a 250nm layer of pure aluminium (Al) was evaporated onto the wafers. The wafers were kept static during the evaporation process and in an orientation perpendicular to the metal vapour.
Although it was not performed in this particular case, a short descum in a plasma asher is recommended before the evaporation in order to remove all potential resist residuals from the developed areas and leave a clean surface.
A lift-off process to remove the remaining photoresist and any attached metal was carried out in a hot acetone bath at 54 C. The results were very encouraging, as the metal layer started off to lift as soon as the wafers were dipped into the bath.
After 10 minutes, approximately 90% of the photoresist and attached metal had been removed from the areas not exposed during patterning to leave the metal patterns in the regions that had been exposed during patterning. To assist removal of the unwanted layers from the un-exposed regions, acetone in the bath was gently agitated. At this stage, the metal patterns, particularly the larger ones, were clearly visible by the naked eye. The wafers were removed from the bath after 30 minutes, and were immediately rinsed with pure acetone and then PA, and were finally blow-dried to leave a clean surface.
* Figure 9A shows an optical microscope image of some of the patterns formed on wafer WI using the new technique followed by lift-off. The samples shown in figure 9A were taken from a chip that had been exposed to the low 4OmJ/cm2 (27% of baseline) flood exposure. As can be seen, the wafer surface appears completely clean and free of resist and metal in the regions not exposed during patterning. The minimum nominal feature size visible is in this image is 2.5pm. The effect of the new exposure and lift-off technique on the fabrication of smaller feature sizes can more clearly be seen in figure 9B, which shows an optical microscope image of L-Bar patterns formed on wafer W2 in the chip area exposed to a flood exposure dose of lO5mJ/cm2 (70% of baseline). Minimum nominal line-width for L-Bars clearly visible in this image is 0.8pm.
Comparing the results obtained over the full range of flood exposure doses, 4OmJIcm2 (27% of baseline) to l5OmJ/cm2(100% of baseline), revealedthat the new technique worked successfully for all ranges tried in the experiment. It was not possible to accurately determine the precise amount of under-cut present in Resist-i, using either an optical microscope or a scanning electron microscope (SEM), due to the poor visible contrast between the two resists. To quantify this parameter (U in figure 4(c)) more accurately, special patterns must be designed and included in the reticle.
The real challenge for lift-off techniques using present state-of-the-art technology is to carry it out for very small features. Figures 9C to 9E show SEM images of some small features fabricated on WI using the technique of the present invention. In figure 9C, the nominal width of the metal bar in the centre of the image is 1pm, and that of the squares and triangles is 2pm. As can be seen, patterns are well defined and no residual of metal is visible in the regions not exposed during patterning. Figure 9D shows a 1pm cross pattern fabricated using the new technique. Figure.9E shows an image of L-Bars with nominal width of 0.4pm, which is the ultimate resolution guaranteed by the manufacturer of the stepper using to create the patterns. For features smaller than this, other high-resolution lithography methods such as Electron Beam Lithography (EBL) should be used. Using such techniques it should be possible to fabricate sub 0.1 pm feature sizes and, possibly, feature sizes as small as 25nm.
As will be appreciated by the skilled person, the present invention provides a simple and elegant method for producing a patterned resist, which when combined with metal deposition and lift-off techniques, enables high resolution features to be fabricated in time and cost efficient manner. Using SPR-660 photoresist, and a 250nm layer of aluminium, feature sizes as small as 0.4pm have been demonstrated.
* Use of mutilayer resist having more than two layers, and precise calibration of the degree of undercut produced, will facilitate even greater control over the quality of the features to be fabricated.
Claims (15)
- * CLAIMS 1. A method for fabricating a patterned resist on a substratecomprising the steps of: depositing a first layer of a first resist on the substrate; exposing the first layer of the first resist to a predetermined level of exposure; depositing a second layer of a second resist over the pre-exposed first layer of the first resist, the second resist having substantially the same sensitivity to exposure as the first resist; and, patterning at least the second layer of resist by exposure.
- 2. A method according to claim 1, wherein the first resist and the second resist are characterized by substantially the same chemistry for post-exposure development.
- 3. A method according to claim 1 or claim 2, wherein the first resist and the second resist comprise the same resist material.
- 4. A method according to any preceding claim, wherein the first resist and the second resist comprise positive-tone resist.
- 5. A method according to any of claims I to 4, wherein the predetermined level of exposure is less than a clearing dose sufficient to fully expose the first layer of the first resist through its depth
- 6. A method according to any of claim I to 4, wherein the predetermined level of exposure is at least a clearing dose sufficient to fully expose the first layer of the first resist through its depth.
- 7. A method according to any preceding claim, wherein the step of patterning comprises exposing regions of the second layer of resist to a level of exposure that is at least a clearing dose sufficient to fully expose at least the second layer of the second resist through its depth.
- 8. A method according to any of claims 5 to 7 when dependent on claim 3, wherein the resist comprises SPR-660 resist.
- 9. A method according to claim 8, wherein the clearing dose is at least 1 2OmJ/cm2.
- 10. A method according to any preceding claim, wherein prior to depositing the second layer of the second resist the method further comprises the steps of: depositing a third layer of a third resist on the pre-exposed first layer of resist, the third resist having substantially the same sensitivity to exposure as the first and second resists; and, exposing the third layer of resist to a predetermined level of exposure.
- 11. A method according to claim 10 when dependent on claim 3, wherein the third resist comprises the same resist material as the first resist and the second resist.
- 12. A method according to any preceding claim, wherein the step of patterning further comprises developing the multi-layer resist to remove resist.
- 13. A method for fabricating features on a substrate comprising the steps of: fabricating a patterned resist on the substrate using the method according to claim 12; depositing a material over regions of the substrate from which the resist has been removed; and, then removing the remaining resist from the substrate.
- 14. A method according to claim 13, wherein the step of removing the remaining resist is performed using a lift-off process.
- 15. A method according to claim 13 or claim 14, wherein the material comprises a metal.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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GB0618425A GB2442030A (en) | 2006-09-19 | 2006-09-19 | Resist exposure and patterning process |
PCT/GB2007/003536 WO2008035059A2 (en) | 2006-09-19 | 2007-09-19 | Exposure and patterning process for forming multi-layer resist structures |
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GB0618425A GB2442030A (en) | 2006-09-19 | 2006-09-19 | Resist exposure and patterning process |
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GB2442030A true GB2442030A (en) | 2008-03-26 |
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CN112652522B (en) | 2020-07-23 | 2022-05-03 | 腾讯科技(深圳)有限公司 | Photoresist structure, patterned deposition layer, semiconductor chip and manufacturing method thereof |
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JPS5984427A (en) * | 1982-11-04 | 1984-05-16 | Matsushita Electric Ind Co Ltd | Patterning method |
JPS61170738A (en) * | 1985-01-25 | 1986-08-01 | Seiko Epson Corp | Lift-off process by multi-layered resist |
JPS63288020A (en) * | 1987-05-20 | 1988-11-25 | Sumitomo Electric Ind Ltd | Formation of electrode |
JPH02231705A (en) * | 1989-03-03 | 1990-09-13 | Nec Corp | Developing method |
US5091288A (en) * | 1989-10-27 | 1992-02-25 | Rockwell International Corporation | Method of forming detector array contact bumps for improved lift off of excess metal |
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US3476561A (en) * | 1965-08-30 | 1969-11-04 | Ibm | Photoetch method |
US4180604A (en) * | 1977-12-30 | 1979-12-25 | International Business Machines Corporation | Two layer resist system |
JPS6021574A (en) * | 1983-07-15 | 1985-02-02 | Fujitsu Ltd | Manufacture of semiconductor device |
US5120622A (en) * | 1990-02-05 | 1992-06-09 | Eastman Kodak Company | Lift-off process for patterning dichroic filters |
JP3119957B2 (en) * | 1992-11-30 | 2000-12-25 | 株式会社東芝 | Method for manufacturing semiconductor device |
US5693548A (en) * | 1994-12-19 | 1997-12-02 | Electronics And Telecommunications Research Institute | Method for making T-gate of field effect transistor |
JP3339331B2 (en) * | 1996-09-27 | 2002-10-28 | 日立電線株式会社 | Method for manufacturing semiconductor device |
JP2000199968A (en) * | 1999-01-06 | 2000-07-18 | Sony Corp | Multilayered resist structure and manufacture of three- dimensional fine structure using the same |
JP2001209189A (en) * | 2000-01-28 | 2001-08-03 | Univ Tohoku | Laminated structure |
WO2003065124A1 (en) * | 2002-01-25 | 2003-08-07 | Jsr Corporation | Two-layer film and method of forming pattern with the same |
EP1489460A3 (en) * | 2003-06-20 | 2008-07-09 | FUJIFILM Corporation | Light-sensitive sheet comprising support, first light-sensitive layer and second light-sensitive layer |
US7229745B2 (en) * | 2004-06-14 | 2007-06-12 | Bae Systems Information And Electronic Systems Integration Inc. | Lithographic semiconductor manufacturing using a multi-layered process |
KR20060071228A (en) * | 2004-12-21 | 2006-06-26 | 동부일렉트로닉스 주식회사 | Pattern of semiconductor device and method for forming the same |
DE102006041774A1 (en) * | 2006-09-04 | 2008-03-20 | Forschungszentrum Jülich GmbH | Lithographic process for the preparation of a structure |
-
2006
- 2006-09-19 GB GB0618425A patent/GB2442030A/en not_active Withdrawn
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2007
- 2007-09-19 WO PCT/GB2007/003536 patent/WO2008035059A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS5984427A (en) * | 1982-11-04 | 1984-05-16 | Matsushita Electric Ind Co Ltd | Patterning method |
JPS61170738A (en) * | 1985-01-25 | 1986-08-01 | Seiko Epson Corp | Lift-off process by multi-layered resist |
JPS63288020A (en) * | 1987-05-20 | 1988-11-25 | Sumitomo Electric Ind Ltd | Formation of electrode |
JPH02231705A (en) * | 1989-03-03 | 1990-09-13 | Nec Corp | Developing method |
US5091288A (en) * | 1989-10-27 | 1992-02-25 | Rockwell International Corporation | Method of forming detector array contact bumps for improved lift off of excess metal |
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WO2008035059A3 (en) | 2008-07-03 |
GB0618425D0 (en) | 2006-11-01 |
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