JPH01239928A - Formation of pattern - Google Patents

Formation of pattern

Info

Publication number
JPH01239928A
JPH01239928A JP6753888A JP6753888A JPH01239928A JP H01239928 A JPH01239928 A JP H01239928A JP 6753888 A JP6753888 A JP 6753888A JP 6753888 A JP6753888 A JP 6753888A JP H01239928 A JPH01239928 A JP H01239928A
Authority
JP
Japan
Prior art keywords
resist film
positive type
type resist
positive resist
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6753888A
Other languages
Japanese (ja)
Inventor
Naoaki Sugimoto
杉本 直明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP6753888A priority Critical patent/JPH01239928A/en
Publication of JPH01239928A publication Critical patent/JPH01239928A/en
Pending legal-status Critical Current

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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To develop at a time first and second positive resist films by superimposing and applying the second positive type resist film, which is not exposed, on the first positive type resist film after exposing the whole surface of the latter, and selectively exposing both films. CONSTITUTION:A first positive type resist film 12 is formed on a substrate 11 and exposed over the entire surface thereof. A second positive type resist film 13 of the same kind as the first one is superimposed and applied on the first one. Then, those films are selectively irradiated with a light l2 by a projection exposure method to selectively form an optically sensitized region 14 on the second positive type resist film 13. Further, the first and second positive type resist films 12, 13 corresponding to the sensitized region 14 are removed to form an opening 15. With such a construction, upon the second positive type resist film 13 being selectively exposed for forming the opening with use of a development solution, the first positive type resist film 12 is also developed for forming an opening therethrough.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造におけるパターン形成の、
中でもポジ型レジストのパターン形成方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to pattern formation in the manufacture of semiconductor devices.
In particular, the present invention relates to a method of forming a positive resist pattern.

〔従来の技術〕[Conventional technology]

半導体基板上に1〜2μm以下の微細なマスクパターン
を形成する方法は、様々であるが、特に段差を有する基
板上に、均一よくレジストパターンを形成する方法とし
て、特開昭58−132926のようなものがある。こ
れを第2図にて説明する。まず、ポジ型レジスト20に
光照射1.(紫外線)を行ない、後の現像液に対し可溶
性とする(第2図(α))。次に、表面が平担あるいは
凹凸を有する半導体基板あるいは薄膜等の基板21上に
前記ポジ型レジスト20を塗布し第1のポジ型レジスト
膜22を形成する(第2図(b))。
There are various methods for forming a fine mask pattern of 1 to 2 μm or less on a semiconductor substrate, but there is a method for forming a resist pattern with good uniformity, especially on a substrate with steps, as described in JP-A-58-132926. There is something. This will be explained with reference to FIG. First, the positive resist 20 is irradiated with light. (ultraviolet rays) to make it soluble in the subsequent developer (Fig. 2 (α)). Next, the positive resist 20 is applied onto a substrate 21 such as a semiconductor substrate or a thin film having a flat or uneven surface to form a first positive resist film 22 (FIG. 2(b)).

レジスト膜22の膜厚は基板21の凹凸よりも厚く形成
する。ここでレジスト膜22の表面は必ずしも平担でな
くてもよいが、平担の方が好ましい。次に、光来照射の
ポジ型しジス)[25を第1のポジ型レジスト1l12
2に重ねて塗布する(第2図(c))。このとき、第1
及び第2のポジ型レジスト膜22.23として同じ種類
のものを用いるため、第1及び第2のレジスト膜22.
25の界面は明確でない。次に、投影露光方法により選
択的に光照射t4 を行ない、レジスト膜23に選択的
に感光領域24を形成する(第2図(d))。次に1ポ
ジ型レジスト用の現像、リンス処理により、感光領域2
4の第1及び第2のレジスト膜22.25を選択的に除
去し、開孔部25を形成する(第2図(e))。そして
、この第1及び第2のレジスト膜22.23のパターン
を用いて基板21のエツチング処理等を行うというもの
である。
The thickness of the resist film 22 is formed to be thicker than the unevenness of the substrate 21. Here, the surface of the resist film 22 does not necessarily have to be flat, but is preferably flat. Next, apply a positive resist (25) to the first positive resist (1l12) using optical irradiation.
2 (Fig. 2(c)). At this time, the first
Since the same type of resist films 22 and 23 are used as the second positive resist films 22 and 23, the first and second resist films 22.
The interface of 25 is not clear. Next, light irradiation t4 is selectively performed using a projection exposure method to selectively form photosensitive regions 24 on the resist film 23 (FIG. 2(d)). Next, the photosensitive area 2 is developed and rinsed for 1 positive resist.
The first and second resist films 22 and 25 of No. 4 are selectively removed to form an opening 25 (FIG. 2(e)). Then, the substrate 21 is etched using the patterns of the first and second resist films 22 and 23.

以上の方法によると、第2図(α)に示すようにあらか
じめ感光したポジ型しジス)20を用いて、第1のレジ
スト膜22を塗布するので開孔部25でのレジスト残り
とが、パターン巾が異なるということがなくなる。また
第1のレジスト膜22が基板21の平担化の効果を持ち
、従って第2のレジ′スト膜23の膜厚は基板21の凹
凸に関係なく、はぼ均一となり、一定の露光量でパター
ン形成を精度よく行うことができる。
According to the above method, as shown in FIG. 2(α), the first resist film 22 is coated using a positive-type resist film 20 that has been exposed in advance, so that the remaining resist in the openings 25 is removed. This eliminates the possibility of different pattern widths. In addition, the first resist film 22 has the effect of flattening the substrate 21, so the thickness of the second resist film 23 becomes almost uniform regardless of the unevenness of the substrate 21, and with a constant exposure amount. Pattern formation can be performed with high precision.

〔発明が解決しよ5とする課題〕J しかし、前述の方法では、ボ°ジ型レジストをあらかじ
め感光する工程が増すと共に、感光されたレジストを塗
布するラインが余計に必要となる。
[Problems to be Solved by the Invention] J However, in the above-mentioned method, the step of exposing the body type resist in advance to light is increased, and an additional line for applying the exposed resist is required.

また、従来の方法では、レジストを大量に一括露光する
ためポジ型レジストを均一よく感光することは困難で、
しかも不純物が混入しゃすくレジストの特性を劣化させ
ていた。
In addition, with conventional methods, a large amount of resist is exposed all at once, making it difficult to uniformly expose positive resist.
Moreover, impurities were mixed in and deteriorated the characteristics of the resist.

そこで、本発明は、このような課題を解決するもので、
その目的とするところは、レジストをあらかじめ感光す
る必要をなくし、しかも現存のレジスト塗布ラインのみ
で微細パターンを精度よくかつ、従来の方法よりも高ス
ループツトに形成スることである。
Therefore, the present invention is intended to solve such problems,
The purpose of this method is to eliminate the need to expose the resist to light in advance, and to form fine patterns with high precision using only existing resist coating lines and with a higher throughput than conventional methods.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によるパターン形成方法は、ポジ型のレジストを
基板上に塗布して、第1のポジ型レジスト膜を形成する
工□と、前記第1のポジ型レジスト膜に全面露光を施し
た後に1前記第1のポジ型レジスト膜上に、未感光の第
2のポジ型レジスト膜に選択的に光照射を行う工程と、
現像処理により、前記第1と第2のポジ型レジスト膜を
選択的に除去してレジストパターンを形成する工程とを
01uえたことを特徴とする。
The pattern forming method according to the present invention includes a step of applying a positive resist onto a substrate to form a first positive resist film, and a step of exposing the entire surface of the first positive resist film to light. selectively irradiating an unexposed second positive resist film with light on the first positive resist film;
The method is characterized in that it further includes a step of selectively removing the first and second positive resist films by a development process to form a resist pattern.

〔作用〕[Effect]

本発明の上記の構成によれば、第1のポジ型レジストI
Nをあらかじめ全面露光することにより、第2のポジ型
レジスト膜を選択的に露光し、現像液にて開孔する際、
第1のポジ型レジスト膜も同時に、現像し開孔できるも
のである。
According to the above configuration of the present invention, the first positive resist I
By exposing the entire surface of N in advance, the second positive resist film is selectively exposed, and when opening holes with a developer,
The first positive resist film can also be developed and opened at the same time.

〔実施例〕〔Example〕

以下、本発明の構成を図面を用いて説明する。 Hereinafter, the configuration of the present invention will be explained using the drawings.

第1図は本発明の一実施例を示す工程断面図である。ま
ず、表面が平担あるいは凹凸を有する半導体基板あるい
は薄膜等の基板11上に第1のポジ型しジス)Ii!J
12を形成し、露光装置にて全面露光を行う(第1図(
α))。レジス)I!s12の膜厚は基板11の凹凸よ
りも厚く形成する。ここで、レジスト膜12の表面は必
ずしも平担でなくてもよいが、平担の方が好ましい。次
に、第2のポジ型レジスト膜13を第1のポジ型レジス
ト膜12に重ねて塗布する(第1図(b))。このとき
、第1及び第2のポジ型しジス)膜12.15として同
じ種類のものを用いるため、第1及び第2のポジ型レジ
スト!12 、1 !lの界面は明確ではない。次に投
影露光方法により選択的に光照射t、を行ない、レジス
ト膜13に選択的に感光領域14を形成する(第1図(
C))。次に、適寸のポジ型レジスト用の現像、リンス
処理により感光領域14の第1及び第2のホ゛ジ型レジ
スト)漠12.15を選択的に除去し、開孔部15を形
成する(第1図(d))。そして、この第1及び第2の
ポジ型レジスト膜12.13のパターンを用いて基板1
1のエツチング処理等を行なう。
FIG. 1 is a process sectional view showing an embodiment of the present invention. First, a first positive type film is formed on a substrate 11 such as a semiconductor substrate or a thin film having a flat or uneven surface. J
12 is formed, and the entire surface is exposed using an exposure device (see Fig. 1 (
α)). Regis) I! The film thickness of s12 is formed to be thicker than the unevenness of the substrate 11. Here, the surface of the resist film 12 does not necessarily have to be flat, but is preferably flat. Next, a second positive resist film 13 is applied over the first positive resist film 12 (FIG. 1(b)). At this time, since the same type of film is used as the first and second positive resist films 12 and 15, the first and second positive resist films 12 and 15 are the same type. 12, 1! The interface of l is not clear. Next, selective light irradiation t is performed using a projection exposure method to selectively form photosensitive areas 14 on the resist film 13 (see FIG.
C)). Next, by developing and rinsing the positive type resist of an appropriate size, the first and second positive type resists 12 and 15 in the photosensitive area 14 are selectively removed, and the openings 15 are formed (the first and second positive type resists). Figure 1 (d)). Then, using the patterns of the first and second positive resist films 12 and 13, the substrate 1 is
1. Etching processing etc. are performed.

〔発明の効果〕 以上述べたように本発明によれば、基板上に第1のポジ
型レジスト膜を形成後、全面露光を行うために、従来の
方法のようにレジストをあらかじめ感光させ、この感光
させたレジストを塗布するラインを設ける必要がなく、
従来の方法と同等の効果を得ることができる。すなわち
、基板表面にあらかじめ露光したポジ型レジスト膜を形
成しておくので、段差上下の膜厚差に関係なくレジスト
膜を現像、リンス処理により精度よく除去できる。故に
、本発明では、段差上下の膜厚差に関係なく微細パター
ンを精度よく形成することができる。また、本発明は反
射率の高い金属膜及び基板段差によるレジスト膜の膜厚
変動に関係なく、一定の露光量でパターン形成を精度よ
く行うことができる。さらに、レジスト膜を2回塗布す
るにもかかわらず1回の現像、リンス処理によりパター
ン形成が行なえるというすぐれた効果を発揮するもので
ある。
[Effects of the Invention] As described above, according to the present invention, after forming the first positive resist film on the substrate, in order to perform full-surface exposure, the resist is exposed in advance as in the conventional method, and this There is no need to set up a line for applying exposed resist,
It is possible to obtain the same effect as the conventional method. That is, since a positive resist film that has been exposed to light in advance is formed on the substrate surface, the resist film can be accurately removed by development and rinsing regardless of the difference in film thickness above and below the step. Therefore, in the present invention, a fine pattern can be formed with high accuracy regardless of the difference in film thickness above and below the step. Furthermore, the present invention allows pattern formation to be performed with high accuracy at a constant exposure amount, regardless of variations in the film thickness of the resist film due to metal films with high reflectance and substrate steps. Furthermore, although the resist film is coated twice, pattern formation can be performed by one development and rinsing treatment, which is an excellent effect.

なお本発明は、配線形成工程、コンタクトホール形成工
程を初め、あらゆる工程のパターン形成に適用可能であ
ることは言うまでもない。
It goes without saying that the present invention is applicable to pattern formation in all processes including wiring formation processes and contact hole formation processes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(α)〜Cd)は本発明の一実施例に係るパター
ン形成方法を示す工程断面図。第2図(α)〜(g)は
、従来の一実施例に係るパターン形成方法を示す工程断
面図である。 11.21・・・・・・半導体基板 12.22・・・・・・第1のポジ型レジスト膜13.
23・・・・・・第2のポジ型レジスト膜14.24・
・・・・・感光領域 15.25・・・・・・開孔部 20   ・・・・・・ポジ型レジスト1、.1..1
8,1.・・・・・・光照射蕃1図 と1 勇 2図
FIGS. 1(α) to Cd) are process cross-sectional views showing a pattern forming method according to an embodiment of the present invention. FIGS. 2(α) to 2(g) are process cross-sectional views showing a pattern forming method according to a conventional example. 11.21... Semiconductor substrate 12.22... First positive resist film 13.
23...Second positive resist film 14.24.
. . . Photosensitive area 15.25 . . . Opening portion 20 . . . Positive resist 1, . 1. .. 1
8,1.・・・・・・Light irradiation barb 1 and 1 Isamu 2

Claims (1)

【特許請求の範囲】[Claims]  半導体装置の製造におけるパターン形成方法において
、ポジ型のレジストを基板上に塗布して第1のポジ型レ
ジスト膜を形成する工程と、前記第1のポジ型レジスト
膜に全面露光を施した後に前記第1のポジ型レジスト膜
上に、未感光の第2のポジ型レジスト膜を形成した後、
前記第2のポジ型レジスト膜に選択的に光照射を行う工
程と、現像処理により、前記第1と第2のポジ型レジス
ト膜を選択的に除去してレジストパターンを形成する工
程とを備えたことを特徴とするパターン形成方法。
In a pattern forming method in manufacturing a semiconductor device, a step of applying a positive resist onto a substrate to form a first positive resist film, and a step of exposing the entire surface of the first positive resist film to light, After forming an unexposed second positive resist film on the first positive resist film,
A step of selectively irradiating the second positive resist film with light, and a step of selectively removing the first and second positive resist films by a development treatment to form a resist pattern. A pattern forming method characterized by:
JP6753888A 1988-03-22 1988-03-22 Formation of pattern Pending JPH01239928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6753888A JPH01239928A (en) 1988-03-22 1988-03-22 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6753888A JPH01239928A (en) 1988-03-22 1988-03-22 Formation of pattern

Publications (1)

Publication Number Publication Date
JPH01239928A true JPH01239928A (en) 1989-09-25

Family

ID=13347852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6753888A Pending JPH01239928A (en) 1988-03-22 1988-03-22 Formation of pattern

Country Status (1)

Country Link
JP (1) JPH01239928A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02118653A (en) * 1988-10-28 1990-05-02 Nec Corp Process for forming fine pattern using two-layered photoresist
JP2014063901A (en) * 2012-09-21 2014-04-10 Mitsubishi Electric Corp Semiconductor device manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02118653A (en) * 1988-10-28 1990-05-02 Nec Corp Process for forming fine pattern using two-layered photoresist
JP2014063901A (en) * 2012-09-21 2014-04-10 Mitsubishi Electric Corp Semiconductor device manufacturing method

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