JPH05243115A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05243115A
JPH05243115A JP4008884A JP888492A JPH05243115A JP H05243115 A JPH05243115 A JP H05243115A JP 4008884 A JP4008884 A JP 4008884A JP 888492 A JP888492 A JP 888492A JP H05243115 A JPH05243115 A JP H05243115A
Authority
JP
Japan
Prior art keywords
exposure
pattern
reticle
semiconductor substrate
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4008884A
Other languages
Japanese (ja)
Inventor
Yoichi Nomura
洋一 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4008884A priority Critical patent/JPH05243115A/en
Publication of JPH05243115A publication Critical patent/JPH05243115A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16LPIPES; JOINTS OR FITTINGS FOR PIPES; SUPPORTS FOR PIPES, CABLES OR PROTECTIVE TUBING; MEANS FOR THERMAL INSULATION IN GENERAL
    • F16L59/00Thermal insulation in general
    • F16L59/02Shape or form of insulating materials, with or without coverings integral with the insulating materials
    • F16L59/021Shape or form of insulating materials, with or without coverings integral with the insulating materials comprising a single piece or sleeve, e.g. split sleeve, two half sleeves

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To make pattern dimensions uniform by a method wherein the prescribed pattern, to be transferred to a photosensitive organic material film through a mask, is composed of a plurality of masks, and the prescribed patterns are formed by conducting an exposure process and a developing treatment on each mask. CONSTITUTION:The first exposure is conducted on a silicon semiconductor substrate on which a positive type photoresist is spin-coated using the first exposure reticle 12a. Then, the second exposure is conducted on the silicon semiconductor substrate on which the first exposure is finished using the second exposure reticle 12b. The position of pattern is arranged by shifting downward the pattern of the first exposure reticle. The second hole pattern should be designed in such a manner that it is positioned in the middle of the hole pattern formed by the first exposure. After exposure, the photoresist on the exposed part of the semiconductor substrate is removed by an alkaline developing solution, and a pattern is formed on the prescribed position without receiving proximity effect. As a result, the problem of proximity effect can be removed, and the dimensional irregularity can be lessened.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にリソグラフィプロセス技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a lithographic process technique.

【0002】[0002]

【従来の技術】図3は、従来の半導体装置の製造フロー
毎の半導体基板の断面図を示している。半導体装置の製
造工程は以下の通りである。半導体基板31上にフォト
レジスト32と呼ばれる感光性有機膜をスピンコートす
る(図3(a))。次にガラス基板上に所定のクロムパ
ターン34を配列したレチクル33を介して紫外線で露
光する(図3(b))。次にアルカリ性現像液により露
光された部分のフォトレジスト膜を除去することにより
所定のフォトレジストのパターン32を形成していた
(図3(c))。
2. Description of the Related Art FIG. 3 is a sectional view of a semiconductor substrate for each manufacturing flow of a conventional semiconductor device. The manufacturing process of the semiconductor device is as follows. A photosensitive organic film called a photoresist 32 is spin-coated on the semiconductor substrate 31 (FIG. 3A). Next, the glass substrate is exposed to ultraviolet rays through a reticle 33 in which a predetermined chrome pattern 34 is arranged (FIG. 3B). Next, the predetermined photoresist pattern 32 was formed by removing the photoresist film in the portion exposed by the alkaline developer (FIG. 3C).

【0003】[0003]

【発明が解決しようとする課題】従来の半導体装置のパ
ターン形成方法では、ステッパを用いて縮小投影露光を
行う際に繰り返しパターンが設計されたレチクルを透過
した光が主にフラウンホウファ回折により横方向に広が
り、本来遮光されるべき部分の光の強度が大きくなると
いう現象が発生する。この現象は、パターン寸法が小さ
くかつパターンの間隔が狭いくり返しパターンの場合に
発生しやすい。
In the conventional method for forming a pattern of a semiconductor device, light transmitted through a reticle in which a repetitive pattern is designed is mainly transmitted in a lateral direction by Fraunhofer diffraction when performing reduction projection exposure using a stepper. A phenomenon occurs in which the light spreads and the intensity of light in the portion that should originally be shielded increases. This phenomenon tends to occur in the case of a repeated pattern having a small pattern size and a narrow pattern interval.

【0004】このため半導体基板上に投影される光の強
度分布は1あるいは0で示される不連続な値ではなく、
連続的になり、本来同一の寸法で形成される繰り返しパ
ターンの寸法が互いに異なるかもしくはパターンの解像
が不可能となる。したがって、繰り返しパターンの多い
半導体装置では各素子のパターン寸法が半導体基板上で
相違し均一な電気特性を得ることができなくなり信頼性
の高い半導体装置の製造が困難となる。
Therefore, the intensity distribution of the light projected on the semiconductor substrate is not a discontinuous value represented by 1 or 0,
It becomes continuous, and the sizes of the repeated patterns that are originally formed with the same size are different from each other, or the pattern cannot be resolved. Therefore, in a semiconductor device having many repeating patterns, the pattern size of each element is different on the semiconductor substrate, and uniform electric characteristics cannot be obtained, and it becomes difficult to manufacture a highly reliable semiconductor device.

【0005】本発明の目的は、繰り返しパターンのパタ
ーン寸法の均一化を可能とし、かつパターンの高集積化
を可能としたパターン形成方法を提供することである。
An object of the present invention is to provide a pattern forming method which makes it possible to make the pattern size of a repetitive pattern uniform and to make the pattern highly integrated.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置のパ
ターン形成方法は、本来単一のガラス製レチクル上に配
置されていた繰り返しクロムパターンを複数のパターン
に分割し、近接するパターンの相互の影響がないように
レチクル1枚当りのパターンの密度を下げ、かつ隣接す
るパターンの間隔を広げた複数のレチクルを用いて複数
回露光する工程を含んでいる。
According to a method of forming a pattern of a semiconductor device of the present invention, a repetitive chrome pattern originally arranged on a single glass reticle is divided into a plurality of patterns, and adjacent patterns are mutually separated. The method includes a step of exposing a plurality of times using a plurality of reticles in which the pattern density per reticle is reduced so that there is no influence and the interval between adjacent patterns is widened.

【0007】[0007]

【実施例】次に図面を参照して本発明を説明する。図1
(a)〜(c)は、本発明の第1の実施例を示す図であ
り、MOS集積回路製造時のコンタクト形成工程におい
てシリコン半導体基板上に形成するフォトレジストパタ
ーンの平面図(a)および露光に用いるマスクの平面図
(b),(c)である。図1(a)において、シリコン
半導体基板上のポジ型フォトレジスト11のパターンは
x(μm)xz(μm)の寸法のホールパターンであ
り、パターンの間隔はy(μm)である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the drawings. Figure 1
(A)-(c) is a figure which shows the 1st Example of this invention, The top view (a) of the photoresist pattern formed on a silicon semiconductor substrate in the contact formation process at the time of MOS integrated circuit manufacture, and (a). It is a top view (b), (c) of the mask used for exposure. In FIG. 1A, the pattern of the positive photoresist 11 on the silicon semiconductor substrate is a hole pattern having dimensions x (μm) xz (μm), and the pattern interval is y (μm).

【0008】露光用の光の波長365nm,開口数0.
45の場合、半導体基板上にパターンを作製する際に問
題となるのは、寸法x(μm)が0.8μm程度以下か
つパターン間隔y(μm)がx(μm)に等しい時であ
る。ここでは5対1縮小投影露光の場合でホール間隔y
がホール寸法x(μm)に等しい時のパターン形成方法
を示す。
The exposure light has a wavelength of 365 nm and a numerical aperture of 0.
In the case of No. 45, the problem when the pattern is formed on the semiconductor substrate is when the dimension x (μm) is about 0.8 μm or less and the pattern interval y (μm) is equal to x (μm). Here, in the case of 5: 1 reduction projection exposure, the hole interval y
Shows the pattern forming method when is equal to the hole dimension x (μm).

【0009】先ず第1露光用レチクル12aを用いてポ
ジ型フォトレジストをスピンコートしたシリコン半導体
基板に第1の露光を行う。第1露光用レチクル12aの
マスクパターンの設計はレチクル上でホールパターンa
(μm)=5x(μm)、ホール間隔b(μm)=3a
(μm)とする。次いで第2露光用レチクル12bを用
いて、第1露光を終了したシリコン半導体基板に対して
2回目の露光を行う。この時用いる第2露光用レチクル
12bのコンタクトホールの寸法a(μm)およびホー
ル間隔b(μm)は第1露光用レチクル12aと同じで
ある。
First, the first exposure reticle 12a is used to perform a first exposure on a silicon semiconductor substrate spin-coated with a positive photoresist. The mask pattern of the first exposure reticle 12a is designed to have a hole pattern a on the reticle.
(Μm) = 5 × (μm), hole spacing b (μm) = 3a
(Μm). Then, the second exposure reticle 12b is used to perform the second exposure on the silicon semiconductor substrate for which the first exposure has been completed. The dimension a (μm) of the contact holes and the hole interval b (μm) of the second exposure reticle 12b used at this time are the same as those of the first exposure reticle 12a.

【0010】パターンの位置は第1露光用レチクルのパ
ターンを図面の下方向に2a(μm)だけずらして配列
しており、第2のホールパターンは第1露光で形成され
たホールパターンの中間に位置するように設計されてい
る。露光後シリコン半導体基板は、アルカリ性現像液を
用い露光部分のフォトレジストが除去され所定の位置に
パターンが近接効果を受けずに形成される。
The positions of the patterns are arranged such that the patterns of the first exposure reticle are shifted in the downward direction of the drawing by 2a (μm), and the second hole pattern is located in the middle of the hole pattern formed by the first exposure. Designed to be located. The post-exposure silicon semiconductor substrate is formed by removing the photoresist in the exposed portion using an alkaline developing solution and forming a pattern at a predetermined position without the proximity effect.

【0011】図2(a)〜(c)は、本発明の第2の実
施例を示す図である。この実施例では、MOS集積回路
製造時のゲート電極の形成工程を示す。レチクル上のパ
ターンの配列及び露光方法は第1の実施例と同様であ
る。この実施例ではラインパターンを形成するためネガ
型フォトレジスト21を用いている。従って、第1露光
用レチクル23aおよび第2露光用レチクル23bは抜
きのパターン24a,24bが形成されている。
2A to 2C are views showing a second embodiment of the present invention. In this embodiment, a step of forming a gate electrode when manufacturing a MOS integrated circuit is shown. The arrangement of the pattern on the reticle and the exposure method are the same as in the first embodiment. In this embodiment, a negative photoresist 21 is used to form a line pattern. Therefore, the first exposure reticle 23a and the second exposure reticle 23b are formed with the blank patterns 24a and 24b.

【0012】[0012]

【発明の効果】本発明は、近接効果が生じる繰り返しパ
ターンにおいて、予め近接効果が起こらない程度の十分
広い間隔をもつパターンを配列した第1露光用レチクル
と第1露光用レチクルのクロムで覆われた空間部に形成
すべき残りのパターンを配列した第2露光用マスクを作
製し、上記マスクを使用して複数回露光を行うことによ
り近接効果を解消し、寸法のバラツキが少なく、かつ集
積度の高いパターンを形成できる効果がある。
According to the present invention, in a repetitive pattern in which the proximity effect occurs, the first exposure reticle and the chrome of the first exposure reticle in which patterns having a sufficiently wide interval that does not cause the proximity effect are arranged in advance are covered. A second exposure mask in which the remaining patterns to be formed in the open space are arranged is formed, and the proximity effect is eliminated by performing multiple exposures using the mask, and there is little dimensional variation and the degree of integration is high. This has the effect of forming a high-quality pattern.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例の半導体基板の平面図
(a)及びマスクの平面図(b),(c)である。
FIG. 1 is a plan view (a) of a semiconductor substrate and plan views (b) and (c) of a mask according to a first embodiment of the present invention.

【図2】本発明の第2の実施例の半導体基板の平面図
(a)及びマスクの平面図(b),(c)である。
FIG. 2 is a plan view (a) of a semiconductor substrate and plan views (b) and (c) of a mask according to a second embodiment of the present invention.

【図3】従来技術のプロセスフロー図(a)〜(c)で
ある。
FIG. 3 is a process flow diagram (a) to (c) of the related art.

【符号の説明】[Explanation of symbols]

11 ポジ型フォトレジスト 12a,23a 第1露光用レチクル 12b,23b 第2露光用レチクル 13a,13b コンタクトホールパターン 14 第1露光用レチクル上にあるコンタクトホール
位置 21 ネガ型フォトレジスト 22 シリコン半導体基板 24a,24b ゲート抜きパターン 25 第1露光用レチクル上にあるゲート抜きパター
ン 31 半導体基板 32 フォトレジスト 33 レチクル
11 Positive Photoresist 12a, 23a First Exposure Reticle 12b, 23b Second Exposure Reticle 13a, 13b Contact Hole Pattern 14 Contact Hole Position on First Exposure Reticle 21 Negative Photoresist 22 Silicon Semiconductor Substrate 24a, 24b gate removal pattern 25 gate removal pattern on first exposure reticle 31 semiconductor substrate 32 photoresist 33 reticle

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上の感光性有機材料膜にマス
クを介して転写する所定のパターンを複数枚のマスクか
ら構成される様にし、各々のマスク毎に露光する工程
と、前記感光性有機膜に現像処理を施して前記所定のパ
ターンを形成する工程とを有することを特徴とする半導
体装置の製造方法。
1. A step of exposing a photosensitive organic material film on a semiconductor substrate through a mask so that a predetermined pattern is formed from a plurality of masks, and exposing each of the masks. A step of developing the film to form the predetermined pattern, the method for manufacturing a semiconductor device.
JP4008884A 1992-01-22 1992-01-22 Manufacture of semiconductor device Withdrawn JPH05243115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4008884A JPH05243115A (en) 1992-01-22 1992-01-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4008884A JPH05243115A (en) 1992-01-22 1992-01-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05243115A true JPH05243115A (en) 1993-09-21

Family

ID=11705109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4008884A Withdrawn JPH05243115A (en) 1992-01-22 1992-01-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05243115A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291552B1 (en) * 1996-10-29 2001-09-17 전주범 Method for metal patterning of thin film type light path control device
KR100307631B1 (en) * 1999-06-01 2001-09-29 윤종용 Method for forming fine patterns of semiconductor device
JP2007173807A (en) * 2005-12-21 2007-07-05 Asml Netherlands Bv Method of manufacturing device and computer program product
JP2008098203A (en) * 2006-10-05 2008-04-24 Fujitsu Ltd Film patterning method and mask for exposure
KR100825801B1 (en) * 2007-02-13 2008-04-29 삼성전자주식회사 Methods of fabricating semiconductor device
JP2011044721A (en) * 2008-03-03 2011-03-03 Toshiba Corp Method of manufacturing semiconductor device
US8293456B2 (en) 2008-03-03 2012-10-23 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
WO2012173215A1 (en) * 2011-06-17 2012-12-20 Fujifilm Corporation Pattern forming method, method for manufacturing electronic device by using the same, and electronic device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291552B1 (en) * 1996-10-29 2001-09-17 전주범 Method for metal patterning of thin film type light path control device
KR100307631B1 (en) * 1999-06-01 2001-09-29 윤종용 Method for forming fine patterns of semiconductor device
US6498105B1 (en) 1999-06-01 2002-12-24 Samsung Electronics Co., Ltd. Method of forming fine patterns of a semiconductor device
JP2007173807A (en) * 2005-12-21 2007-07-05 Asml Netherlands Bv Method of manufacturing device and computer program product
JP2008098203A (en) * 2006-10-05 2008-04-24 Fujitsu Ltd Film patterning method and mask for exposure
KR100825801B1 (en) * 2007-02-13 2008-04-29 삼성전자주식회사 Methods of fabricating semiconductor device
JP2011044721A (en) * 2008-03-03 2011-03-03 Toshiba Corp Method of manufacturing semiconductor device
US8293456B2 (en) 2008-03-03 2012-10-23 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US8679731B2 (en) 2008-03-03 2014-03-25 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
WO2012173215A1 (en) * 2011-06-17 2012-12-20 Fujifilm Corporation Pattern forming method, method for manufacturing electronic device by using the same, and electronic device
JP2013004820A (en) * 2011-06-17 2013-01-07 Fujifilm Corp Pattern formation method, electronic device manufacturing method using the same, and electronic device

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990408