JP2801867B2 - Method for forming photoresist pattern of semiconductor device - Google Patents
Method for forming photoresist pattern of semiconductor deviceInfo
- Publication number
- JP2801867B2 JP2801867B2 JP7017754A JP1775495A JP2801867B2 JP 2801867 B2 JP2801867 B2 JP 2801867B2 JP 7017754 A JP7017754 A JP 7017754A JP 1775495 A JP1775495 A JP 1775495A JP 2801867 B2 JP2801867 B2 JP 2801867B2
- Authority
- JP
- Japan
- Prior art keywords
- photomask
- pattern
- photoresist
- exposed
- phase inversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229920002120 photoresistant polymer Polymers 0.000 title claims description 60
- 238000000034 method Methods 0.000 title claims description 35
- 239000004065 semiconductor Substances 0.000 title claims description 10
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 40
- 229910052804 chromium Inorganic materials 0.000 claims description 9
- 239000011651 chromium Substances 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 2
- 238000002834 transmittance Methods 0.000 claims description 2
- 239000010453 quartz Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体素子のフォトレジ
ストパターンを形成する方法に関するものであって、特
に高集積半導体素子を製造する時、要求される微細パタ
ーンを形成するために、4個のフォトマスクを用いた多
重重畳露光法で半導体素子のフォトレジストパターンを
形成する方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a photoresist pattern of a semiconductor device, and more particularly, to forming a fine pattern required for manufacturing a highly integrated semiconductor device. The present invention relates to a method for forming a photoresist pattern of a semiconductor device by a multiple overlapping exposure method using a photomask.
【0002】[0002]
【従来の技術】一般に、半導体素子が高集積化されてい
くことによって、0.25μm以下の線幅を有するパタ
ーンが素子製造において要求される。パターンの線幅は
光の波長(λ)に影響を多く受けるものの、光りの波長
が短ければ短いほどもっと小さい線幅を有するパターン
を形成することができる。2. Description of the Related Art In general, as a semiconductor device is highly integrated, a pattern having a line width of 0.25 .mu.m or less is required in device manufacture. Although the line width of the pattern is greatly affected by the wavelength (λ) of light, the shorter the wavelength of light, the smaller the line width of the pattern.
【0003】解像力(resolution power)は光の波長に比
例する。したがって、0.25μm以下の線幅を有する
パターンを形成するために短い波長を有するエキシマレ
ーザ(λ=248nm)が適用されたステップ(Steppe
r) を用いなければならない。[0003] Resolution power is proportional to the wavelength of light. Therefore, an excimer laser (λ = 248 nm) having a short wavelength is applied to form a pattern having a line width of 0.25 μm or less.
r) must be used.
【0004】[0004]
【発明が解決しようとする課題】ところで、比較的に長
い波長を有するG-line(λ=436nm)またはI-line
(λ=365nm)が適用されるステップを用いてこれ
らステップで形成することのできる最小線幅のパターン
よりもっと小さいパターンを形成しようとする場合、露
光コントラストの低下で素子から要求する形状(profil
e) 及び線幅を有するパターンは形成し難い問題があ
る。A G-line (λ = 436 nm) or an I-line having a relatively long wavelength is used.
(.Lambda. = 365 nm), when a pattern smaller than the minimum line width pattern that can be formed by these steps is to be formed, the shape required by the device due to the decrease in exposure contrast (profil).
e) There is a problem that it is difficult to form a pattern having a line width.
【0005】したがって、本発明は既存のステップを用
いるものの、このステップで形成することのできる最小
線幅のパターンよりもっと小さいパターンを形成するこ
とのできるフォトレジストパターン形成方法を提供する
ことにその目的がある。本発明のもう一つの目的は半導
体素子の超高集積化を達成することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method of forming a photoresist pattern which can form a pattern smaller than a pattern having a minimum line width which can be formed in this step, while using an existing step. There is. Another object of the present invention is to achieve ultra-high integration of a semiconductor device.
【0006】[0006]
【課題を解決するための手段】このような目的を達成す
るための本発明のフォトレジストパターン形成工程は第
1フォトマスクが装着されたステップにフォトレジスト
が塗布されたウェーハをローデェングし1次露光工程を
実施し、これによって前記フォトレジストの部分が露光
される段階と、前記第1フォトマスクを除去し、前記第
1フォトマスクが除去された位置で第2フォトマスクを
装着させ2次露光工程を実施し、これによって第1フォ
トマスクによって露光された前記フォトレジストの部分
が重複露光される段階と、前記第2フォトマスクを除去
し、前記第2フォトマスクが除去された位置に第3フォ
トマスクを装着させ3次露光工程を実施し、これによっ
て前記第1及び第2フォトマスクによって重複露光され
た前記フォトレジストの部分の間で露光されたフォトレ
ジストの部分が形成される段階と、前記第3フォトマス
クを除去し、前記第3フォトマスクが除去された位置に
第4フォトマスクを装着させ4次露光工程を実施し、こ
れによって前記第3フォトマスクによって露光された前
記フォトレジストの部分が重複露光される段階と、前記
第1及び第2フォトマスクによって露光された前記フォ
トレジストの部分と前記第3及び第4フォトマスクによ
って露光されたフォトレジストの部分を現像工程によっ
て除去し、これによってウェーハ上にフォトレジストパ
ターンを成形する段階からなることを特徴とする。In order to achieve the above object, a photoresist pattern forming process of the present invention comprises a step of loading a wafer coated with a photoresist in a step in which a first photomask is mounted and performing a first exposure. Performing a step of exposing the portion of the photoresist, removing the first photomask, mounting a second photomask at a position where the first photomask is removed, and performing a second exposure process. Performing the overlapping exposure of the portion of the photoresist exposed by the first photomask, removing the second photomask, and removing the third photomask at a position where the second photomask is removed. A third exposure process is performed by mounting a mask, whereby the photoresist that is overlap-exposed by the first and second photomasks is exposed. Forming an exposed portion of the photoresist between portions of the photomask, removing the third photomask, mounting a fourth photomask at a position where the third photomask has been removed, and performing fourth exposure. Performing a step of overlappingly exposing the portion of the photoresist exposed by the third photomask, and exposing the portion of the photoresist exposed by the first and second photomasks to the third portion. And removing a portion of the photoresist exposed by the fourth photomask by a developing process, thereby forming a photoresist pattern on the wafer.
【0007】[0007]
【作用】クロムパターンと位相反転物パターンの位置だ
け異なる第1及び第2フォトマスクを用いてフォトレジ
ストの部分を重複露光し、クロムパターンと位相反転物
パターンの位置だけ異なる第3及び第4フォトマスクを
用いて前記フォトレジストの他の部分を重複露光する。A portion of the photoresist is overlap-exposed using first and second photomasks that differ only in the position of the chrome pattern and the phase inversion pattern, and the third and fourth photos differ only in the position of the chrome pattern and the phase inversion pattern. Another portion of the photoresist is overexposed using a mask.
【0008】[0008]
【実施例】以下、添付された図面を参照して本発明を詳
細に説明する。図1は本発明の予定されたフォトレジス
トパターンを形成するために製作されたフォトマスクを
フォトマスク作業順序によってステップに配置したフォ
トマスクの断面図であり、図2Aないし図2Eは本発明
のフォトレジストパターンを形成する工程を説明するた
めに示したウェーハの断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a photomask in which a photomask manufactured to form a predetermined photoresist pattern according to the present invention is arranged in steps according to a photomask working sequence. FIGS. FIG. 3 is a cross-sectional view of a wafer shown for explaining a step of forming a resist pattern.
【0009】本発明ではフォトレジストパターン形成方
法の原理を分かり易くするために、フォトマスクに形成
されたパターンがウェーハ上に同じ大きさで伝達される
場合を適用した。通常に、露光工程時ウェーハ上に伝達
されるイメージはフォトマスクに形成されたパターンの
大きさより一定比率で縮小される。In the present invention, in order to make the principle of the photoresist pattern forming method easy to understand, a case where a pattern formed on a photomask is transmitted in the same size on a wafer is applied. Generally, an image transmitted on a wafer during an exposure process is reduced at a certain rate from the size of a pattern formed on a photomask.
【0010】図1に示された第1、第2、第3及び第4
フォトマスク11,21,31,41は素子製造において要求さ
れるパターンの線幅が0.2μmである場合、適用させ
るために製作したものである。The first, second, third and fourth shown in FIG.
The photomasks 11, 21, 31, and 41 are manufactured so as to be applied when the line width of the pattern required in element manufacturing is 0.2 μm.
【0011】第1フォトマスク11は多数のクロムパター
ン12と多数の位相反転物パターン13を石英基板14上に形
成し製作される。各々のクロムパターン12は隣設するク
ロムパターンとの間隔が1μmで離隔されるようにし、
クロムパターンの線幅が0.6μmとなるように形成す
る。多数の位相反転物パターン13は前記クロムパターン
12の間に一つずつ形成される。各々の位相反転物パター
ン13は隣設するクロムパターン12との間隔が0.2μm
で離隔されるようにし、位相反転物パターンの線幅が
0.6μmになるように形成する。一方、位相反転物パ
ターン13はSOG(Spin On Glass)透過率が10%であるク
ロムなどから形成される。The first photomask 11 is manufactured by forming a number of chrome patterns 12 and a number of phase inversion patterns 13 on a quartz substrate 14. Each chrome pattern 12 is separated from an adjacent chrome pattern by 1 μm,
The chromium pattern is formed so that the line width is 0.6 μm. Many phase inversion patterns 13 are the chrome patterns
Formed one by one between 12 Each phase inversion pattern 13 has a distance of 0.2 μm between adjacent chrome patterns 12.
And the line width of the phase inversion pattern is 0.6 μm. On the other hand, the phase inversion pattern 13 is formed of chrome or the like having a SOG (Spin On Glass) transmittance of 10%.
【0012】第2、第3及び第4フォトマスク21,31,
41は前述した第1フォトマスク11と同一である構成から
形成される。しかしながら、このフォトマスク11,21,
31,41をステップに同一である条件で装着し相互重畳さ
せた時、各々フォトマスク11,21,31,41のクロムパタ
ーン及び位相反転物パターンはその位置が設計ルール(r
ule)によってずれるように形成される。The second, third and fourth photomasks 21, 31,
41 is formed from the same configuration as the first photomask 11 described above. However, this photomask 11, 21,
When the steps 31 and 41 are mounted and superimposed on each other under the same conditions as the steps, the positions of the chromium pattern and the phase inversion pattern of the photomasks 11, 21, 31 and 41 are the design rules (r
ule).
【0013】すなわち、第2フォトマスク21が第1フォ
トマスク11を基準として製作される場合、第2フォトマ
スク21の位相反転物パターン23は第1フォトマスク11の
クロムパターン12と同一である位置になるように形成
し、第2フォトマスク21のクロムパターン22は第1フォ
トマスク11の位相反転物パターン13と同一である位置に
なるように形成する。結局、第1フォトマスク11と第2
フォトマスク21はクロムパターンと位相反転物パターン
の位置だけ異なるように製作される。That is, when the second photomask 21 is manufactured based on the first photomask 11, the phase inversion pattern 23 of the second photomask 21 is the same as the chrome pattern 12 of the first photomask 11. The chromium pattern 22 of the second photomask 21 is formed at the same position as the phase inversion pattern 13 of the first photomask 11. After all, the first photomask 11 and the second
The photomask 21 is manufactured so as to differ only by the position of the chrome pattern and the phase inversion pattern.
【0014】第3フォトマスク31が第2フォトマスク21
(または第1フォトマスク11)を基準として製作される
場合、第3フォトマスク31のクロムパターン32と位相反
転物パターン33は第2フォトマスク21のクロムパターン
22と位相反転物パターン23の間で0.2μmの間隔で露
出された石英基板24に重畳されながら順次に形成され
る。The third photomask 31 is used as the second photomask 21.
(Or the first photomask 11), the chrome pattern 32 and the phase inversion pattern 33 of the third photomask 31 are the same as those of the second photomask 21.
It is sequentially formed while being superposed on the quartz substrate 24 exposed at an interval of 0.2 μm between the pattern 22 and the phase inversion pattern 23.
【0015】そして第4フォトマスク41が第3フォトマ
スク31を基準として製作される場合、第4フォトマスク
41の位相反転物パターン43は第3フォトマスク31のクロ
ムパターン32と同一である位置になるように形成し、第
4フォトマスク41のクロムパターン42は第3フォトマス
ク31の位相反転物パターン33と同一である位置になるよ
うに形成する。When the fourth photomask 41 is manufactured based on the third photomask 31, the fourth photomask 41 is used.
The phase inversion pattern 43 of 41 is formed so as to be at the same position as the chromium pattern 32 of the third photomask 31, and the chrome pattern 42 of the fourth photomask 41 is formed in the phase inversion pattern 33 of the third photomask 31. It is formed so as to be in the same position as.
【0016】結局、第4フォトマスク41は第3フォトマ
スク31と比較しクロムパターンと位相反転物パターンの
位置だけ異なるように製作される。説明されていない符
号34,44は石英基板である。As a result, the fourth photomask 41 is manufactured so as to be different from the third photomask 31 only in the position of the chrome pattern and the phase inversion pattern. Unexplained reference numerals 34 and 44 are quartz substrates.
【0017】一方、前記のように4個のフォトマスク1
1,21,31,41を別々に製作せず4個のフォトマスクの
うち、いずれかの一つだけを製作し図1に示したように
フォトマスクの位置を順次に調節し露光工程を実施する
こともできる。On the other hand, as described above, the four photomasks 1
1, 21, 31 and 41 are not separately manufactured, but only one of the four photomasks is manufactured, and the position of the photomask is sequentially adjusted as shown in FIG. 1 to perform an exposure process. You can also.
【0018】本発明のフォトレジストパターン形成工程
は下記の通りである。図2Aはフォトレジスト2が塗布
されたウェーハ1を第1フォトマスク11が装着されたス
テップ(図示しない)にローディングし1次露光工程を
実施したものが示される。The photoresist pattern forming process of the present invention is as follows. FIG. 2A shows that the wafer 1 coated with the photoresist 2 is loaded to a step (not shown) in which the first photomask 11 is mounted, and a first exposure process is performed.
【0019】この時第1フォトマスク11のクロムパター
ン12に対応したフォトレジスト2の第1部分P1は露光さ
れなく、第1フォトマスク11の位相反転物パターン13に
対応したフォトレジスト2の第2部分P2は強度が弱く露
光され、第1フォトマスク11のクロムパターン12と位相
反転物パターン13の間の露出された部分に対応したフォ
トレジスト2の第3部分P3は正常的に露光される。その
後第1フォトマスク11は除去される。At this time, the first portion P1 of the photoresist 2 corresponding to the chrome pattern 12 of the first photomask 11 is not exposed, and the second portion P2 of the photoresist 2 corresponding to the phase inversion pattern 13 of the first photomask 11 is not exposed. The portion P2 is lightly exposed, and the third portion P3 of the photoresist 2 corresponding to the exposed portion between the chrome pattern 12 and the phase inversion pattern 13 of the first photomask 11 is normally exposed. After that, the first photomask 11 is removed.
【0020】図2Bは第1フォトマスク11が除去された
位置に第2フォトマスク21を装着させ2次露光工程を実
施したものが示される。この時第2フォトマスク21のク
ロムパターン22に対応したフォトレジスト2の第2部分
P2は露光されなく、第2フォトマスク21の位相反転物パ
ターン23に対応したフォトレジスト2の第1部分P1は強
度が弱く露光され、第2フォトマスク21のクロムパター
ン22と位相反転物パターン23の間の露出された部分に対
応したフォトレジスト2の第3部分P3は正常的に露光さ
れる。その後第2フォトレジスト21は除去される。した
がって、フォトレジスト2の第3部分P3は重複露光さ
れ、フォトレジスト2の第1及び第2部分P1,P2は強度
が弱く露光される。FIG. 2B shows a state in which the second photomask 21 is mounted at the position where the first photomask 11 has been removed and a second exposure process is performed. At this time, the second portion of the photoresist 2 corresponding to the chrome pattern 22 of the second photomask 21
P2 is not exposed, and the first portion P1 of the photoresist 2 corresponding to the phase inversion pattern 23 of the second photomask 21 is exposed with low intensity, and the chrome pattern 22 and the phase inversion pattern 23 of the second photomask 21 are exposed. The third portion P3 of the photoresist 2 corresponding to the portion exposed during the exposure is normally exposed. Thereafter, the second photoresist 21 is removed. Therefore, the third portion P3 of the photoresist 2 is overlap-exposed, and the first and second portions P1 and P2 of the photoresist 2 are exposed with low intensity.
【0021】図2Cは第2フォトマスク21が除去された
位置に第3フォトマスク31を装着させ3次露光工程を実
施したものが示される。この時第3フォトマスク31のク
ロムパターン32に対応したフォトレジスト2の第1部分
P1の左側部P1L 、第2部分P2の右側部P2R そして前記左
側部P1L と前記右側部P2R の間の第3部分P3は露光され
なく、第3フォトマスク31の位相反転物パターン33に対
応したフォトレジスト2の第1部分P1の右側部P1R 、第
2部分P2の左側部P2L そして前記右側部P1R と前記左側
部P2L の間で第3部分P3は強度が弱く露光され、第3フ
ォトマスク31のクロムパターン32と位相反転物パターン
33の間の露出された部分に対応したフォトレジスト2の
第1及び第2部分P1,P2の中央部P1C ,P2C は正常的に
露光される。FIG. 2C shows a state in which the third photomask 31 is attached to the position where the second photomask 21 has been removed and a third exposure process is performed. At this time, the first portion of the photoresist 2 corresponding to the chrome pattern 32 of the third photomask 31
The left part P1L of P1, the right part P2R of the second part P2 and the third part P3 between the left part P1L and the right part P2R are not exposed and correspond to the phase inversion pattern 33 of the third photomask 31. The right portion P1R of the first portion P1 of the photoresist 2, the left portion P2L of the second portion P2, and the third portion P3 between the right portion P1R and the left portion P2L are weakly exposed to light, and the third photomask 31 is exposed. Chrome pattern 32 and phase reversal pattern
The central portions P1C and P2C of the first and second portions P1 and P2 of the photoresist 2 corresponding to the exposed portions between 33 are normally exposed.
【0022】第3フォトマスク31によって正常的に露光
されたフォトレジスト2の部分は第1及び第2フォトマ
スク11,21によって重複露光された部分の間で存在す
る。その後第3フォトマスク31は除去される。The portion of the photoresist 2 normally exposed by the third photomask 31 exists between the portions that are repeatedly exposed by the first and second photomasks 11 and 21. Thereafter, the third photomask 31 is removed.
【0023】図2Dは第3フォトマスク31が除去された
位置に第4フォトマスク41を装着させ4次露光工程を実
施したことが示される。この時第4フォトマスク41のク
ロムパターン42に対応したフォトレジスト2の第1部分
P1の右側部P1R 、第2部分P2の左側部P2L そして前記右
側部P1R と前記左側部P2L の間の第3部分P3は露光され
なく、第4フォトマスク41の位相反転物パターン43に対
応したフォトレジスト2の第1部分P1の左側部P1L 、第
2部分P2の右側部P2R そして前記左側部P1L と前記右側
部P2R の間の第3部分P3は強度が弱く露光され、第4フ
ォトマスク41のクロムパターン42と位相反転物パターン
43の間の露出された部分に対応したフォトレジスト2の
第1及び第2部分P1,P2の中央部P1C ,P2C は露光され
る。その後第4フォトマスク41は除去される。FIG. 2D shows that the fourth photomask 41 is mounted at the position where the third photomask 31 is removed, and the fourth exposure process is performed. At this time, the first portion of the photoresist 2 corresponding to the chrome pattern 42 of the fourth photomask 41
The right part P1R of P1, the left part P2L of the second part P2, and the third part P3 between the right part P1R and the left part P2L are not exposed and correspond to the phase inversion pattern 43 of the fourth photomask 41. The left portion P1L of the first portion P1 of the photoresist 2, the right portion P2R of the second portion P2, and the third portion P3 between the left portion P1L and the right portion P2R are weakly exposed, and the fourth photomask 41 is exposed. Chrome pattern 42 and phase reversal pattern
The central portions P1C, P2C of the first and second portions P1, P2 of the photoresist 2 corresponding to the exposed portions between 43 are exposed. Thereafter, the fourth photomask 41 is removed.
【0024】したがって、フォトレジスト2の第1及び
第2部分P1,P2の中央部P1C ,P2Cが重複露光され、フ
ォトレジスト2の第1及び第2部分P1,P2の左側及び右
側部(P1L ,P1R 及びP2L ,P2R )は強度が弱く露光さ
れる。Therefore, the central portions P1C and P2C of the first and second portions P1 and P2 of the photoresist 2 are overlap-exposed, and the left and right portions (P1L and P1L and P1L) of the first and second portions P1 and P2 of the photoresist 2 are exposed. P1R and P2L, P2R) are exposed with low intensity.
【0025】図2Eは第1及び第2フォトマスク11,21
によって重複露光されたフォトレジスト2の第3部分P3
と第3及び第4フォトマスク31,41によって重複露光さ
れたフォトレジスト2の第1及び第2部分P1,P2の中央
部P1C ,P2C を現像工程として除去しウェーハ1上に多
数のフォトレジストパターン2Aを形成したものが示され
る。FIG. 2E shows the first and second photomasks 11, 21.
Third portion P3 of the photoresist 2 that has been repeatedly exposed by
The central portions P1C and P2C of the first and second portions P1 and P2 of the photoresist 2 which are overlapped and exposed by the third and fourth photomasks 31 and 41 are removed as a developing process to form a large number of photoresist patterns on the wafer 1. Forming 2A is shown.
【0026】フォトレジストパターン2Aの各々の幅はフ
ォトマスクのクロムパターンと位相反転物パターンの間
の離隔された幅に比例する。本発明ではフォトマスクに
形成されたパターンがウェーハ上に同じ大きさで伝達さ
れる場合のことを適用したため、フォトレジストパター
ン2Aの幅はフォトマスクのクロムパターンと位相反転物
パターンの間の離隔距離である0.2μmになる。The width of each of the photoresist patterns 2A is proportional to the distance between the chrome pattern of the photomask and the phase inversion pattern. In the present invention, since the case where the pattern formed on the photomask is transmitted on the wafer with the same size is applied, the width of the photoresist pattern 2A is the separation distance between the chrome pattern of the photomask and the phase inversion pattern. 0.2 μm.
【0027】図3は第1及び第2フォトマスク11,21を
順次に用いた露光工程から得られた重複露光エネルギー
合成強度分布度である。第1強度分布曲線3は第1フォ
トマスク11を用いた露光工程時得られ、第2強度分布曲
線4は第2フォトマスク21を用いた露光工程時得ること
ができる。第3強度分布曲線5は第1及び第2強度分布
曲線3,4が合成し得られたもので、とても高いコント
ラスト曲線を成し重畳露光法に有用である強度分布曲線
が成される。これによっての結果が図2Bに示されたフ
ォトレジスト2の露光状態である。FIG. 3 shows the overlapping exposure energy combined intensity distribution obtained by the exposure step using the first and second photomasks 11 and 21 in sequence. The first intensity distribution curve 3 can be obtained during the exposure step using the first photomask 11, and the second intensity distribution curve 4 can be obtained during the exposure step using the second photomask 21. The third intensity distribution curve 5 is obtained by synthesizing the first and second intensity distribution curves 3 and 4, and forms a very high contrast curve, which is useful for the superposition exposure method. The result is the exposed state of the photoresist 2 shown in FIG. 2B.
【0028】前記図3は第1及び第2フォトマスク11,
21を用いた強度分布曲線を示したものであるものの、第
3及び第4フォトマスク31,41も同じ結果を得ることが
できる。FIG. 3 shows the first and second photomasks 11,
Although the intensity distribution curve using 21 is shown, the same result can be obtained with the third and fourth photomasks 31 and 41.
【0029】本発明では、第1、第2、第3及び第4フ
ォトマスク11,21,31,41が図1に示された順序で用い
られたことを説明したものの、その順序に関わらず用い
ても図2Fのようなフォトレジストパターン2Aを形成す
ることができる。In the present invention, the first, second, third, and fourth photomasks 11, 21, 31, and 41 are described as being used in the order shown in FIG. 1, but regardless of the order. Even if used, a photoresist pattern 2A as shown in FIG. 2F can be formed.
【0030】[0030]
【発明の効果】前述のように4個のフォトマスクを用い
た4重重畳露光法であって、とても良好なコントラスト
の強度分布曲線を得ることができ解像力限界以上の超微
細パターンの形成ができるようにして半導体素子の高集
積化を成すことができる。As described above, in the quadruple overlapping exposure method using four photomasks, a very good contrast intensity distribution curve can be obtained and an ultrafine pattern exceeding the resolution limit can be formed. Thus, high integration of the semiconductor element can be achieved.
【図1】本発明のフォトレジストパターン形成のために
4個のマスクを順次に配置したマスク断面図である。FIG. 1 is a cross-sectional view of a mask in which four masks are sequentially arranged for forming a photoresist pattern according to the present invention.
【図2】本発明のフォトレジストパターンを形成する段
階を示した断面図である。FIG. 2 is a cross-sectional view illustrating a step of forming a photoresist pattern according to the present invention.
【図3】重複露光エネルギー合成強度分布図である。FIG. 3 is a distribution diagram of a combined exposure energy intensity;
1:ウェーハ 2:フォトレジス
ト 2A:フォトレジストパターン 3、4、5:強度分
布曲線 11、21、31、41: フォトマスク 12、22、32、42: クロムパターン 13、23、33、43: 位相反転物パターン 14、24、34、44: 石英基板1: Wafer 2: Photoresist 2A: Photoresist pattern 3, 4, 5: Intensity distribution curve 11, 21, 31, 41: Photomask 12, 22, 32, 42: Chrome pattern 13, 23, 33, 43: Phase Inverted pattern 14, 24, 34, 44: quartz substrate
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H01L 21/30 515B 528 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 21/30 515B 528
Claims (8)
方法において、第1フォトマスクが装着されたステップ
にフォトレジストが塗布されたウェーハをローディング
して1次露光工程を実施し、前記第1フォトマスクのク
ロムパターンと位相反転物パターンの間に対応される露
出されるフォトレジストの部分が露光される段階と、前
記第1フォトマスクを除去し、前記第1フォトマスクが
除去された位置に第2フォトマスクを装着させ2次露光
工程を実施し、前記第1フォトマスクによって露光され
た前記フォトレジストの部分が前記第2フォトマスクの
クロムパターンと位相反転物パターンの間で再び露出さ
れ重複露光される段階と、前記第2フォトマスクを除去
し、前記第2フォトマスクが除去された位置に第3フォ
トマスクを装着させ3次露光工程を実施し、前記第3フ
ォトマスクのクロムパターンと位相反転物パターンの間
に対応されて露出される前記第1及び第2フォトマスク
によって重複露光された前記フォトレジストの部分の間
のフォトレジストの他の部分が露光される段階と、前記
第3フォトマスクを除去し、前記第3フォトマスクが除
去された位置に第4フォトマスクを装着させ4次露光工
程を実施し、前記第3フォトマスクによって露光された
前記フォトレジストの他の部分が前記第4フォトマスク
のクロムパターンと位相反転物パターンの間で再び露出
され重複露光される段階と、前記第1及び第2フォトマ
スクによって重複露光された前記フォトレジストの部分
と前記第3及び第4フォトマスクによって重複露光され
た前記フォトレジストの他の部分を現像工程によって除
去することによって、前記ウェーハ上に多数のフォトレ
ジストパターンが形成される段階からなることを特徴と
する半導体素子のフォトレジストパターン形成方法。In a method of forming a photoresist pattern of a semiconductor device, a first exposure step is performed by loading a wafer coated with a photoresist in a step of mounting a first photomask, and performing a first exposure process. Exposing a portion of the exposed photoresist corresponding to between the chrome pattern and the phase inversion pattern; removing the first photomask; and removing a second photo-resist at a position where the first photomask is removed. A mask is mounted and a second exposure process is performed, and the portion of the photoresist exposed by the first photomask is exposed again between the chrome pattern and the phase inversion pattern of the second photomask and is subjected to double exposure. Removing the second photomask, and mounting a third photomask at a position where the second photomask has been removed. Performing a third exposure process, between the portions of the photoresist that are overlapped and exposed by the first and second photomasks correspondingly exposed between the chrome pattern and the phase inversion pattern of the third photomask; Exposing another portion of the photoresist, removing the third photomask, mounting a fourth photomask at a position where the third photomask has been removed, and performing a fourth exposure process; Another portion of the photoresist exposed by the third photomask is exposed again between the chrome pattern and the phase-inverted pattern of the fourth photomask and is overlapped, and the first and second photomasks are exposed. A portion of the photoresist overlap-exposed by the above and another portion of the photoresist overlap-exposed by the third and fourth photomasks. By removing by image process, a photoresist pattern forming method of a semiconductor device characterized by comprising the step of a number of photo-resist pattern on the wafer is formed.
ーンと位相反転物パターンはそのパターン線幅が同一で
あることを特徴とする半導体素子のフォトレジストパタ
ーン形成方法。2. A method according to claim 1, wherein said chromium pattern and said phase inversion pattern have the same pattern line width.
ーンとこれと隣設する位相反転物パターンは一定間隔離
隔されるように形成されることを特徴とする半導体素子
のフォトレジストパターン形成方法。3. The method of claim 1, wherein the chromium pattern and the phase inversion pattern adjacent thereto are formed so as to be separated from each other by a predetermined distance.
パターンはSOG(SpinOn Glass)として形成されることを
特徴とする半導体素子のフォトレジストパターン形成方
法。4. The method according to claim 1, wherein the phase inversion pattern is formed as SOG (Spin On Glass).
パターンは透過率が10%であるクロムから形成される
ことを特徴とする半導体素子のフォトレジストパターン
形成方法。5. The method according to claim 1, wherein said phase inversion pattern is formed of chromium having a transmittance of 10%.
2フォトマスクを前記ステップに同一である条件で装着
して相互重畳される場合、前記第1フォトマスクのクロ
ムパターンと前記第2フォトマスクの位相反転物パター
ンは同一である位置になり、前記第1フォトマスクの位
相反転物パターンと前記第2フォトマスクのクムパター
ンは同一である位置になることを特徴とする半導体素子
のフォトレジストパターン形成方法。6. The chromium pattern of the first photomask and the second photomask, wherein the first and second photomasks are mounted under the same condition as in the step and overlap each other. The phase shifter pattern of the photomask is located at the same position, and the phase shifter pattern of the first photomask and the comb pattern of the second photomask are located at the same position. A method for forming a resist pattern.
4フォトマスクを前記ステップに同一である条件で装着
し相互重畳させる場合、前記第3フォトマスクのクロム
パターンと前記第4フォトマスクの位相反転物パターン
は同一である位置になり、前記第3フォトマスクの位相
反転物パターンと前記第4フォトマスクのクロムパター
ンは同一である位置になることを特徴とする半導体素子
のフォトレジストパターン形成方法。7. The chromium pattern of the third photomask and the fourth photomask according to claim 1, wherein the third and fourth photomasks are mounted under the same conditions as in the step and overlap each other. Wherein the phase inversion pattern of the third photomask is at the same position, and the phase inversion pattern of the third photomask and the chrome pattern of the fourth photomask are at the same position. Forming method.
2フォトマスクのうち、いずれかの一つと前記第3及び
第4フォトマスクのうち、いずれかの一つを前記ステッ
プに同一である条件で装着し相互重畳させる場合、前記
第1または第2フォトマスクのクロムパターンと位相反
転物パターンは前記第3または第4フォトマスクのクロ
ムパターンと位相反転物パターンの間で重畳されること
を特徴とする半導体素子のフォトレジストパターン形成
方法。8. The method according to claim 1, wherein one of said first and second photomasks and one of said third and fourth photomasks are the same as said step. In a case where the chrome pattern and the phase inversion pattern of the first or second photomask are superposed between the chrome pattern and the phase inversion pattern of the third or fourth photomask when they are mounted and superimposed on each other under certain conditions. A method for forming a photoresist pattern of a semiconductor device, comprising:
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940002240A KR970005682B1 (en) | 1994-02-07 | 1994-02-07 | Fine patterning method of semiconductor device |
KR94-2240 | 1994-02-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0845834A JPH0845834A (en) | 1996-02-16 |
JP2801867B2 true JP2801867B2 (en) | 1998-09-21 |
Family
ID=19376920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7017754A Expired - Fee Related JP2801867B2 (en) | 1994-02-07 | 1995-02-06 | Method for forming photoresist pattern of semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (1) | US5532114A (en) |
JP (1) | JP2801867B2 (en) |
KR (1) | KR970005682B1 (en) |
DE (1) | DE19503985B4 (en) |
GB (1) | GB2286256B (en) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5811222A (en) * | 1996-06-24 | 1998-09-22 | Advanced Micro Devices, Inc. | Method of selectively exposing a material using a photosensitive layer and multiple image patterns |
US5801088A (en) * | 1996-07-17 | 1998-09-01 | Advanced Micro Devices, Inc. | Method of forming a gate electrode for an IGFET |
JPH10209039A (en) * | 1997-01-27 | 1998-08-07 | Nikon Corp | Method and apparatus for projection exposure |
US6030752A (en) * | 1997-02-25 | 2000-02-29 | Advanced Micro Devices, Inc. | Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device |
US6121158A (en) * | 1997-08-13 | 2000-09-19 | Sony Corporation | Method for hardening a photoresist material formed on a substrate |
US6008085A (en) * | 1998-04-01 | 1999-12-28 | Vanguard International Semiconductor Corporation | Design and a novel process for formation of DRAM bit line and capacitor node contacts |
US6133599A (en) * | 1998-04-01 | 2000-10-17 | Vanguard International Semiconductor Corporation | Design and a novel process for formation of DRAM bit line and capacitor node contacts |
US6383719B1 (en) | 1998-05-19 | 2002-05-07 | International Business Machines Corporation | Process for enhanced lithographic imaging |
US6284413B1 (en) * | 1998-07-01 | 2001-09-04 | Agere Systems Guardian Corp. | Method of manufacturing semicustom reticles using reticle primitives and reticle exchanger |
KR100307631B1 (en) * | 1999-06-01 | 2001-09-29 | 윤종용 | Method for forming fine patterns of semiconductor device |
US6387596B2 (en) | 1999-08-30 | 2002-05-14 | International Business Machines Corporation | Method of forming resist images by periodic pattern removal |
US6322934B1 (en) | 1999-09-30 | 2001-11-27 | Lucent Technologies Inc. | Method for making integrated circuits including features with a relatively small critical dimension |
JP2001230186A (en) * | 2000-02-17 | 2001-08-24 | Hitachi Ltd | Method for manufacturing semiconductor integrated circuit device |
US6406950B1 (en) | 2000-12-07 | 2002-06-18 | Advanced Micro Devices, Inc. | Definition of small damascene metal gates using reverse through approach |
US6541166B2 (en) | 2001-01-18 | 2003-04-01 | International Business Machines Corporation | Method and apparatus for lithographically printing tightly nested and isolated device features using multiple mask exposures |
JP2004356469A (en) * | 2003-05-30 | 2004-12-16 | Renesas Technology Corp | Manufacturing method of semiconductor integrated circuit device |
DE10360536B4 (en) * | 2003-09-30 | 2006-12-21 | Infineon Technologies Ag | Method for inspecting masks of a mask set for a multiple exposure |
US20050202352A1 (en) * | 2004-03-11 | 2005-09-15 | Worcester Polytechnic Institute | Systems and methods for sub-wavelength imaging |
KR100880232B1 (en) * | 2007-08-20 | 2009-01-28 | 주식회사 동부하이텍 | Fineness mask, and method of forming mask pattern using the same |
CN106933064B (en) * | 2017-03-27 | 2018-11-09 | 上海华力微电子有限公司 | Realize the photoetching process of smaller line width |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4869999A (en) * | 1986-08-08 | 1989-09-26 | Hitachi, Ltd. | Method of forming pattern and projection aligner for carrying out the same |
JP2710967B2 (en) * | 1988-11-22 | 1998-02-10 | 株式会社日立製作所 | Manufacturing method of integrated circuit device |
US5217830A (en) * | 1991-03-26 | 1993-06-08 | Micron Technology, Inc. | Method of fabricating phase shifting reticles using ion implantation |
US5364716A (en) * | 1991-09-27 | 1994-11-15 | Fujitsu Limited | Pattern exposing method using phase shift and mask used therefor |
US5308741A (en) * | 1992-07-31 | 1994-05-03 | Motorola, Inc. | Lithographic method using double exposure techniques, mask position shifting and light phase shifting |
US5407785A (en) * | 1992-12-18 | 1995-04-18 | Vlsi Technology, Inc. | Method for generating dense lines on a semiconductor wafer using phase-shifting and multiple exposures |
-
1994
- 1994-02-07 KR KR1019940002240A patent/KR970005682B1/en not_active IP Right Cessation
-
1995
- 1995-01-31 GB GB9501897A patent/GB2286256B/en not_active Expired - Fee Related
- 1995-02-03 US US08/383,006 patent/US5532114A/en not_active Expired - Lifetime
- 1995-02-06 JP JP7017754A patent/JP2801867B2/en not_active Expired - Fee Related
- 1995-02-07 DE DE19503985A patent/DE19503985B4/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2286256A (en) | 1995-08-09 |
DE19503985A1 (en) | 1995-08-10 |
GB2286256B (en) | 1997-10-08 |
KR950025914A (en) | 1995-09-18 |
US5532114A (en) | 1996-07-02 |
JPH0845834A (en) | 1996-02-16 |
DE19503985B4 (en) | 2007-05-31 |
GB9501897D0 (en) | 1995-03-22 |
KR970005682B1 (en) | 1997-04-18 |
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