JPS6236823A - Resist pattern formation - Google Patents
Resist pattern formationInfo
- Publication number
- JPS6236823A JPS6236823A JP60176445A JP17644585A JPS6236823A JP S6236823 A JPS6236823 A JP S6236823A JP 60176445 A JP60176445 A JP 60176445A JP 17644585 A JP17644585 A JP 17644585A JP S6236823 A JPS6236823 A JP S6236823A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- sensitivity
- highly sensitive
- resist film
- coated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔概要〕
感度の異なるレジス1−を順に2回塗布することにより
、現像した後にレジストパターンのテーパがなくなるよ
うにする。DETAILED DESCRIPTION OF THE INVENTION [Summary] By sequentially applying resists 1- with different sensitivities twice, the taper of the resist pattern is eliminated after development.
本発明はレジストパターン形成方法に関するもので、さ
らに詳しく言えば、当該レジストを現像したときにテー
バが付かない、すなわち断面形状が良好なレジストパタ
ーンが得られるようにレジストを塗布する方法に関する
ものである。The present invention relates to a method for forming a resist pattern, and more specifically, to a method for applying a resist so that when the resist is developed, no tapering occurs, that is, a resist pattern with a good cross-sectional shape is obtained. .
半導体装置の製造においてポトエソチング工程は重要な
役割の工程である。ホトエソチング工程を順を追って説
明すると、先ず基板を洗浄してきれいにし、レジストを
塗布し、レジスト塗布後塗布膜中に残存する溶剤を除く
ためにプレベータと呼称される熱処理をなし、ホトマス
クの位置合せをなし、例えば紫外線を照射して露光をな
し、有機溶剤等で現像しレジストパターンを作り、エツ
チング前にレジストと基板との密着を良くするためにポ
ストベークといわれる熱処理をなし、エツチングを行い
、しかる後に不必要になったレジストを剥離除去する。2. Description of the Related Art In the manufacture of semiconductor devices, the poto-ethoting process is a process that plays an important role. To explain the photolithography process step by step, first, the substrate is cleaned and cleaned, a resist is applied, and after the resist is applied, a heat treatment called prebeta is performed to remove the solvent remaining in the coating film, and the photomask is aligned. For example, it is exposed to ultraviolet light, developed with an organic solvent, etc. to create a resist pattern, and before etching, a heat treatment called post-bake is performed to improve the adhesion between the resist and the substrate, and etching is performed. After that, the resist that is no longer needed is peeled off and removed.
第2図を参照すると、前記した露光において焦点(フォ
ーカス)が合っていると同図に21で示す両側がまっす
ぐに立った断面形状の良いレジストパターン21が得ら
れ、このレジストパターン21をマスクにして半導体基
板22をエツチングすると図に斜線を付けた部分22a
がエツチングされ、レジストパターン21と同じパター
ン22bが得られる。Referring to FIG. 2, when the focus is correct in the exposure described above, a resist pattern 21 with a good cross-sectional shape with straight sides shown as 21 in the same figure is obtained, and this resist pattern 21 can be used as a mask. When the semiconductor substrate 22 is etched by etching, a hatched area 22a in the figure is formed.
is etched, and a pattern 22b identical to the resist pattern 21 is obtained.
露光においてフォーカスがずれたりすると、光の散乱が
発生し、光が照射したところとそうでないところの切れ
目がぼけてきて、第3図に符号3Iを付して示すような
テーパした断面形状の良くないレジストパターン31が
作られる。このレジストパターン31をマスクに半導体
基板32をエツチングすると、斜線を付した部分32a
が除去され、レジストパターン31とほぼ同じようにテ
ーパしたパターン32bが半導体基板32に作られる。If the focus shifts during exposure, light scattering occurs, and the line between the areas irradiated with light and the areas that are not irradiated becomes blurred, resulting in a sharp cross-sectional shape with a tapered shape, as shown with reference numeral 3I in Figure 3. A resist pattern 31 is created. When the semiconductor substrate 32 is etched using this resist pattern 31 as a mask, the diagonally shaded portion 32a is etched.
is removed, and a tapered pattern 32b substantially similar to the resist pattern 31 is formed on the semiconductor substrate 32.
レジストパターン31の上方の幅aと下方の幅すとの比
率(a/b)はフォーカスずれの程度によって異なるが
、60°〜80°の範囲の比率の場合が比較的に多い。The ratio (a/b) between the upper width a and the lower width of the resist pattern 31 varies depending on the degree of defocus, but is relatively often in the range of 60° to 80°.
そうなると、マスクのパターンどおりのパターンが基板
に形成されなくなる問題がある。In this case, there is a problem that a pattern exactly matching the pattern of the mask cannot be formed on the substrate.
本発明はこのような点に鑑みて創作されたもので、フォ
ーカスずれがあったとしてもテーパしなくまっすぐに立
った断面形状の良好がレジストパターンが得られるよう
なレジストの塗布方法を提供することを目的とする。The present invention was created in view of the above points, and an object of the present invention is to provide a resist coating method that can obtain a resist pattern with a good straight cross-sectional shape without tapering even if there is a focus shift. With the goal.
C問題点を解決するための手段〕
第1図(alと山)は本発明の方法を実施する工程にお
けるレジス日東を示す断面図である。Means for Solving Problem C] FIG. 1 (al and mountains) is a sectional view showing Regis Nitto in the process of carrying out the method of the present invention.
先ず、同図(alに示される如く基板例えば半導体基板
11上に高感度レジストを塗布して高感度レジスト膜1
2を作り、プレヘークすることなく低感度レジストを塗
布すると、最上層には低感度レジスト膜13が形成され
、高感度レジスト膜12と低感度レジスト膜13の間に
は感度変化領域14が形成される。しかる後にプレヘー
クし、従来の工程どおり、露光、現像を行うものである
。First, as shown in FIG.
2 and apply a low-sensitivity resist without pre-haking, a low-sensitivity resist film 13 is formed on the top layer, and a sensitivity change region 14 is formed between the high-sensitivity resist film 12 and the low-sensitivity resist film 13. Ru. Thereafter, the film is pre-haked, exposed and developed as in conventional processes.
上記の如くにして形成したレジスト膜においては、少量
の光に対して残る(抜けない)方向にある低感度レジス
トが最上層に、また少量の光に対してな(なる(抜ける
)方向にある高感度レジストが最下層にあるので、第3
図に示した如きテーパの発生が防止され断面形状が良好
なレジストパターンが得られるのである。In the resist film formed as described above, the low-sensitivity resist in the direction in which it remains (does not come out) with respect to a small amount of light is the top layer, and the resist in the direction in which it remains (does not come out) in response to a small amount of light is the top layer, and the resist film in the direction in which it remains (does not come out) in response to a small amount of light is the top layer. Since the high-sensitivity resist is on the bottom layer, the third
The taper shown in the figure is prevented from occurring and a resist pattern with a good cross-sectional shape can be obtained.
以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
第3図に戻ると、レジストパターン31がテーパした断
面形状になる理由は、光の散乱によりレジストの下方部
分に照射される光量が上方部分に比べて低下するために
、上方部分が抜ける(現像によってなくなる)のに対し
、下方部分が十分に、すなわち上方部分と同程度に抜け
ない(現像後に残る)からである。Returning to FIG. 3, the reason why the resist pattern 31 has a tapered cross-sectional shape is that due to light scattering, the amount of light irradiated to the lower part of the resist is lower than that to the upper part, so that the upper part disappears (developing This is because the lower part does not come off sufficiently, that is, to the same extent as the upper part (remains after development).
そこで、本発明においては、第1図falに示される如
く、基板例えば半導体基板(11)のすぐ上には高感度
レジストを塗布して高感度レジスト膜12を作る。レジ
スト塗布前にはレジストと半導体基板の密着性を良くす
るために、通常の技術で基板表面を洗浄などによってき
れいにしておく。高感度レジストは例えば商品名、東京
応化0PPR−5000の如きものを用いる。高感度レ
ジスト膜′12の膜厚は、通常1μm程度の厚さのレジ
スト膜を用いてエツチングをなすので、次工程で低感度
レジストが塗布されることを予定して低感度レジスト膜
よりもより厚く例えば0.6μm程度の厚さにする。Therefore, in the present invention, as shown in FIG. 1, a high-sensitivity resist film 12 is formed by coating a high-sensitivity resist immediately on a substrate, for example, a semiconductor substrate (11). Before applying the resist, the surface of the substrate is cleaned using conventional techniques, such as cleaning, in order to improve the adhesion between the resist and the semiconductor substrate. As the high-sensitivity resist, for example, a product such as Tokyo Ohka 0PPR-5000 is used. The film thickness of the high-sensitivity resist film '12 is usually made using a resist film with a thickness of about 1 μm for etching. The thickness is set to be about 0.6 μm, for example.
レジスト塗布は通常のスピンコーティングでなす。The resist is applied by ordinary spin coating.
続いて、プリベータなどの熱処理をなすことなく、低感
度レジスト、例えば商品名、東京応化0FPR−800
の如きものを0.4μmの厚さに塗布し低感度レジスト
膜13を形成する。そうすると、高感度レジストはまだ
硬化していないし、低感度レジストも硬化していないの
で、高感度レジスト膜12と低感度レジスト膜13の中
間には、双方のレジストがまじり合って作られた感度変
化領域14が作られ、これらのレジストの感度を全体的
にみると、基板11の側から高感度から低感度へ徐々に
変化するほぼ1μmの厚さのレジスト塗布が提供され、
露光において、フォーカスのぼけのために光量が低下し
ても、高感度レジストも感度変化領域のレジス1へも最
上層の低感度レジストとほぼ同じ程度に抜けることにな
り、両側がまっすぐに立った、すなわちテーバの付かな
いレジストパターンが得られることになる。Subsequently, a low-sensitivity resist, such as the trade name Tokyo Ohka 0FPR-800, is applied without heat treatment such as pre-beta.
A low-sensitivity resist film 13 is formed by applying a material such as the following to a thickness of 0.4 μm. Then, since the high-sensitivity resist has not yet hardened and the low-sensitivity resist has also not hardened, there is a sensitivity change between the high-sensitivity resist film 12 and the low-sensitivity resist film 13 that is created by mixing both resists. Regions 14 are created, and the overall sensitivity of these resists provides a resist application with a thickness of approximately 1 μm that gradually changes from high to low sensitivity from the side of the substrate 11;
During exposure, even if the amount of light decreases due to defocusing, the high-sensitivity resist and the sensitivity change area (Register 1) pass through to almost the same extent as the low-sensitivity resist on the top layer, so both sides stand straight. In other words, a resist pattern without tapering can be obtained.
なお、」二記の説明は半導体基板のエツチングについて
述べたが、本発明の適用範囲はその場合に限定されるも
のではなく、レジスト塗布一般の場合に及ぶものである
。Incidentally, although the explanation in item 2 has been made regarding etching of a semiconductor substrate, the scope of application of the present invention is not limited to that case, but extends to resist coating in general.
以上性べてきたように、本発明によればレジストパター
ンの断面形状が改善され、テーバが付くことが防止され
、エツチング形状やレジスト幅の制御に有効である。As described above, the present invention improves the cross-sectional shape of the resist pattern, prevents tapering, and is effective in controlling the etching shape and resist width.
第1図(a)と(blは本発明方法実施工程におけるレ
ジスト膜の断面図、
第2図は断面形状の良好なレジストパターンの断面図、
第3図はテーバした断面形状のレジストパターンの断面
図である。
第1図において、
11は半導体基板、
12ば高感度レジスト膜、
13は低感度レジスト塗布、
14は感度変化領域である。Figures 1 (a) and (bl) are cross-sectional views of the resist film in the process of implementing the method of the present invention; Figure 2 is a cross-sectional view of a resist pattern with a good cross-sectional shape; Figure 3 is a cross-sectional view of a resist pattern with a tapered cross-sectional shape. In FIG. 1, 11 is a semiconductor substrate, 12 is a high-sensitivity resist film, 13 is a low-sensitivity resist coating, and 14 is a sensitivity change region.
Claims (1)
理をすることなく高感度レジスト膜(12)の上に低感
度レジストを塗布し、しかる後露光、現像をしてパター
ニングすることを特徴とするレジストパターン形成方法
。The method is characterized in that a high-sensitivity resist is coated on a substrate (11), then a low-sensitivity resist is coated on a high-sensitivity resist film (12) without heat treatment, and then exposed and developed for patterning. A resist pattern forming method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60176445A JPS6236823A (en) | 1985-08-10 | 1985-08-10 | Resist pattern formation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60176445A JPS6236823A (en) | 1985-08-10 | 1985-08-10 | Resist pattern formation |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6236823A true JPS6236823A (en) | 1987-02-17 |
Family
ID=16013826
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60176445A Pending JPS6236823A (en) | 1985-08-10 | 1985-08-10 | Resist pattern formation |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6236823A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01273030A (en) * | 1988-04-26 | 1989-10-31 | Fujitsu Ltd | Production of semiconductor device |
WO2006137582A1 (en) * | 2005-06-24 | 2006-12-28 | Fujifilm Corporation | Exposure method and apparatus |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58171818A (en) * | 1982-03-31 | 1983-10-08 | Matsushita Electric Ind Co Ltd | Method and apparatus for manufacturing semiconductor device |
JPS58218119A (en) * | 1982-06-14 | 1983-12-19 | Hitachi Ltd | Pattern forming method |
JPS59175725A (en) * | 1983-03-26 | 1984-10-04 | Toshiba Corp | Multilayer resist film |
-
1985
- 1985-08-10 JP JP60176445A patent/JPS6236823A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58171818A (en) * | 1982-03-31 | 1983-10-08 | Matsushita Electric Ind Co Ltd | Method and apparatus for manufacturing semiconductor device |
JPS58218119A (en) * | 1982-06-14 | 1983-12-19 | Hitachi Ltd | Pattern forming method |
JPS59175725A (en) * | 1983-03-26 | 1984-10-04 | Toshiba Corp | Multilayer resist film |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01273030A (en) * | 1988-04-26 | 1989-10-31 | Fujitsu Ltd | Production of semiconductor device |
WO2006137582A1 (en) * | 2005-06-24 | 2006-12-28 | Fujifilm Corporation | Exposure method and apparatus |
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