JP2014063901A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can form resist patterns on both of a surface region having a larger level difference and a surface region having a smaller level difference in a wafer surface with high resolution.SOLUTION: A semiconductor device manufacturing method for a semiconductor wafer 2 which has a level difference formed by a first surface 2a and a second surface 2b lower than the first surface 2a comprises: a first exposure process of providing a positive photoresist layer 1 on the second surface in a manner such that a height of a surface of the second surface is restricted to be lower than a height of the first surface and selectively exposing the resist layer 1; a process of removing the exposed part by developing the positive photoresist layer; a second exposure process of exposing the first resist pattern to laminate a positive photoresist layer; a third exposure process of exposing a part on the first surface 2a and a part stacked on the first resist pattern; and a process of removing the exposed part by developing the first resist pattern and the positive photoresist layer to form second resist patterns 17a, 17b.

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that performs photoresist patterning using a photolithography technique.

  Conventionally, as disclosed in, for example, the following Patent Document 1 (Japanese Patent Laid-Open No. 4-99016), there has been an improved method for manufacturing a semiconductor device with respect to a technique for forming a resist pattern on a semiconductor wafer having a step. Are known. Hereinafter, the photoresist may be simply referred to as a resist for convenience. When patterning using a projection optical system in photolithography, it is necessary to adjust the focus of the projection optical system appropriately. The depth of focus means a range in which sufficient resolving power can be obtained before and after the focus when the focus of the optical system is shifted. For semiconductor wafers having irregularities (steps) whose height does not exceed the depth of focus, resist patterning by photolithography can be performed in a common process on the high and low steps.

  However, if the height of the unevenness of the semiconductor wafer greatly exceeds the effective range of the depth of focus, exposure is commonly performed on the concave surface (the surface on the lower step side) and the convex surface (the surface on the higher step side). I can't do it. That is, when focusing on the concave portion of the semiconductor wafer, the pattern contrast at the convex portion becomes insufficient. On the contrary, when the focus is adjusted by the convex portion of the semiconductor wafer, the pattern contrast in the concave portion becomes insufficient. Thus, depending on the size of the step, accurate resist patterning may be difficult.

  In this way, in a semiconductor wafer having irregularities, when the step due to the irregularities is larger than the depth of focus of the projection optical system that performs the exposure, a desired pattern cannot be obtained or formed accurately. There's a problem. This is because the pattern contrast in the region exceeding the depth of focus falls below a threshold value at which the resist can be patterned.

  Therefore, in Patent Document 1, exposure is performed at a first focal position on a resist on a surface with a high level difference, and exposure is performed at a second focal position on a resist on a surface with a low level difference. I have to. Thereby, it is possible to expose the resist so as to cover a focal position shift due to a step and to obtain a sufficient pattern contrast even if the semiconductor wafer is uneven.

Japanese Patent Laid-Open No. 4-99016 JP-A-4-107915

  However, the technique according to Patent Document 1 has the following problems. That is, in Patent Document 1, it is assumed that the resist is provided across both the convex part and the concave part of the step when applying the resist to the step of the semiconductor wafer. In this case, the resist inevitably has a certain thickness. In this case, the patterning for the thick resist must be one that forms a deep opening, that is, one that has a high aspect ratio. In general, it is difficult to form a high-resolution resist pattern because fine patterning is difficult in high aspect ratio patterning. The prior art still has room for improvement in this regard.

  The present invention has been made to solve the above-described problems, and provides a method for manufacturing a semiconductor device capable of forming a resist pattern with high resolution on both a high and low step surface on a semiconductor wafer surface. The purpose is to provide.

A method for manufacturing a semiconductor device according to the present invention includes:
Preparing a semiconductor wafer having a step formed by a first surface and a second surface located next to the first surface and lower than the first surface;
Providing a first resist layer on the second surface such that the height of the surface is equal to or less than the height of the first surface;
A first exposure step of selectively exposing the first resist layer;
Removing the exposed portion in the first exposure step by developing the first resist layer, and forming a first resist pattern;
A second exposure step of exposing the first resist pattern;
After the second exposure step, a step of laminating a second resist layer on the first surface and the first resist pattern;
A third exposure step of exposing a portion of the second resist layer on the first surface and a portion of the second resist layer stacked on the first resist pattern;
After the third exposure step, the exposed portion is removed by developing the first resist pattern and the second resist layer to form a second resist pattern;
It is characterized by providing.

  According to the present invention, it is possible to form a resist pattern with high resolution on both a high-level surface (first surface) and a low-level surface (second surface) on the semiconductor wafer surface. The step (first surface) and the lower surface (second surface) are higher than the step using the resist pattern in common on the surface (first surface) and the surface (second surface) where the step is high. A high-resolution fine structure can be formed at a time.

It is a figure which shows the manufacture process of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a figure which shows the manufacture process of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a figure which shows the manufacture process of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a figure which shows the manufacture process of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a figure which shows the manufacture process of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a figure which shows the manufacture process of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a figure which shows the manufacture process of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a figure which shows the manufacture process of the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a flowchart which shows the manufacture flow of the manufacturing method of the semiconductor device concerning embodiment of this invention.

Embodiment.
Hereinafter, embodiments of the present invention will be described with reference to FIGS. FIGS. 1-8 is a figure which shows the manufacturing process of the manufacturing method of the semiconductor device concerning embodiment of this invention. FIG. 9 is a flowchart showing a manufacturing flow of the semiconductor device manufacturing method according to the embodiment of the present invention.

  In the manufacturing method according to the present embodiment, first, a process of preparing the semiconductor wafer 2 is performed (step S100). Although the process of this step is not shown, the semiconductor wafer 2 shown in FIG. 1 and subsequent figures is prepared. The semiconductor wafer 2 includes a step formed by the first surface 2a and the second surface 2b. The second surface 2b is located next to the first surface 2a and is lower than the first surface 2a. The height of the step is the height of the step side surface 2c. The height of the step is higher than the effective depth of focus of the projection optical system (stepper) used in the subsequent exposure process. Hereinafter, the “portion on the first surface 2a on the semiconductor wafer 2” is also referred to as a protrusion 2d, and the “portion on the second surface 2b in the semiconductor wafer 2” is also referred to as a recess 2e.

  Next, as shown in FIGS. 1 and 2, the positive photoresist layer 1 (first resist layer) is formed on the second surface 2b so that the height of the surface is equal to or lower than the height of the first surface 2a. The process of providing is performed. In the present embodiment, in this step, first, as shown in FIG. 1, a step of applying a positive photoresist layer 1 on the semiconductor wafer 2 is performed (step S102). The resist coating is performed by a spin coat method using a spin coater. In FIG. 1, a positive photoresist layer 1 is laminated on a semiconductor wafer 2. The positive photoresist layer 1 is preferably one that can be patterned with g-line to i-line. High-pressure mercury lamp g-line (wavelength 436 nm) h-line (wavelength 405 nm) i-line (wavelength 365 nm). This is because the depth of focus is relatively large particularly in projection exposure, and is suitable for use in the present embodiment.

  Next, a pre-bake process is performed on the positive photoresist layer 1 (step S104). The positive photoresist layer 1 is applied to the semiconductor wafer 2 and prebaked at 90 to 170 ° C. to volatilize the solvent contained in the positive photoresist layer 1.

Next, in the present embodiment, as shown in FIG. 2, the positive photoresist layer 1 is immersed in a liquid for dissolving the positive photoresist layer 1 until the positive photoresist layer 1 remains only in the recess 2e of the semiconductor wafer 2 (see FIG. Step S106). Thereby, the film thickness of the positive photoresist layer 1 in the recessed part 2e can be set freely.
The solution used here is preferably one in which the dissolution rate can be controlled by the mixing ratio of the liquid that dissolves the positive photoresist layer 1 and the liquid that does not dissolve it. This is because the film thickness to be dissolved differs depending on the level difference of the semiconductor wafer 2 to be processed and the film thickness at the time of application of the positive photoresist layer 1. In particular, it is preferable to use a solution obtained by diluting normal butyl acetate with isopropyl alcohol. This is because it has excellent controllability in controlling the dissolution rate of commonly used positive resists, is easy to obtain and handle, and has little danger.

  It is important to keep the positive photoresist layer 1 only on the bottom surface of the recess 2e and to control the resist film thickness of the recess 2e in order to maintain controllability of the pattern size of the recess 2e. Therefore, the dissolution rate is adjusted by diluting the solution so that the dimensional control of the pattern is 100 nm / sec or less. The dissolution rate is preferably 10 nm / sec to 50 nm / sec.

Next, as shown in FIG. 3, a first exposure step of selectively exposing the positive photoresist layer 1 is performed (step S108).
In FIG. 3, the photomask 3 has a pattern with a width of 1 μm or more. The exposed positive photoresist 4 is one in which the positive photoresist layer 1 is exposed.

  Next, as shown in FIG. 4, the positive photoresist layer 1 is developed to remove the portion exposed in the first exposure process, thereby forming a first resist pattern 11 (step S110). As shown in FIG. 3, the photomask 3 is used for exposure and further development to obtain the structure shown in FIG.

  Next, as shown in FIG. 5, a second exposure process for exposing the first resist pattern 11 is performed (step S112). In this step, as shown in FIG. 5, the first resist pattern 11 is exposed by exposing the entire surface of the semiconductor wafer 2. Since the positive photoresist layer 1 is used, the first resist pattern 11 formed in the recess 2e is dissolved in the developer by the exposure of the entire surface of the semiconductor wafer 2.

  Next, as shown in FIG. 6, after the second exposure step, a positive photoresist layer 5 (second resist layer) is laminated so as to overlap the first surface 2 a and cover the first resist pattern 11. The process to perform is performed (step S114). In FIG. 6, a positive photoresist layer 5 is applied. The positive photoresist layer 5 is also preferably one that can be patterned with g-line to i-line. The positive photoresist layer 1 and the positive photoresist layer 5 are preferably the same resist material. “The resist material is the same” means that the material, the solvent and the sensitivity are the same. Specifically, it is a preparation with the same product name and the same standard. Thereby, the resist coating apparatus can be made common in step S102 and step S114.

  Further, a pre-baking process is performed (step S116). Here, after the positive type photoresist layer 5 is applied as shown in FIG. 6, it is pre-baked at 90 to 120.degree. In particular, heating at 120 ° C. or more for 3 minutes or more is not preferable because the interface between the resists is mixed and the pattern of the recesses 2e is not resolved during development. Therefore, the temperature at which the solvent volatilizes and does not mix is preferably 90 to 100 ° C., and the time is preferably less than 3 minutes. If the upper limit of the temperature range or the like is exceeded, the previously formed first resist pattern 11 is deformed, making it difficult to form the pattern.

Next, as shown in FIG. 7, a third exposure step is performed (step S118). In the third exposure step, both "a part of the positive photoresist layer 5 on the first surface 2a" and "a part of the positive photoresist layer 5 stacked on the first resist pattern" On the other hand, exposure is performed simultaneously.
In FIG. 7, a photomask 6 is a photomask having a pattern of 1 μm or more in which the exposed portion and the light shielding portion of the photomask 3 are reversed. The exposed positive photoresist 7 is one in which “a portion of the positive photoresist layer 5 stacked on the first resist pattern” is exposed by the third exposure step.
Note that the photomask 3 and the photomask 6 do not have to have a relationship in which the exposure portion and the light shielding portion are reversed. As a modification, the photomask 3 may be a photomask having a pattern of only the recesses 2e. The photomask 6 may be a photomask composed of a pattern of the concave portions 2e and the convex portions 2d. In this case, the two photomasks do not correspond to the inverted pattern.

  Next, as shown in FIG. 8, after the third exposure step, the exposed portion is removed by developing the first resist pattern and the positive photoresist layer 5, and the second resist pattern 17a and the second resist pattern 17b are removed. A developing process for forming the film is performed (step S120). By performing exposure using a photomask 6 as shown in FIG. 7 and further development, a pattern outside the effective range of the focal depth in the recess 2e of the semiconductor wafer 2 is also resolved. As shown in FIG. Patterns (second resist pattern 17a and second resist pattern 17b) can be formed on 2e and convex portion 2d, respectively. The developer used at this time is the same as the developer used in making the structure of FIG. In particular, a solution obtained by diluting tetramethylammonium hydroxide with water to about 2 to 3 wt% is desirable. This is because it is most commonly used for developing a positive photoresist.

  Thereafter, a fine structure can be formed on the semiconductor wafer 2 by performing etching or film formation using the second resist pattern 17a and the second resist pattern 17b.

  According to the manufacturing method according to the present embodiment described above, when a resist pattern is formed on a surface having a high step (first surface) and a surface having a low step (second surface), the surface having a low step (second surface). Can be formed with high resolution. By using this resist pattern, a fine structure with high resolution can be formed on a surface with a high level difference (first surface) and a surface with a low level (second surface).

  The step of providing the positive photoresist layer 1 according to the present embodiment includes an application step (step S102) of applying the first resist layer to the second surface, and the thickness of the positive photoresist layer 1 after this application step. And a process for reducing the thickness (step S106). However, the present invention is not limited to this. From the beginning, the positive photoresist layer 1 may be applied to a thickness not higher than the step side surface 2c. The coating method may be a spin coating method using a spin coater or a spray coating method using a spray coater.

  Various applications of the semiconductor device manufacturing method according to the present embodiment are conceivable. For example, in the processing step after the ridge formation of the ridge type semiconductor laser, the semiconductor wafer has irregularities due to the ridge, so that this embodiment can be used. The present embodiment can also be used when processing (such as providing an opening to form a contact hole with an electrode) is performed on an insulating film to be positioned immediately below the electrode of the ridge type semiconductor laser.

  In addition, although the method (refer patent document 2) of performing patterning and a process separately to a convex part and a recessed part, respectively is considered, in this case, a resist patterning and a process process must be repeated in multiple times. As a result, the wafer processing process becomes complicated, which may lead to pattern variations and a decrease in processing accuracy. In this regard, according to the present embodiment, the processing step can be performed after the exposure step is repeated a plurality of times to form the second resist pattern 17a and the second resist pattern 17b. The problem of reduced accuracy can be avoided.

DESCRIPTION OF SYMBOLS 1 Positive type photoresist layer, 2 Semiconductor wafer, 2a 1st surface, 2b 2nd surface, 2c Step side surface, 2d Convex part, 2e Concave, 3 Photomask, 4 Photosensitized positive type photoresist, 5 Positive type photo resist Resist, 6 photomask, 7 exposed positive photoresist, 11 first resist pattern, 17a second resist pattern, 17b second resist pattern

Claims (8)

Preparing a semiconductor wafer having a step formed by a first surface and a second surface located next to the first surface and lower than the first surface;
Providing a first resist layer on the second surface such that the height of the surface is equal to or less than the height of the first surface;
A first exposure step of selectively exposing the first resist layer;
Removing the exposed portion in the first exposure step by developing the first resist layer, and forming a first resist pattern;
A second exposure step of exposing the first resist pattern;
After the second exposure step, a step of laminating a second resist layer on the first surface and the first resist pattern;
A third exposure step of exposing a portion of the second resist layer on the first surface and a portion of the second resist layer stacked on the first resist pattern;
After the third exposure step, the exposed portion is removed by developing the first resist pattern and the second resist layer to form a second resist pattern;
A method for manufacturing a semiconductor device, comprising: The first exposure step is to perform exposure using a first photomask having a first mask pattern on the second surface;
The third exposure step uses the second photomask having a second mask pattern in which an exposure position and a non-exposure position on the second surface are reversed with respect to the first mask pattern. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second resist layer is exposed. The step of providing the first resist layer includes:
An application step of applying the first resist layer to the second surface;
A thinning step for reducing the thickness of the first resist layer after the coating step;
The method for manufacturing a semiconductor device according to claim 1, wherein: The thinning step includes a step of thinning the applied first resist layer by immersing the first resist layer in a liquid,
4. The method of manufacturing a semiconductor device according to claim 3, wherein the liquid is a solution obtained by diluting normal butyl acetate with isopropyl alcohol.   5. The semiconductor device manufacturing method according to claim 1, wherein the resist material of the first resist layer and the resist material of the second resist layer have the same material, solvent, and sensitivity. 6. Method.   The semiconductor device according to claim 1, wherein the first resist layer and the second resist layer are made of a resist material that can be patterned with g-line to i-line. Method.   The semiconductor device according to claim 1, further comprising a step of performing pre-baking at 90 ° C. to 120 ° C. for less than 3 minutes after the second resist layer is stacked. Production method.   8. The semiconductor according to claim 1, wherein the developing step uses tetramethylammonium hydroxide diluted with water to a concentration of 2 wt% to 3 wt% as a developing solution. Device manufacturing method.

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