JPS6045021A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6045021A JPS6045021A JP58153766A JP15376683A JPS6045021A JP S6045021 A JPS6045021 A JP S6045021A JP 58153766 A JP58153766 A JP 58153766A JP 15376683 A JP15376683 A JP 15376683A JP S6045021 A JPS6045021 A JP S6045021A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- resist
- layer resist
- upper layer
- development
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
Landscapes
- Engineering & Computer Science (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor device.
従来、半導体装置の製造工程には、レジスト膜の多層構
造を利用してパターニングを行う所謂写真蝕刻工程が設
けられている。すなわち、先ず、パターニングを行う半
導体基板上に、例えばポリメタクリル酸メチル（Ｐ Ｍ
Ｍ Ａ ）からなるレジスト膜を形成し、その上層に
紫外線用のレジスト膜を形成する。次いで、上層のレジ
スト膜の所定領域に選択的に開口部を形成する。Conventionally, the manufacturing process of semiconductor devices includes a so-called photolithography process in which patterning is performed using a multilayer structure of a resist film. That is, first, for example, polymethyl methacrylate (P M
A resist film made of M A ) is formed, and a resist film for ultraviolet rays is formed on top of the resist film. Next, openings are selectively formed in predetermined regions of the upper resist film.
次いで、この開口部を有するレジスト膜をマスクにして
、下層のレジスト膜に遠紫外線を照射し、開口部を形成
する。これらのレジスト膜をマスクにして半導体基板に
所定の７４ターニングを施す。Next, using the resist film having the opening as a mask, the underlying resist film is irradiated with deep ultraviolet rays to form the opening. Using these resist films as a mask, a predetermined 74 turns are applied to the semiconductor substrate.
上述のような写真蝕刻工程を備えた従来の半導体装置の
製造方法では、遠紫外線用のレジストとして主にＰＭＭ
Ａ系レジストが使用されている。しかし、ＰＭＭＡ系レ
ジメしＵ感度が悪く、露光時間が長くなる。更に耐エツ
チング性が悪い。In the conventional semiconductor device manufacturing method that includes the photolithography process described above, PMM is mainly used as a resist for deep ultraviolet rays.
A series resist is used. However, the PMMA-based regimen has poor sensitivity and requires a long exposure time. Furthermore, the etching resistance is poor.
ＰＭＭＡ系レジストよりも感度の良いＩリメチルイソペ
ニルケトン（ＰＭＩＰＫ）系レシストを使用すると、露
光時間を短縮できるが、他のレジストとの相溶性が強い
ため隣接するレジスト膜との関係で塗布むらが起きる。Exposure time can be shortened by using I-trimethyl isopenyl ketone (PMIPK) resist, which has higher sensitivity than PMMA resist, but it has strong compatibility with other resists, so it must be applied in relation to the adjacent resist film. Unevenness occurs.
また、現像時に隣接するレジスト膜が溶解するため、微
細パターンの形成を達成できない。更に、リフトオフ構
造を可能にするレジスト膜の積層を実現できない問題が
あった。Furthermore, since adjacent resist films are dissolved during development, formation of fine patterns cannot be achieved. Furthermore, there was a problem in that it was not possible to realize a stack of resist films that would enable a lift-off structure.
本発明は、レジスト膜の解像性を高め、かつ露光時間を
短縮すると共に、それに付随して起こる■レジスＩａ布
中のレジスト間の溶解による塗布むら、■溶解性のない
レジストの組み合せでも現像中に他の現像液にレジスト
が溶解してしまう。などの問題点をも解決した半導体装
置の製造方法を提供することをその目的とするものであ
る。The present invention improves the resolution of the resist film, shortens the exposure time, and also eliminates the accompanying problems of (1) coating unevenness due to dissolution between resists in the resist Ia cloth, and (2) developing a combination of resists that are not soluble. The resist will be dissolved in other developer. It is an object of the present invention to provide a method for manufacturing a semiconductor device that solves the problems such as the above.
またレジストの組み合せが上記問題により困難と判断さ
れていた多層レジスト構造を可能にする。Furthermore, the combination of resists makes it possible to create a multilayer resist structure, which has been considered difficult due to the above-mentioned problems.
本発明は、露光、現像、ベークの工程間に、再露光工程
或はベーク工程を設けて、レジスト膜の解像性を高め、
かつ、露光時間を短縮すると共に、塗布中のレゾスト溶
解性による塗布むら、レジスト残り全なくシ、シかも工
程の短縮を達成した半導体装置の製造方法である。The present invention improves the resolution of the resist film by providing a re-exposure step or a baking step between the exposure, development, and baking steps.
In addition, this method of manufacturing a semiconductor device can shorten the exposure time, eliminate coating unevenness due to the solubility of the resist during coating, eliminate any residual resist, and shorten the process.
以下、本発明の％ Ｙｍ Ｍについて図面を参照して説
明する。Hereinafter, % Ym M of the present invention will be explained with reference to the drawings.
先ず、第１図＜Ａｌに示す如く、所定の素子を形成した
半導体基板１上に下層のレジスト膜２として例えばポリ
メチルインベニルケトン（ＰＭＩＰＫ）例えば０ＤＯＲ
−１０１４（東京応化社ｆＭ）からなるものを形成し、
プリベーク処理を施す。次いで、同図（Ｂ）に示す如く
、固化したレジスト膜２上に上層のレジスト膜３として
例えば紫外線用のレジスト（実施例としてＫｏｄａｋ（
長池産渠社製）からなるものを形成し、プリベーク処理
を施し、固化する。First, as shown in FIG. 1<Al, a lower resist film 2 of, for example, polymethyl inbenyl ketone (PMIPK), for example, 0DOR is deposited on a semiconductor substrate 1 on which predetermined elements are formed.
-1014 (Tokyo Ohkasha fM),
Perform pre-bake treatment. Next, as shown in FIG. 2B, an upper resist film 3 is formed on the solidified resist film 2 using, for example, an ultraviolet resist (for example, Kodak (Kodak)).
(manufactured by Nagaike Sandosha), prebaked, and solidified.
次に、同図（Ｃ）に示す如く、上層のレジスト膜３上に
マスク４を載置して選択的に紫外光５を照射する。次い
で、現像を行い、上層のレジスト膜３に開口部６を同図
（Ｉｊに示す如く形成する。Next, as shown in FIG. 3C, a mask 4 is placed on the upper resist film 3 and ultraviolet light 5 is selectively irradiated. Next, development is performed to form an opening 6 in the upper resist film 3 as shown in the figure (Ij).
次に、開口部６ｆｔ、設けた上層のレジスト膜３′ｆｃ
マスクにして、下層のレジスト膜２に遠紫外光７ｆ、選
択的に照射する。次いで、これに実験的に１２０℃で２
０分間ベーク処理を施してから下層のレジスト膜２の現
像を行い開口部８を同図（Ｅ）に示す如く、形成する。Next, the opening 6ft and the upper resist film 3'fc
Using a mask, the lower resist film 2 is selectively irradiated with deep ultraviolet light 7f. This was then experimentally heated at 120°C for 2
After baking for 0 minutes, the lower resist film 2 is developed to form an opening 8 as shown in FIG.
然る後、これらのレジスト膜２．３ｆ、マスクにして半
導体基板１に所定のパターニングｔｌ−施した。このよ
うにして得られたレジスト膜２゜３の開口部６，８はＳ
ＥＭ写真より第２図に示す如く、リフトオフ処理の可能
な構造であり。Thereafter, using these resist films 2.3f as a mask, the semiconductor substrate 1 was patterned in a predetermined manner. The openings 6 and 8 of the resist film 2°3 thus obtained are S
As shown in Figure 2 from the EM photograph, it has a structure that can be subjected to lift-off treatment.
第３図に示すようなレジスト残り９や或は第４図や第５
図に示す如く、上下のレジスト膜２′。Resist remaining 9 as shown in Figure 3, or Figure 4 or 5.
As shown in the figure, upper and lower resist films 2'.
３′の溶力了速度の違いによる過剰開口部１０はできな
かった。No excessive opening 10 was formed due to the difference in the melting rate of 3'.
その結果、リフトオフ処理を行って作業性を高めると共
に、レジスト膜２，３の高い解像度の下で露光時間を短
縮し、しかも形状精度の高いノｆターニングを行うこと
ができる。なお、このレジスト膜２，３の解像度の向上
は、露光彼ベーク処理によって達成されるものであるが
、別のレジストの組み合せによっては（実施例上層０Ｆ
ＰＲ−８００（東京応化社製）、下層ＲＤ−２００ＯＮ
（日立化成社製））再露光を行っても同様の効果が得
られる。As a result, it is possible to perform lift-off processing to improve workability, shorten the exposure time under the high resolution of the resist films 2 and 3, and perform nof turning with high shape accuracy. The resolution of the resist films 2 and 3 can be improved by exposure baking, but it may be possible to improve the resolution of the resist films 2 and 3 by using a different resist combination.
PR-800 (manufactured by Tokyo Ohkasha), lower layer RD-200ON
(manufactured by Hitachi Chemical)) Similar effects can be obtained by re-exposure.
以上説明した如く、本発明に係る半導体装置の製造方法
によれば、レジスト膜の解像性を高め、かつ、露光時間
を短縮すると共に、塗布むら、レジスト残りをなくし、
しかも工程の短縮を達成できるものである。As explained above, according to the method for manufacturing a semiconductor device according to the present invention, the resolution of the resist film is improved, the exposure time is shortened, and uneven coating and resist residue are eliminated.
Moreover, the process can be shortened.
第１図囚乃至同図（島は、水元ｒＪ］方法を工程順に示
す説明図、第２図乃至第５図は、レジスト膜の開口部の
状態を示す断面図である。
１・・・半導体基板、２・・・レジスト膜、３・・・レ
ソスト膜、４・・・マスク、５°・・紫外光、６・・・
開口部。
７・・・遠紫外光、８・・・開口部、９・・・レジスト
残り、１０・・・過剰開口部。
出願人代理人 弁理士 鈴 江 武 彦第１図
策２図 、’Ｔ”、 ３ ｒ４
第４ 図＠５ ＭFigures 1 to 5 are explanatory diagrams showing the method in order of process. Figures 2 to 5 are cross-sectional views showing the state of the opening in the resist film. 1... Semiconductor substrate, 2... Resist film, 3... Resist film, 4... Mask, 5°... Ultraviolet light, 6...
Aperture. 7...Deep ultraviolet light, 8...Aperture, 9...Resist remaining, 10...Excess aperture. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1, Strategy 2, 'T', 3 r4 Figure 4 @5 M
Claims (1)
と、前記レジスト膜の最上層から順次選択的に露光処理
及び現像処理を施す工程とを具備する半導体装置の製造
方法において、レジスト膜上へのレジスト塗布、あるい
は現像中に起こるレジストの相溶性、又は不溶解部分の
溶解を防止する為露光処理と現像処理の間に再露光処理
またはベーク処理を施す工程を設けてかつリフト・オフ
構造を可能にしたことを特徴とする半導体装置の製造方
法。A method for manufacturing a semiconductor device comprising the steps of sequentially stacking a desired number of resist films on a semiconductor substrate, and sequentially selectively exposing and developing the resist films starting from the top layer. In order to prevent resist compatibility or dissolution of undissolved portions that occur during resist coating or development, a process of re-exposure or baking is provided between exposure and development, and a lift-off structure is provided. A method of manufacturing a semiconductor device characterized by making it possible.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58153766A JPS6045021A (en) | 1983-08-23 | 1983-08-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58153766A JPS6045021A (en) | 1983-08-23 | 1983-08-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6045021A true JPS6045021A (en) | 1985-03-11 |
Family
ID=15569660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58153766A Pending JPS6045021A (en) | 1983-08-23 | 1983-08-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6045021A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100607776B1 (en) | 2004-07-27 | 2006-08-01 | 동부일렉트로닉스 주식회사 | Method for forming hard mask in semiconductor lithography procedure |
-
1983
- 1983-08-23 JP JP58153766A patent/JPS6045021A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100607776B1 (en) | 2004-07-27 | 2006-08-01 | 동부일렉트로닉스 주식회사 | Method for forming hard mask in semiconductor lithography procedure |
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