JPS616830A - Pattern formation - Google Patents
Pattern formationInfo
- Publication number
- JPS616830A JPS616830A JP12791384A JP12791384A JPS616830A JP S616830 A JPS616830 A JP S616830A JP 12791384 A JP12791384 A JP 12791384A JP 12791384 A JP12791384 A JP 12791384A JP S616830 A JPS616830 A JP S616830A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- photo resist
- pattern
- dissolution rate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/143—Masks therefor
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は基板上に例えば電極配線等の薄膜の微細パター
ンを形成する場合のパターン形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pattern forming method for forming fine thin film patterns, such as electrode wiring, on a substrate.
従来例の構成とその問題点
半導体装置の電極配線パターン形成方法のひとつにリフ
トオフ法があり、素子の微細化、電極の多層金属化に適
した方法である。しかし、素子の高速化、低消費電力化
に伴い、電極配線膜厚を大きくする必要があり、そのた
めにはリフトオフの際のフォトレジスト膜厚も大きくし
なければならない。従来フォトレジスト膜厚を大きくす
るため現像液に対する溶解度の異なるフォトレジストを
用いた２層フォトレジスト工程がある。Conventional Structures and Their Problems One of the methods for forming electrode wiring patterns for semiconductor devices is the lift-off method, which is suitable for miniaturization of elements and multilayer metalization of electrodes. However, as devices become faster and consume less power, it is necessary to increase the thickness of the electrode wiring, and for this purpose, the thickness of the photoresist during lift-off must also be increased. Conventionally, in order to increase the thickness of the photoresist film, there is a two-layer photoresist process using photoresists having different solubility in a developer.
第１図は、従来の２層フォトレジストパターン形成工程
の断面図である。基板１上に現像液に対して溶解速度が
大きい第１のフォトレジスト２と溶解速度が小さい第２
のフォトレジスト３を順次形成しく＆）、所定のマスク
を用いて露光を行い、現像を行い第１のフォトレジスト
パターン４の開孔部面積が第２のフォトレジストパター
ン６のＲ孔部面積より大きいオーバーハングパターン６
を形成するものである（ｂ）。しかしこの方法では、第
２のフォトレジスト３を形成する時、第１のフォトレジ
スト２と第２のフォトレジスト３が溶解し合い十分なフ
ォトレジスト膜厚が得られないという問題がある。FIG. 1 is a cross-sectional view of a conventional two-layer photoresist pattern forming process. A first photoresist 2 having a high dissolution rate with respect to the developer and a second photoresist having a low dissolution rate are placed on the substrate 1.
The photoresists 3 are sequentially formed (&), exposed using a predetermined mask, and developed so that the opening area of the first photoresist pattern 4 is larger than the R hole area of the second photoresist pattern 6. Large overhang pattern 6
(b). However, this method has a problem in that when forming the second photoresist 3, the first photoresist 2 and the second photoresist 3 dissolve into each other, making it impossible to obtain a sufficient photoresist film thickness.
また、第２図は、従来の２層フォトレジストパターンの
断面図であり、膜厚が大きく微細な薄膜パターンを形成
する場合について示している。フォトレジストパターン
開孔部６において、第１のフォトレジストパターン４が
横に広がり微細なところではパターンくずれ５を起こし
２層フォトレジストパターンの形成が困難であるという
問題があった。Further, FIG. 2 is a cross-sectional view of a conventional two-layer photoresist pattern, and shows the case where a fine thin film pattern with a large film thickness is formed. In the photoresist pattern opening 6, the first photoresist pattern 4 spreads laterally, causing pattern distortion 5 in minute areas, making it difficult to form a two-layer photoresist pattern.
発明の目的
本発明は、これらの問題を解決するためになされたもの
で、膜厚の大きい微細な配線電極パターン形成方法を提
供するものである。OBJECTS OF THE INVENTION The present invention was made to solve these problems, and provides a method for forming a fine wiring electrode pattern with a large thickness.
発明の構成
本発明は、基板上に現像液に対する溶解速度が大きい第
１のフォトレジスト膜を形成し、その後前記フォトレジ
ストを１３０℃〜１６０’Ｃで熱処理し、その後溶解速
度が第１のフォトレジストより小さい第２のフォトレジ
スト膜を形成し５．所定のフォトマスクを用いて露光し
、その後現像液にて現像しオーバーハングパターンを形
成することを特徴とする。このように、第１のフォトレ
ジストを熱処理することによって、第１のフォトレジス
トが硬化され第２のフォトレジスト被膜時の第１のフォ
トレジストと第２のフォトレジストの溶解が少なくなり
、膜厚の大きい２層フォトレジスト膜が得られる。また
、第１のフォトレジストを１３０℃〜１６０℃で熱処理
することによって現像液に対する溶解速度が下がり、さ
らに第１のフォトレジストの露光部と未露光部の溶解速
度の差カ太キ＜なり、第２の７オトレジストパタ一ン開
孔部に対し、第１のフォトレジスト開孔部の広が９を制
御でき、膜厚の大きい微細パターン形成が可能となるの
で膜厚の大きい微細配線電極パターン形成が可能となる
。Structure of the Invention The present invention forms a first photoresist film having a high dissolution rate in a developing solution on a substrate, then heat-treats the photoresist at 130°C to 160'C, and then forms a first photoresist film with a high dissolution rate in a developing solution. 5. forming a second photoresist film smaller than the resist; It is characterized in that it is exposed using a predetermined photomask and then developed with a developer to form an overhang pattern. As described above, by heat-treating the first photoresist, the first photoresist is hardened, and the dissolution of the first photoresist and the second photoresist when coating the second photoresist is reduced, and the film thickness is increased. A two-layer photoresist film with a large . Further, by heat-treating the first photoresist at 130° C. to 160° C., the dissolution rate in the developer is reduced, and furthermore, the difference in the dissolution rate between the exposed and unexposed portions of the first photoresist becomes large. The width 9 of the first photoresist opening can be controlled with respect to the second seven photoresist pattern openings, making it possible to form a fine pattern with a large film thickness. Pattern formation becomes possible.
従来のように第１のフォトレジスト膜形成後１３０″Ｃ
以上の熱処理を行なわない場合、現像時の第１のフォト
レジストの現像液【対する溶解速度が太きく、′−！た
、未露光部と露光部の溶解速度の差が小さく、その結果
オーバーハングパターンひさし幅の制御が難しく、また
１７上ｍ程度の微細パターンの形成は難しかった。しか
し本発明によれば、ひさし幅の制御は容易に行え、１μ
ｍの微細パターンの形成も可能となる。第１のフォトレ
ジスト膜形成後の熱処理を１７０℃以上とすると第１の
フォトレジスト膜は現像液に対して溶解され々くなる。130″C after forming the first photoresist film as before.
If the above heat treatment is not performed, the dissolution rate of the first photoresist in the developer during development will be high, and In addition, the difference in dissolution rate between the unexposed area and the exposed area was small, and as a result, it was difficult to control the width of the overhang pattern eaves, and it was difficult to form a fine pattern of about 17 m. However, according to the present invention, the eaves width can be easily controlled, and
It is also possible to form a fine pattern of m. If the heat treatment after forming the first photoresist film is performed at 170° C. or higher, the first photoresist film will be less likely to be dissolved in the developer.
したがって第１のフォトレジスト膜形成後の熱処理は１
３０〜１６０″Ｃが最も好ましい。Therefore, the heat treatment after forming the first photoresist film is
30-160''C is most preferred.
実施例の説明 本発明の実施例を第３図（＋Ｌ）〜（ｆ）に示す。Description of examples Examples of the present invention are shown in FIGS. 3(+L) to (f).
基板１１上に現像液例えばＭＦ３１２（商品名）に対し
て溶解速度の大きい第１のフォトレジスト１２例えばマ
イクロポジット２３ポジテイブレジスト（商品名）を２
μｍの膜厚で形成する←）ｄその後１４０′Ｃで３０分
間熱処理を行い第１のフォトレジスト１２を硬化させる
（ｂ）。その後、第１のフォトレジスト１２より溶解速
度の小さい第２のフォトレジスト１３例えばＡＺ１４０
０−２７（商品名）を硬化した第１のフォトレジスト１
２Ａ上に１．５μｍの膜厚で形成し、９０″Ｃで１５分
間プリベークする（Ｃ）。その後、所定のマスクを用い
て露光を行い、現像液ＭＦ３１２で現像を行えばオーバ
ーハングレジストパターン１４が得られる（（１＋。A first photoresist 12 such as Microposit 23 and a positive resist (trade name) having a high dissolution rate in a developer such as MF312 (trade name) are placed on the substrate 11.
The first photoresist 12 is formed with a film thickness of μm←)d and then heat treated at 140'C for 30 minutes to harden the first photoresist 12 (b). Thereafter, a second photoresist 13 having a lower dissolution rate than the first photoresist 12, for example AZ140, is applied.
First photoresist 1 cured with 0-27 (trade name)
2A with a thickness of 1.5 μm and prebaking at 90"C for 15 minutes (C). After that, exposure is performed using a prescribed mask and development is performed with developer MF312 to form an overhang resist pattern 14. is obtained ((1+.
次に、所定の電極配線金属１５を全面に１．５μｍ蒸着
形成しく６）、その後、アセトン等の有機溶剤に浸漬し
、硬化した第１のフォトレジスト１２Ａ、第２のフォト
レジスト１３及びフォトレジスト上部の不要金属１５を
除去すれば所望の電極配線・ぐターン１６人が得られる
（ｆ）。Next, a predetermined electrode wiring metal 15 is deposited to a thickness of 1.5 μm on the entire surface 6), and then the first photoresist 12A, the second photoresist 13, and the photoresist are immersed in an organic solvent such as acetone and hardened. By removing the unnecessary metal 15 on the top, the desired electrode wiring pattern 16 can be obtained (f).
本実施例では、パターン幅２μｍ膜厚１．５ ｇ ｍの
ラインアンドスペースパターンの形成を行ったところ膜
厚が大きく、かつパターン幅の小さい・；ターン形成が
可能であった。In this example, when a line and space pattern with a pattern width of 2 μm and a film thickness of 1.5 gm was formed, it was possible to form a turn with a large film thickness and a small pattern width.
第４図は、下層レジストとしてマイクロポジツト２３ポ
ジティブレジストを膜厚２．０μｍ、上層レジストにＡ
Ｚ１４００−２７を膜厚１．５μｍを用いた場合のオー
バハングパターンのオーバーハング部の長さの下層レジ
スト熱処理温度依存性を示すものである。Figure 4 shows a microposit 23 positive resist with a film thickness of 2.0 μm as the lower resist, and an A as the upper resist.
This figure shows the dependence of the length of the overhang part of the overhang pattern on the lower resist heat treatment temperature when using Z1400-27 with a film thickness of 1.5 μm.
なお、熱処理温度を高くするにつれ第１のフォトレジス
ト２の溶解度は小さくな！１１１３０℃〜１６０’Ｃで
あればパターン形成が可能であり、１７０’Ｃ以上では
ほとんど溶解されなくなる。Note that as the heat treatment temperature increases, the solubility of the first photoresist 2 decreases! Pattern formation is possible at 11130°C to 160'C, and almost no melting occurs at 170'C or higher.
発明の効果
本発明（Ｃよれば、微細で、膜厚の大きい２層フメトレ
ジストパターンをオーバーハング形状で形成でき、これ
を用いてリフトオフ法によって微細で膜厚の大きい薄膜
パターンが得られる。Effects of the Invention According to the present invention (C), a fine, thick two-layer fumetresist pattern can be formed in an overhang shape, and a fine, thick thin film pattern can be obtained using the lift-off method.
第１図（ａｌ ｌ （ｔ））、第２図は従来の２層フォ
トレジストパターン形成工程の断面図、第３図（ａ）〜
（ｆ）は本発明の実施例による２層フォトレジストパタ
ーン形成工程の断面図、第４図はオーバーハングパター
ンの熱処理温度依存性を示す図である。
１１・・・・・基板、１２・・・・・第１のフォトレジ
スト、１３・・・第２のフォトレジスト、１４・・・・
・・フォトレジストパターン、１５・・−・金属、１５
Ａ・ 金属パターン。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
第３図
第３図
第４図
黙プ＜ 復温、４司（’Ｃ）Figure 1 (al l (t)), Figure 2 are cross-sectional views of the conventional two-layer photoresist pattern forming process, and Figures 3 (a) -
(f) is a cross-sectional view of the process of forming a two-layer photoresist pattern according to an embodiment of the present invention, and FIG. 4 is a diagram showing the dependence of the overhang pattern on the heat treatment temperature. 11...Substrate, 12...First photoresist, 13...Second photoresist, 14...
...Photoresist pattern, 15...Metal, 15
A. Metal pattern. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 3 Figure 4
Claims (1)
ジスト膜を形成する第１の工程と、前記第１のフォトレ
ジストを１３０℃〜１６０℃で熱処理する第２の工程と
、前記第１のフォトレジストに比べ前記現像液に対する
溶解速度が小さい第２のフォトレジスト膜を形成する第
３の工程と、所定のマスクを用いて露光する第４の工程
と、前記現像液にて現像しフォトレジストパターンを形
成する第５の工程と、前記基板全面に薄膜を形成する第
６の工程と、前記フォトレジストパターン及びフォトレ
ジストパターン上部の薄膜を除去する第７の工程とを有
することを特徴とするパターン形成方法。a first step of forming a first photoresist film having a high dissolution rate in a developer on the substrate; a second step of heat-treating the first photoresist at 130° C. to 160° C.; a third step of forming a second photoresist film that has a lower dissolution rate in the developer than the photoresist; a fourth step of exposing the film to light using a predetermined mask; The method includes a fifth step of forming a resist pattern, a sixth step of forming a thin film on the entire surface of the substrate, and a seventh step of removing the photoresist pattern and the thin film above the photoresist pattern. pattern formation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12791384A JPS616830A (en) | 1984-06-21 | 1984-06-21 | Pattern formation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12791384A JPS616830A (en) | 1984-06-21 | 1984-06-21 | Pattern formation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS616830A true JPS616830A (en) | 1986-01-13 |
Family
ID=14971741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12791384A Pending JPS616830A (en) | 1984-06-21 | 1984-06-21 | Pattern formation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS616830A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0263056A (en) * | 1988-04-05 | 1990-03-02 | Mitsubishi Kasei Corp | Formation of resist pattern |
| US5091288A (en) * | 1989-10-27 | 1992-02-25 | Rockwell International Corporation | Method of forming detector array contact bumps for improved lift off of excess metal |
| JP2005040940A (en) * | 2003-06-13 | 2005-02-17 | Agilent Technol Inc | Wafer bonding method using reactive foils for massively parallel micro-electromechanical systems packaging |
| JP2005539379A (en) * | 2002-09-12 | 2005-12-22 | オリベッティ・アイ−ジェット・ソチエタ・ペル・アツィオーニ | Method for selectively covering a micromachined surface |
| EP1733281A2 (en) * | 2004-04-06 | 2006-12-20 | MacDermid, Incorporated | Method of forming a metal pattern on a substrate |
| CN102446774A (en) * | 2010-10-01 | 2012-05-09 | 住友金属矿山株式会社 | Method of manufacturing a base plate for mounting semiconductor elements |
| CN103560083A (en) * | 2013-11-18 | 2014-02-05 | 电子科技大学 | Stripping process for non-refrigerating infrared FPA detector electrode patterning |
-
1984
- 1984-06-21 JP JP12791384A patent/JPS616830A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0263056A (en) * | 1988-04-05 | 1990-03-02 | Mitsubishi Kasei Corp | Formation of resist pattern |
| US5091288A (en) * | 1989-10-27 | 1992-02-25 | Rockwell International Corporation | Method of forming detector array contact bumps for improved lift off of excess metal |
| JP2005539379A (en) * | 2002-09-12 | 2005-12-22 | オリベッティ・アイ−ジェット・ソチエタ・ペル・アツィオーニ | Method for selectively covering a micromachined surface |
| JP2005040940A (en) * | 2003-06-13 | 2005-02-17 | Agilent Technol Inc | Wafer bonding method using reactive foils for massively parallel micro-electromechanical systems packaging |
| EP1733281A2 (en) * | 2004-04-06 | 2006-12-20 | MacDermid, Incorporated | Method of forming a metal pattern on a substrate |
| EP1733281A4 (en) * | 2004-04-06 | 2010-06-09 | Macdermid Inc | Method of forming a metal pattern on a substrate |
| CN102446774A (en) * | 2010-10-01 | 2012-05-09 | 住友金属矿山株式会社 | Method of manufacturing a base plate for mounting semiconductor elements |
| CN103560083A (en) * | 2013-11-18 | 2014-02-05 | 电子科技大学 | Stripping process for non-refrigerating infrared FPA detector electrode patterning |
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