JPH0518253B2 - - Google Patents
Info
- Publication number
- JPH0518253B2 JPH0518253B2 JP11776884A JP11776884A JPH0518253B2 JP H0518253 B2 JPH0518253 B2 JP H0518253B2 JP 11776884 A JP11776884 A JP 11776884A JP 11776884 A JP11776884 A JP 11776884A JP H0518253 B2 JPH0518253 B2 JP H0518253B2
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- resist
- film
- pattern
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 35
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 description 1
- 229910000423 chromium oxide Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor device.
従来、レジスト膜の残しパターンを形成する場
合、ポジ型レジストでは、選択的露光の後にレジ
スト膜の露光部を現像液で除去する処理を行う。
また、ネガ型のレジストでは、未露光部を現像液
で除去する工程を経てレジスト膜の所定の残しパ
ターンを得る。
Conventionally, when forming a residual pattern of a resist film, in the case of a positive resist, after selective exposure, a process of removing the exposed portion of the resist film with a developer is performed.
In addition, in the case of a negative resist, a predetermined remaining pattern of the resist film is obtained through a step of removing the unexposed portions with a developer.
而して、現像液のレジスト膜の残しパターンに
ポストベークを施して硬化させ、得られたレジス
ト膜をマスクにしてその直下の金属層等のパター
ニングを行つている。 The remaining pattern of the resist film of the developer is then post-baked and cured, and the resulting resist film is used as a mask to pattern the metal layer directly below it.
上述の従来の半導体装置の製造方法では、サブ
ミクロンオーダのレジスト膜の残しパターンを得
るためには、遠紫外線及び電子線に感光するレジ
ストを必要とする。しかしながら、ポジ型レジス
トでは、マスク作成の際にクロム、酸化クロム等
をマスク基板上に残す必要があるが、クロムの残
しは製造上多くの問題を有している。また、クロ
ムを石英等のマスク上に残すため寸法のばらつき
が大きくなる。また、第５図Ａ，Ｂに示す如く、
マスク１１上のクロム層１２が剥れ易い問題があ
る。
In the conventional semiconductor device manufacturing method described above, a resist sensitive to deep ultraviolet rays and electron beams is required in order to obtain a residual pattern of a resist film on the order of submicrons. However, in the case of a positive resist, it is necessary to leave chromium, chromium oxide, etc. on the mask substrate during mask fabrication, but the remaining chromium causes many problems in manufacturing. Furthermore, since chromium is left on a mask made of quartz or the like, dimensional variations become large. In addition, as shown in FIG. 5A and B,
There is a problem that the chromium layer 12 on the mask 11 easily peels off.
一方、ネガ型レジストの場合は、微細パターン
を形成する場合、マスクを通過する光量が大き目
のパターンと異なるため、微細パターンを形成す
るのに必要な露光量を得ると、それ以外の大きい
パターンではオーバ露光になる。また、ネガ型レ
ジストの特徴として露光後の現像時にレジストが
現像液を吸収して膨潤するため、微細パターンの
形成が困難である欠点がある。 On the other hand, in the case of a negative resist, when forming a fine pattern, the amount of light passing through the mask is different from that of a large pattern. Overexposure will result. In addition, a negative resist has the disadvantage that it is difficult to form fine patterns because the resist absorbs a developer and swells during development after exposure.
本発明は、耐ドライエツチングに強い微細レジ
ストパターンを容易に形成することができる半導
体装置の製造方法を提供することをその目的とす
るものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can easily form a fine resist pattern that is resistant to dry etching.
本発明は、遠紫外ポジ型レジストを利用してサ
ブミクロンオーダの穴明けを可能にし、相溶性の
ないレジストを穴に埋込んでレジスト膜のリフト
オフを行うことにより、耐ドライエツチングに強
い微細レジストパターンを容易に形成することが
できる半導体装置の製造方法である。
The present invention makes it possible to drill submicron-order holes using a deep ultraviolet positive resist, and lifts off the resist film by filling the holes with an incompatible resist, thereby creating a fine resist that is resistant to dry etching. This is a method of manufacturing a semiconductor device in which a pattern can be easily formed.
以下、本発明の実施例について図面を参照して
説明する。
Embodiments of the present invention will be described below with reference to the drawings.
先ず、第１図Ａに示す如く、半導体基板１上に
被パターニング層である金属層２を形成し、この
金属層２上に例えばODUR−1014（東京応化社
製、商品名）からなる遠紫外線及び電子線に感光
する樹脂を含んだ第１レジスト膜３（ポジ型レジ
ストの膜）を形成する。次いで、第１レジスト膜
３の所定領域に例えば遠紫外光を選択的に照射
し、露光現像を施してサブミクロンオーダの微細
穴４を開口する。 First, as shown in FIG. 1A, a metal layer 2, which is a layer to be patterned, is formed on a semiconductor substrate 1, and a deep ultraviolet ray made of, for example, ODUR-1014 (manufactured by Tokyo Ohka Co., Ltd., trade name) is formed on this metal layer 2. Then, a first resist film 3 (a positive resist film) containing a resin sensitive to electron beams is formed. Next, a predetermined region of the first resist film 3 is selectively irradiated with, for example, far-ultraviolet light, and exposed and developed to open minute holes 4 on the order of submicrons.
次に、同図Ｂに示す如く、微細穴４内及び第１
レジスト膜３上に例えばOMR−83（東京応化社
製、商品名）からなる第２レジスト膜５（ネガ型
レジストの膜）であつて、第１レジスト膜３と相
溶性のないものを形成する。次いで、第２レジス
ト膜５にプリベークを施し硬化させる。 Next, as shown in FIG.
A second resist film 5 (negative resist film) made of, for example, OMR-83 (manufactured by Tokyo Ohka Co., Ltd., trade name), which is incompatible with the first resist film 3, is formed on the resist film 3. . Next, the second resist film 5 is prebaked and hardened.
次に、同図Ｃに示す如く、第２レジスト膜５を
透過して遠紫外線６を第１レジスト膜３に照射す
る。次いで、第１レジスト膜３を現像して同図Ｄ
に示す如く、その上の第２レジスト膜５と一体に
所謂リフトオフのようにして除去し、微細残しパ
ターン７を得る。 Next, as shown in FIG. 3C, the first resist film 3 is irradiated with deep ultraviolet rays 6 that pass through the second resist film 5. Next, the first resist film 3 is developed and shown in FIG.
As shown in FIG. 3, the second resist film 5 thereon is removed together with the second resist film 5 by a so-called lift-off process to obtain a fine remaining pattern 7.
然る後、同図Ｅに示す如く、微細残しパターン
７をマスクにしてその直下の金属層２を所定の形
状にパターニングして半導体装置を得る。 Thereafter, as shown in Figure E, the metal layer 2 immediately below is patterned into a predetermined shape using the fine remaining pattern 7 as a mask to obtain a semiconductor device.
ここで、微細残パターン７の形状が良好でない
場合は、第２レジスト膜５に紫外線照射を施すの
が望ましい。その理由は、第２レジスト膜５は、
紫外線ネガ型レジストであり、通常第２図に示す
如く、85％の残膜値が適性露光量のため、第３図
に示す如く微細穴４の内壁面に薄膜５ａが付着し
易い。この薄膜５ａを紫外線の照射で硬化させ、
専用の現像液で現像することにより、後のリフト
オフ処理の際に第１レジスト膜３と共に容易に除
去するためである。 Here, if the shape of the fine remaining pattern 7 is not good, it is desirable to irradiate the second resist film 5 with ultraviolet rays. The reason is that the second resist film 5 is
Since this is a negative ultraviolet resist, and as shown in FIG. 2, a residual film value of 85% is the appropriate exposure amount, the thin film 5a tends to adhere to the inner wall surface of the microhole 4 as shown in FIG. This thin film 5a is cured by irradiation with ultraviolet rays,
This is because by developing with a dedicated developer, it can be easily removed together with the first resist film 3 during a subsequent lift-off process.
このように本発明に係る半導体装置の製造方法
によれば、ポジ型の第１レジスト膜３を用いて微
細穴４を容易に形成し、この微細穴４内に遠紫外
線にほとんど感光しない第２レジスト膜５を形成
すると共に、第１、第２のレジスト膜３，５の不
要部分をリフトオフにより容易に除去して耐ドラ
イエツチングに強い微細残しパターン７を高い形
状精度の下に得ることができる。その結果、微細
残りパターン７をマスクにしてその直下の金属層
２を所定形状に容易にパターニングできるもので
ある。 As described above, according to the method of manufacturing a semiconductor device according to the present invention, the microscopic holes 4 are easily formed using the positive type first resist film 3, and the second resist film 4, which is hardly sensitive to deep ultraviolet rays, is formed in the microscopic holes 4. At the same time as forming the resist film 5, unnecessary portions of the first and second resist films 3 and 5 can be easily removed by lift-off, and a fine remaining pattern 7 that is resistant to dry etching can be obtained with high shape accuracy. . As a result, the metal layer 2 immediately below can be easily patterned into a predetermined shape using the fine remaining pattern 7 as a mask.
なお、第１、第２のレジスト膜３，５のリフト
オフ処理が困難な場合には、第４図Ａ乃至同図Ｄ
に示す如く、第１レジスト膜３ａ，３ｂを多層構
造にし、実施例と同様に微細穴４の形成、第２レ
ジスト膜５の形成、及びリフトオフ処理を順次行
ない、微細残しパターン７を得るようにするのが
望ましい。 In addition, if the lift-off process of the first and second resist films 3 and 5 is difficult, the steps shown in FIGS. 4A to 4D
As shown in the figure, the first resist films 3a and 3b are made into a multilayer structure, and similarly to the embodiment, the formation of micro holes 4, the formation of the second resist film 5, and the lift-off treatment are performed in sequence to obtain a micro-remaining pattern 7. It is desirable to do so.
以上説明した如く、本発明に係る半導体装置の
製造方法によれば、耐ドライエツチングに強い微
細レジストパターンを容易に形成できるものであ
る。
As explained above, according to the method of manufacturing a semiconductor device according to the present invention, a fine resist pattern that is resistant to dry etching can be easily formed.
第１図Ａ乃至同図Ｅは、本発明方法を工程順に
示す説明図、第２図は、現像後の残膜率とUVの
露光量との関係を示す説明図、第３図は、第２レ
ジスト膜の薄膜が微細穴内に形成されている状態
を示す断面図、第４図Ａ乃至同図Ｄは、本発明の
他の実施例を工程順に示す説明図、第５図Ａ，Ｂ
は、マスクとクロム層の関係を示す説明図であ
る。
１……半導体基板、２……金属層、３……第１
レジスト膜、４……微細穴、５……第２レジスト
膜、６……遠紫外線、７……微細残しパターン。
1A to 1E are explanatory diagrams showing the method of the present invention in the order of steps, FIG. 2 is an explanatory diagram showing the relationship between the residual film rate after development and the UV exposure amount, and FIG. 4A to 4D are cross-sectional views showing a state in which a thin resist film is formed in a microhole, and FIGS.
FIG. 2 is an explanatory diagram showing the relationship between a mask and a chromium layer. 1... Semiconductor substrate, 2... Metal layer, 3... First
Resist film, 4...Minute hole, 5...Second resist film, 6...Far ultraviolet rays, 7...Minute remaining pattern.
Claims (1)
る樹脂を含むポジ型レジストの第１レジスト膜を
形成する工程と、該１レジスト膜に所定の光を選
択的に照射して露光現象によつて所定の微細穴を
開口する工程と、該微細穴の内部及び前記第１レ
ジスト膜上にこれと相溶性のないネガ型レジスト
の第２レジスト膜を形成する工程と、該第２レジ
スト膜をプリベークして固める工程と、該第２レ
ジスト膜を透過して前記第１レジスト膜に再び所
定の光を照射した後、前記第１レジスト膜及びそ
の上の前記第２レジスト膜の部分を一体的に除去
する工程と、上記微細穴に対応して残留した前記
第２レジスト膜の部分を下地エツチング用のマス
クとして使用する工程と、を具備することを特徴
とする半導体装置の製造方法。1. A step of forming a first resist film of a positive resist containing a resin sensitive to deep ultraviolet rays and electron beams on a semiconductor substrate, and selectively irradiating the first resist film with a predetermined light to cause an exposure phenomenon. a step of opening a predetermined microscopic hole, a step of forming a second resist film of a negative resist incompatible with the first resist film inside the microscopic hole and on the first resist film, and a step of prebaking the second resist film. and solidifying the first resist film, and after passing through the second resist film and irradiating the first resist film with a predetermined light again, the first resist film and the portion of the second resist film thereon are integrated. A method for manufacturing a semiconductor device, comprising the steps of: removing the second resist film; and using a portion of the second resist film remaining corresponding to the microhole as a mask for underlying etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11776884A JPS60262427A (en) | 1984-06-08 | 1984-06-08 | Productioin of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11776884A JPS60262427A (en) | 1984-06-08 | 1984-06-08 | Productioin of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60262427A JPS60262427A (en) | 1985-12-25 |
| JPH0518253B2 true JPH0518253B2 (en) | 1993-03-11 |
Family
ID=14719839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11776884A Granted JPS60262427A (en) | 1984-06-08 | 1984-06-08 | Productioin of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60262427A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2105950A1 (en) * | 2008-03-27 | 2009-09-30 | United Radiant Technology Corp. | Thin film etching method |
-
1984
- 1984-06-08 JP JP11776884A patent/JPS60262427A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60262427A (en) | 1985-12-25 |
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