WO2008035059A3 - Exposure and patterning process for forming multi-layer resist structures - Google Patents

Exposure and patterning process for forming multi-layer resist structures Download PDF

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Publication number
WO2008035059A3
WO2008035059A3 PCT/GB2007/003536 GB2007003536W WO2008035059A3 WO 2008035059 A3 WO2008035059 A3 WO 2008035059A3 GB 2007003536 W GB2007003536 W GB 2007003536W WO 2008035059 A3 WO2008035059 A3 WO 2008035059A3
Authority
WO
WIPO (PCT)
Prior art keywords
resist
layer
exposure
controlled
structures
Prior art date
Application number
PCT/GB2007/003536
Other languages
French (fr)
Other versions
WO2008035059A2 (en
Inventor
Naser Afshar-Hanaee
Original Assignee
Polymer Vision Ltd
Naser Afshar-Hanaee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Polymer Vision Ltd, Naser Afshar-Hanaee filed Critical Polymer Vision Ltd
Publication of WO2008035059A2 publication Critical patent/WO2008035059A2/en
Publication of WO2008035059A3 publication Critical patent/WO2008035059A3/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers

Abstract

A method for forming on a substrate a multi-layer resist structure having a controlled and pre-determined amount of undercut or overcut according to whether a positive or negative tone resist is used. The amount of undercut or overcut is controlled by means of a predetermined level of pre-exposure of each underlying resist layer prior to deposition of the next resist layer and the final patterning of the top resist layer. The multi-layer resist is then developed to remove resist in a controlled manner from each layer according to the degree of exposure of the resist. Using the technique, multi-layer resist structures having very fine sub-micron details may be formed. Multi-layer positive tone resist structures can be employed as a mask and combined with metal deposition and lift-off techniques for fabricating very high resolution metallic features.
PCT/GB2007/003536 2006-09-19 2007-09-19 Exposure and patterning process for forming multi-layer resist structures WO2008035059A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0618425A GB2442030A (en) 2006-09-19 2006-09-19 Resist exposure and patterning process
GB0618425.3 2006-09-19

Publications (2)

Publication Number Publication Date
WO2008035059A2 WO2008035059A2 (en) 2008-03-27
WO2008035059A3 true WO2008035059A3 (en) 2008-07-03

Family

ID=37421237

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2007/003536 WO2008035059A2 (en) 2006-09-19 2007-09-19 Exposure and patterning process for forming multi-layer resist structures

Country Status (2)

Country Link
GB (1) GB2442030A (en)
WO (1) WO2008035059A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112652522B (en) * 2020-07-23 2022-05-03 腾讯科技（深圳）有限公司 Photoresist structure, patterned deposition layer, semiconductor chip and manufacturing method thereof

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3476561A (en) * 1965-08-30 1969-11-04 Ibm Photoetch method
EP0002795A2 (en) * 1977-12-30 1979-07-11 International Business Machines Corporation Process for the fabrication of masks for lithographic processes using a photoresist
JPS6021574A (en) * 1983-07-15 1985-02-02 Fujitsu Ltd Manufacture of semiconductor device
US5120622A (en) * 1990-02-05 1992-06-09 Eastman Kodak Company Lift-off process for patterning dichroic filters
US5432125A (en) * 1992-11-30 1995-07-11 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5693548A (en) * 1994-12-19 1997-12-02 Electronics And Telecommunications Research Institute Method for making T-gate of field effect transistor
JPH10154707A (en) * 1996-09-27 1998-06-09 Hitachi Cable Ltd Manufacture of semiconductor device
EP1120688A1 (en) * 2000-01-28 2001-08-01 Tohoku University Laminate structure and method of manufacturing the same
US6455227B1 (en) * 1999-01-06 2002-09-24 Sony Corporation Multilayer resist structure, and method of manufacturing three-dimensional microstructure with use thereof
US20040131963A1 (en) * 2002-01-25 2004-07-08 Masaru Ohta Two-layer film and method of forming pattern with the same
EP1489460A2 (en) * 2003-06-20 2004-12-22 Fuji Photo Film Co., Ltd. Light-sensitive sheet comprising support, first light-sensitive layer and second light-sensitive layer
US20050277064A1 (en) * 2004-06-14 2005-12-15 Bae Systems Information & Electronic Systems Integration, Inc. Lithographic semiconductor manufacturing using a multi-layered process
US20060134559A1 (en) * 2004-12-21 2006-06-22 Ha Jeong H Method for forming patterns on a semiconductor device
WO2008028458A2 (en) * 2006-09-04 2008-03-13 Forschungszentrum Jülich GmbH Lithography method for producing a feature

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984427A (en) * 1982-11-04 1984-05-16 Matsushita Electric Ind Co Ltd Patterning method
JPS61170738A (en) * 1985-01-25 1986-08-01 Seiko Epson Corp Lift-off process by multi-layered resist
JPS63288020A (en) * 1987-05-20 1988-11-25 Sumitomo Electric Ind Ltd Formation of electrode
JPH02231705A (en) * 1989-03-03 1990-09-13 Nec Corp Developing method
US5091288A (en) * 1989-10-27 1992-02-25 Rockwell International Corporation Method of forming detector array contact bumps for improved lift off of excess metal

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3476561A (en) * 1965-08-30 1969-11-04 Ibm Photoetch method
EP0002795A2 (en) * 1977-12-30 1979-07-11 International Business Machines Corporation Process for the fabrication of masks for lithographic processes using a photoresist
JPS6021574A (en) * 1983-07-15 1985-02-02 Fujitsu Ltd Manufacture of semiconductor device
US5120622A (en) * 1990-02-05 1992-06-09 Eastman Kodak Company Lift-off process for patterning dichroic filters
US5432125A (en) * 1992-11-30 1995-07-11 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5693548A (en) * 1994-12-19 1997-12-02 Electronics And Telecommunications Research Institute Method for making T-gate of field effect transistor
JPH10154707A (en) * 1996-09-27 1998-06-09 Hitachi Cable Ltd Manufacture of semiconductor device
US6455227B1 (en) * 1999-01-06 2002-09-24 Sony Corporation Multilayer resist structure, and method of manufacturing three-dimensional microstructure with use thereof
EP1120688A1 (en) * 2000-01-28 2001-08-01 Tohoku University Laminate structure and method of manufacturing the same
US20040131963A1 (en) * 2002-01-25 2004-07-08 Masaru Ohta Two-layer film and method of forming pattern with the same
EP1489460A2 (en) * 2003-06-20 2004-12-22 Fuji Photo Film Co., Ltd. Light-sensitive sheet comprising support, first light-sensitive layer and second light-sensitive layer
US20050277064A1 (en) * 2004-06-14 2005-12-15 Bae Systems Information & Electronic Systems Integration, Inc. Lithographic semiconductor manufacturing using a multi-layered process
US20060134559A1 (en) * 2004-12-21 2006-06-22 Ha Jeong H Method for forming patterns on a semiconductor device
WO2008028458A2 (en) * 2006-09-04 2008-03-13 Forschungszentrum Jülich GmbH Lithography method for producing a feature

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GRUNDBACHER R ET AL: "Four-layer resist process for asymmetric gate recess", MICROELECTRONIC ENGINEERING, ELSEVIER PUBLISHERS BV., AMSTERDAM, NL, vol. 30, no. 1-4, 1 January 1996 (1996-01-01), pages 317 - 320, XP004597521, ISSN: 0167-9317 *

Also Published As

Publication number Publication date
GB0618425D0 (en) 2006-11-01
GB2442030A (en) 2008-03-26
WO2008035059A2 (en) 2008-03-27

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