TW200733225A - Method for forming fine pattern of semiconductor device - Google Patents

Method for forming fine pattern of semiconductor device

Info

Publication number
TW200733225A
TW200733225A TW096105208A TW96105208A TW200733225A TW 200733225 A TW200733225 A TW 200733225A TW 096105208 A TW096105208 A TW 096105208A TW 96105208 A TW96105208 A TW 96105208A TW 200733225 A TW200733225 A TW 200733225A
Authority
TW
Taiwan
Prior art keywords
hard mask
mask pattern
semiconductor device
forming
pattern
Prior art date
Application number
TW096105208A
Other languages
Chinese (zh)
Other versions
TWI349306B (en
Inventor
Jae-Chang Jung
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200733225A publication Critical patent/TW200733225A/en
Application granted granted Critical
Publication of TWI349306B publication Critical patent/TWI349306B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks

Abstract

A method for forming a fine pattern of a semiconductor device comprises the steps of: forming a first hard mask pattern having a width of W1 and a thickness of T1 over an underlying layer formed over a semiconductor substrate; forming a second hard mask film with a planar type over the resulting structure and planarizing the second hard mask s to expose the first hard mask pattern; removing the first hard mask pattern by a thickness T2 from the top surface (0 < T2 < T1); performing a trimming process on the second hard mask film to form a second hard mask pattern having a slope side wall; performing a second trimming process on the second hard mask pattern to separate the second hard mask pattern from the first hard mask pattern and form a third hard mask pattern having a width of W2; and patterning the underlying layer using the first hard mask pattern and the third hard mask pattern as etching masks.
TW096105208A 2006-02-24 2007-02-13 Method for forming fine pattern of semiconductor device TWI349306B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20060018144 2006-02-24
KR1020060131936A KR100861212B1 (en) 2006-02-24 2006-12-21 Method for forming fine patterns of semiconductor devices

Publications (2)

Publication Number Publication Date
TW200733225A true TW200733225A (en) 2007-09-01
TWI349306B TWI349306B (en) 2011-09-21

Family

ID=38549355

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096105208A TWI349306B (en) 2006-02-24 2007-02-13 Method for forming fine pattern of semiconductor device

Country Status (4)

Country Link
JP (1) JP4901526B2 (en)
KR (1) KR100861212B1 (en)
CN (1) CN100550288C (en)
TW (1) TWI349306B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI512784B (en) * 2009-11-26 2015-12-11 Hynix Semiconductor Inc Method of manufacturing fine patterns of semiconductor device
US11205574B2 (en) 2020-03-05 2021-12-21 Winbond Electronics Corp. Method for forming a semiconductor memory structure
TWI750574B (en) * 2020-01-31 2021-12-21 華邦電子股份有限公司 Semiconductor memory structure and method for forming the same

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7314810B2 (en) * 2006-05-09 2008-01-01 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
KR100763538B1 (en) * 2006-08-29 2007-10-05 삼성전자주식회사 Method of forming mask pattern and method of forming fine pattern using the same in a semiconductor device fabricating
JP4932671B2 (en) * 2007-10-26 2012-05-16 東京エレクトロン株式会社 Etching mask forming method, control program, and program storage medium
KR100932333B1 (en) * 2007-11-29 2009-12-16 주식회사 하이닉스반도체 Hard Mask Pattern of Semiconductor Device and Formation Method
KR101439394B1 (en) 2008-05-02 2014-09-15 삼성전자주식회사 Method for forming fine patterns by double patterning process using acid diffusion
US8461053B2 (en) * 2010-12-17 2013-06-11 Spansion Llc Self-aligned NAND flash select-gate wordlines for spacer double patterning
CN103999191B (en) * 2011-12-15 2016-10-19 英特尔公司 For single exposure-self aligned dual, triple and method of quadruple patterning
US8765612B2 (en) * 2012-09-14 2014-07-01 Nanya Technology Corporation Double patterning process
CN103839781B (en) * 2012-11-21 2016-05-25 中芯国际集成电路制造(上海)有限公司 The formation method of semiconductor fine pattern
KR101882561B1 (en) * 2015-10-02 2018-07-26 삼성에스디아이 주식회사 Cmp slurry composition for organic film and polishing method using the same
US10700072B2 (en) * 2018-10-18 2020-06-30 Applied Materials, Inc. Cap layer for bit line resistance reduction
CN113363217B (en) * 2020-03-04 2024-02-06 华邦电子股份有限公司 Semiconductor memory structure and forming method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54155771A (en) * 1978-05-29 1979-12-08 Nec Corp Pattern forming method
JPS62166520A (en) * 1986-01-20 1987-07-23 Nec Corp Patterning method for fine pattern
JPH02266517A (en) * 1989-04-06 1990-10-31 Rohm Co Ltd Manufacture of semiconductor device
JP3906037B2 (en) * 2001-04-20 2007-04-18 株式会社東芝 Manufacturing method of semiconductor device
KR100694412B1 (en) 2006-02-24 2007-03-12 주식회사 하이닉스반도체 Method for forming fine patterns of semiconductor devices
KR100744683B1 (en) 2006-02-27 2007-08-01 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI512784B (en) * 2009-11-26 2015-12-11 Hynix Semiconductor Inc Method of manufacturing fine patterns of semiconductor device
TWI750574B (en) * 2020-01-31 2021-12-21 華邦電子股份有限公司 Semiconductor memory structure and method for forming the same
US11205574B2 (en) 2020-03-05 2021-12-21 Winbond Electronics Corp. Method for forming a semiconductor memory structure
US11665889B2 (en) 2020-03-05 2023-05-30 Winbond Electronics Corp. Semiconductor memory structure

Also Published As

Publication number Publication date
KR20070088248A (en) 2007-08-29
CN100550288C (en) 2009-10-14
TWI349306B (en) 2011-09-21
CN101026086A (en) 2007-08-29
JP2007227934A (en) 2007-09-06
KR100861212B1 (en) 2008-09-30
JP4901526B2 (en) 2012-03-21

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MM4A Annulment or lapse of patent due to non-payment of fees