CN101026086A - Method for forming fine pattern of semiconductor device - Google Patents
Method for forming fine pattern of semiconductor device Download PDFInfo
- Publication number
- CN101026086A CN101026086A CNA2007100792890A CN200710079289A CN101026086A CN 101026086 A CN101026086 A CN 101026086A CN A2007100792890 A CNA2007100792890 A CN A2007100792890A CN 200710079289 A CN200710079289 A CN 200710079289A CN 101026086 A CN101026086 A CN 101026086A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- mask pattern
- film
- etching
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for forming fine pattern of semiconductor device, including following steps: a step of forming a first hard mask pattern, with a width of W1 and a thickness of T1, on bottom layer formed on substrate; a step of forming a flat second hard mask film on the said structure, and smoothing the same to bare the first hard mask pattern; a step of eliminating the first hard mask pattern for a thickness of T2 (0 <T2 <T1); a step of executing modify-etching procedure on the second hard mask film to form a second hard mask pattern having inclined side wall; a step of executing a second modify-etching procedure on the second hard mask pattern to separate the second hard mask pattern from the first hard mask pattern, and to form a third hard mask pattern with a width of W2; a step of patterning the bottom layer by employing the first hard mask pattern and the third hard mask pattern as etching mask.
Description
Technical field
The present invention relates to make the method for semiconductor device, more particularly, relate to the method that forms hard mask pattern, to obtain meticulous pattern.
Background technology
In order to make more and more littler semiconductor device, it is littler that the size of pattern also becomes.For obtaining meticulous pattern, studied to improve photoresistance and lithographic equipment.
Though in photoetching technique, used KrF (248nm) or ArF (193nm) as exposure light source, also attempted using short wavelength light source, for example F
2(157nm) or EUV (13nm).
Yet, when using such as F
2Or during the new light sources of EUV and so on, need new exposure sources, thereby cause manufacturing cost to increase.In addition, the increase of the numerical aperture that new light sources brought has then reduced focal depth range.
In addition, be difficult to make the semiconductor device of the high integration with fine pattern, this is because be limited to the cause of 0.1 μ m from the resulting pattern resolution of exposure sources of using short wavelength light source.
Summary of the invention
Various embodiment of the present invention aims to provide a kind of method that forms fine pattern on semiconductor device, and this method is included in the dual etching work procedure on two kinds of hard mask films, and every kind of hard mask film has different etching selectivities.
According to embodiments of the invention, the method that forms the fine pattern of semiconductor device may further comprise the steps: on the bottom that is formed on the semiconductor substrate, the formation width is that W1, thickness are first hard mask pattern of T1; On resulting structures, form the second hard mask film of flat type, and with the described second hard mask film planarization, to expose described first hard mask pattern; Described first hard mask pattern is removed the T2 (thickness of 0＜T2＜T1) from end face; On the described second hard mask film, repair the erosion operation, have second hard mask pattern of sloped sidewall with formation; On described second hard mask pattern, carry out second and repair the erosion operation, with separately, and form the 3rd hard mask pattern of width W 2 described second hard mask pattern and described first hard mask pattern; And use described first hard mask pattern and described the 3rd hard mask pattern as etching mask, described bottom is carried out patterning.
In one embodiment, the method for patterning that forms semiconductor device comprises: on the bottom that is formed on the semiconductor substrate, form first hard mask pattern with first width and first thickness.On described first hard mask pattern, form the second hard mask film.Remove the described second hard mask film, at least till described first hard mask pattern exposes.Remove the top of described first hard mask pattern that exposes, make the upper surface of resulting first hard mask pattern be lower than the upper surface of the described second hard mask film.On the described second hard mask film, carry out first and repair the erosion operation, have second hard mask pattern of sloped sidewall with formation.On described second hard mask pattern, carry out second and repair the erosion operation, so that described second hard mask pattern is transformed into the 3rd hard mask pattern with second width, thereby on the exposed portions serve of described bottom, form described first hard mask pattern and described the 3rd hard mask pattern together.Use described first hard mask pattern and described the 3rd hard mask pattern as etching mask, described bottom is carried out patterning.
In another embodiment, comprise forming method of patterning on the substrate: on bottom, form first hard mask pattern, described first structure and described second structure qualification, first space and the part of described bottom is exposed with first structure and second structure.Forming the second hard mask film on described first hard mask pattern and in described first space, described bottom is covered by described first hard mask pattern and the described second hard mask film basically.Remove the described second hard mask film,, make first structure of described first hard mask pattern and second structure expose so that the 3rd structure that is defined in described first space to be provided.Described the 3rd structure of etching, between described first structure and described the 3rd structure, to limit second space, and limit the 3rd space between described second structure and described the 3rd structure, described second space and described the 3rd space all make the part of described bottom expose.The part of exposing by described second space and described the 3rd space of the described bottom of etching.
In another embodiment, this method also comprises: remove described first structure exposed and the top of described second structure, till the height of described first structure and described second structure is lower than the height of described the 3rd structure.Described the 3rd structure of etching, up to described the 3rd thickness of structure with till described first thickness of structure is substantially the same.Described bottom can be the part of described substrate, perhaps can be the one deck that is arranged on the described substrate.
In another embodiment, substrate being formed method of patterning comprises: form first hard mask pattern with first structure and second structure on bottom.Described first structure and described second structure qualification, first space and the part of described substrate is exposed.Forming the second hard mask film on described first hard mask pattern and in described first space, described bottom is covered by described first hard mask pattern and the described second hard mask film basically.Remove the described second hard mask film,, make first structure of described first hard mask pattern and second structure expose so that the 3rd structure that is defined in described first space to be provided.Described the 3rd structure of etching, till described first structure, described second structure and described the 3rd structure qualification went out given pattern, described given pattern exposed the part of described bottom.The described bottom of etching is so that described given design transfer is to described bottom.
In another embodiment, this method also comprises: remove described first structure exposed and the top of described second structure, till the height of described first structure and described second structure is lower than the height of described the 3rd structure.Described the 3rd structure of etching, up to described the 3rd thickness of structure with till described first thickness of structure is substantially the same.
Description of drawings
Fig. 1 a is the cross-sectional view that illustrates according to the method for the fine pattern of the formation semiconductor device of the embodiment of the invention to figure li.
Embodiment
Describe the present invention with reference to the accompanying drawings in detail.
Fig. 1 a is illustrated in the hard mask film 115 of first on the bottom 113, and this bottom 113 is formed on the semiconductor substrate 111.Coating photoresistance film on the structure of gained.
With placing the exposed mask on this photoresistance film to carry out exposure process.Carry out developing procedure again, to form photoresistance pattern 116.Bottom 113 is formed by the material that is used for word line, bit line or metal wire.The first hard mask film 115 is formed by the material that its etching selectivity is different from the etching selectivity of bottom 113.The first hard mask film is formed by the material that is selected from the group that following material constitutes: polysilicon, oxidation film, nitride film, metal and combination thereof.
Fig. 1 b illustrates and uses the photoresistance pattern to come the etching first hard mask film as etching mask, to form the first hard mask pattern 115-1.The width of the first hard mask pattern 115-1 is that W1, thickness are T1.Remove the removing photoresistance pattern then.
In the exposure process that forms the photoresistance pattern, pattern can be designed to have minimum live width and minimum spacing, and increases the overexposure operation of exposure energy and time for exposure, so that the photoresistance film is positioned at the side exposure of the shaded areas of exposed mask.As a result, the minimum feature of resulting photoresistance pattern (W1) behind the developing procedure, be to use conventional lithography equipment can patterning minimum spacing, that is corresponding to the resolution limit of device therefor.
Fig. 1 c illustrates and is formed at the hard mask film 117 of second on the resulting structures.The second hard mask film 117 is formed by the material that its etching selectivity is different from the etching selectivity of the first hard mask film.The second hard mask film can be formed by organic membrane or inoranic membrane.
Can use by the formed organic membrane of spin coating operation.In general, photoresistance film or anti-reflective film can be used as organic membrane.For example, organic membrane is at open No.1984-0003145 of Korean Patent and No.1985-0008565, US5,212,043 (on May 18th, 1993), WO97/33198 (on September 12nd, 1997), WO96/37526 (on November 28th, 1996), US5,750,680 (on Mays 12nd, 1998), US6,051,678 (on April 18th, 2000), GB2,345,286A (on July 5th, 2000), US6,132,926 (on October 17th, 2000), US6,225,020B1 (May 1 calendar year 2001), US6,235,448B1 (May 22 calendar year 2001), and US6,235, describe to some extent among the 447B1 (May 22 calendar year 2001), all these patent documentations are incorporated herein by the degree that is allowed with reform.
Particularly, the photoresistance film comprises the host that is selected from the group that is made of following material: polyvinylphenol class, polycarboxylated styrene class, polynorbornene class, poly-adamantane base class, polyimide, polyacrylate, polymethacrylate, poly-fluorine class and combination thereof.More specifically, the host of photoresistance film comprises the polymer that is selected from the group that is made of following material: ROMA base polymer (the maleic anhydride repetitive that comprises open loop), COMA base polymer (comprising cycloolefin repetitive, maleic anhydride repetitive, methacrylate or acrylic ester repeat units) and mixed type polymer thereof.Anti-reflective film is formed by the resin that is selected from the group that following resin constitutes: anline resin, melamine-derived resin, alkali soluble resins, acrylate, epoxy resin and combination thereof.
Inoranic membrane can comprise oxidation film, nitride film or polysilicon layer.Can be according to being used for using the film/layer of other type as inoranic membrane.
For example, when the first hard mask pattern 115-1 was formed by polysilicon layer, the second hard mask film was organic membrane (a for example photoresistance film).
Make second hard mask film 117 planarizations, till the first hard mask pattern 115-1 exposes, shown in Fig. 1 d.The planarization operation can be undertaken by chemico-mechanical polishing (CMP) method, perhaps adopts etching gas to be undertaken by the method for eat-backing, and described etching gas is selected from the group that is made of following gas: N
2, O
2, Ar, H, Cl and combination thereof.
Fig. 1 e illustrates by the method for eat-backing and removes the first hard mask pattern 115-1 of given thickness (T2), wherein 0＜T2≤1/3T1 from end face.The thickness of the resulting first hard mask pattern 115-1 is T3 (0＜T3＜T1).When method is eat-back in use,, make the height of the hard mask pattern 115-1 that wins be lowered into the height that is lower than the second hard mask film by the engraving method that overuses.
The etching gas that use is selected from the group that following gas constitutes eat-backs operation: CF
4, C1
2, HBr and combination thereof.For example, when the second hard mask film is the organic membrane and the first hard mask film when being polysilicon film, use CF
4As etching gas.
Fig. 1 f illustrates the second hard mask pattern 117-1 with sloped sidewall, its on the resulting structures of Fig. 1 e, carry out first repair the erosion operation obtain.
Carry out first under the following conditions and repair the erosion operation, described condition promptly, the etching selectivity of second hard mask pattern: the etching selectivity of first hard mask pattern=(9～10): 1, this first is repaiied the erosion operation and uses the etching gas be selected from the group that is made of following gas: CF
4, N
2, O
2, Ar, H and combination thereof.In the present embodiment, use comprises O
2, CF
4(concentration ratio is O as main component with Ar
2: CF
4: etching gas Ar=1: (7～10): (25～45)) carries out first and repaiies the erosion operation.
For example, when first hard mask pattern be that the polysilicon layer and the second hard mask film are when being organic membrane (particularly photoresistance film), with the O of 3～4sccm (per minute standard milliliter)
2, 30sccm CF
4Carry out first with the Ar of 130sccm as etching gas and repair the erosion operation.
Carry out first and repair erosion operation (for example, eat-backing operation) with the etching second hard mask film, till bottom exposes.Place the bottom between first hard mask pattern and second hard mask pattern partly to expose.In the present embodiment, because expose by eat-backing operation the side of the second hard mask film, so the corner of the second hard mask film that exposes can be subjected to the influence of etching gas, thereby the side of second hard mask pattern becomes inclination.
Fig. 1 g illustrates by second and repaiies the 3rd hard mask pattern 117-2 that obtains of erosion operation, and its width (W2) is substantially the same with the width of the first hard mask pattern 115-1.
Carry out second under the following conditions and repair the erosion operation, described condition promptly, the etching selectivity of second hard mask pattern: the etching selectivity of first hard mask pattern=(9～10): 1, this second is repaiied the erosion operation and uses the etching gas be selected from the group that is made of following gas: CF
4, N
2, O
2, Ar, H and combination thereof.In the present embodiment, use comprises O
2, CF
4(concentration ratio is O as main component with Ar
2: CF
4: etching gas Ar=1: (40～80): (25～50)) carries out second and repaiies the erosion operation.
For example, when first hard mask pattern be that the polysilicon layer and the second hard mask are when being organic membrane (particularly photoresistance film), with the O of 1～2sccm
2, 80sccm CF
4Carry out second with the Ar of 50sccm as etching gas and repair the erosion operation.
Adjust second and repair the etching period of losing operation, and make the width (W2) of the 3rd hard mask pattern 117-2 substantially the same with the width (W1) of the first hard mask pattern 115-1, and the 3rd hard mask pattern 117-2 forms apart from first hard mask pattern and becomes given distance.The thickness of the 3rd hard mask pattern is T4 (0＜T4＜T3).
Fig. 1 h illustrates by carrying out the resulting bottom pattern of general etching work procedure 113-1 with first hard mask pattern and the 3rd hard mask pattern as etching mask.
Figure li be illustrated in carry out on the resulting structures follow-up matting to remove the first hard mask pattern 115-1 and the 3rd hard mask pattern 117-2 resulting bottom pattern 113-1.
According to embodiments of the invention, have closely spaced the 3rd hard mask pattern by dual etching work procedure (comprise first repair the erosion operation and second repair the erosion operation) be formed between first hard mask pattern.Therefore, when using first hard mask pattern and the 3rd hard mask pattern to come etching bottom as etching mask, can obtain conventional lithography equipment the fine pattern that can't obtain.
In addition, guarantee registration, layout degree, the etching limit of etching work procedure easily, and may reduce the manufacturing cost and the activity time of semiconductor device.
The above embodiment of the present invention is illustrative rather than restrictive.For example, use term " the first hard mask film ", " the second hard mask film ", " first hard mask pattern ", " second hard mask pattern ", " the 3rd hard mask pattern " to describe the foregoing description.Yet they are purposes of property presented for purpose of illustration and using.As skilled in the art to understand, can to use not be that the mask film (or mask pattern) of hard mask film (or hard mask pattern) is implemented in the present invention.Have replacement scheme miscellaneous and equivalents.The present invention is not limited to lithography step as herein described.The present invention also is not limited to the semiconductor device of any particular type.For example, the present invention can be applied in dynamic random access memory (DRAM) or the nonvolatile memory.Consider content disclosed in this invention, other increase, minimizing or modification are conspicuous, and should fall in the scope of claims.
The application requires respectively on February 24th, 2006 and the korean patent application No.10-2006-0018144 of submission on December 21st, 2006 and the priority of No.10-2006-0131936, and its full content is incorporated this paper by reference into.
Claims (21)
1. method of patterning that is used to form semiconductor device, this method comprises:
On the bottom that is formed on the semiconductor substrate, form first hard mask pattern with first width and first thickness;
On described first hard mask pattern, form the second hard mask film;
Remove the described second hard mask film, at least till described first hard mask pattern exposes;
Remove the top of described first hard mask pattern that exposes, make the upper surface of described first hard mask pattern of gained be lower than the upper surface of the described second hard mask film;
On the described second hard mask film, carry out first and repair the erosion operation, have second hard mask pattern of sloped sidewall with formation;
On described second hard mask pattern, carry out second and repair the erosion operation, so that described second hard mask pattern is transformed into the 3rd hard mask pattern with second width, make described first hard mask pattern and described the 3rd hard mask pattern that the part of described bottom is exposed; And
Use described first hard mask pattern and described the 3rd hard mask pattern as etching mask, described bottom is carried out patterning.
2. method according to claim 1, the bottom of wherein said patterning are word line, bit line or metal wire.
3. method according to claim 1, the wherein said first hard mask film comprise select the group that constitutes from following material one: polysilicon, oxidation film, nitride film, metal and combination thereof.
4. method according to claim 1, wherein said first width be used to form pattern lithographic equipment can patterning the limiting resolution size.
5. method according to claim 1, first width of wherein said first hard mask pattern is substantially the same with second width of described the 3rd hard mask pattern.
6. method according to claim 1, the wherein said second hard mask film are that to be different from the material of etching selectivity of the described first hard mask film by its etching selectivity formed.
7. method according to claim 6, the wherein said second hard mask film is organic membrane or inoranic membrane.
8. method according to claim 7, wherein said organic membrane comprises photoresistance film or anti-reflective film, it forms by the spin coating operation.
9. method according to claim 8, wherein said organic membrane is the photoresistance film, the host of described photoresistance film comprise select the group that constitutes from following material one: polyvinylphenol class, polycarboxylated styrene class, polynorbornene class, poly-adamantane base class, polyimide, polyacrylate, polymethacrylate, poly-fluorine class and combination thereof.
10. method according to claim 8, wherein said organic membrane is an anti-reflective film, and described anti-reflective film is that the resin of selecting the group that constitutes from following resin forms: anline resin, melamine-derived resin, alkali soluble resins, acrylate, epoxy resin and combination thereof.
11. method according to claim 7, wherein said inoranic membrane comprises oxidation film, nitride film or polysilicon layer.
12. method according to claim 1, wherein said step of removing first hard mask pattern are to use the etching gas of selecting the group that constitutes from following gas to carry out: CF
4, Cl
2, HBr and combination thereof.
13. method according to claim 1, wherein said first repaiies the erosion operation carries out under the following conditions: the etching selectivity of described second hard mask pattern: the etching selectivity of described first hard mask pattern=(9～10): 1; And
Described first repaiies the erosion operation is to use the etching gas selected the group that constitutes from following gas to carry out: CF
4, N
2, O
2, Ar, H and combination thereof.
14. method according to claim 13, wherein said first repaiies the erosion operation is to use and comprises O
2: CF
4: Ar=1: (7～10): carry out as the etching gas of main component (25～45).
15. method according to claim 1, wherein said second repaiies the erosion operation carries out under the following conditions: the etching selectivity of described second hard mask pattern: the etching selectivity of described first hard mask pattern=(9～10): 1; And
Described second repaiies the erosion operation is to use the etching gas selected the group that constitutes from following gas to carry out: CF
4, N
2, O
2, Ar, H and combination thereof.
16. according to claim 15 described methods, wherein said second repaiies the erosion operation is to use and comprises O
2: CF
4: Ar=1: (40～80): carry out as the etching gas of main component (25～50).
17. one kind forms method of patterning to substrate, this method comprises:
Form first hard mask pattern with first structure and second structure on bottom, the part of described first structure and described second structure qualification, first space and described bottom is exposed;
Forming the second hard mask film on described first hard mask pattern and in described first space, described bottom is covered by described first hard mask pattern and the described second hard mask film basically;
Remove the described second hard mask film,, make first structure of described first hard mask pattern and second structure expose so that the 3rd structure that is defined in described first space to be provided;
Described the 3rd structure of etching, between described first structure and described the 3rd structure, to limit second space, and limit the 3rd space between described second structure and described the 3rd structure, described second space and described the 3rd space all make the part of described bottom expose; And
The part of exposing by described second space and described the 3rd space of the described bottom of etching.
18. method according to claim 17, described method also comprises:
Remove described first structure exposed and the top of described second structure, till the height of described first structure and described second structure is lower than the height of described the 3rd structure;
Described the 3rd structure of etching, up to described the 3rd thickness of structure with till described first thickness of structure is substantially the same;
Wherein said bottom is arranged on the described substrate.
19. method according to claim 17, wherein said bottom are the parts of described substrate.
20. one kind forms method of patterning to substrate, this method comprises:
On bottom, form first hard mask pattern, described first structure and described second structure qualification, first space and the part of described bottom is exposed with first structure and second structure;
Forming the second hard mask film on described first hard mask pattern and in described first space, described bottom is covered by described first hard mask pattern and the described second hard mask film basically;
Remove the described second hard mask film,, make first structure of described first hard mask pattern and second structure expose so that the 3rd structure that is defined in described first space to be provided;
Described the 3rd structure of etching, till described first structure, described second structure and described the 3rd structure qualification went out given pattern, described given pattern exposed the part of described bottom; And
The described bottom of etching is to arrive described bottom with described given design transfer.
21. method according to claim 20, described method also comprises:
Remove described first structure exposed and the top of described second structure, till the height of described first structure and described second structure is lower than the height of described the 3rd structure;
Described the 3rd structure of etching, up to described the 3rd thickness of structure with till described first thickness of structure is substantially the same;
Wherein said bottom is arranged on the described substrate.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060018144 | 2006-02-24 | ||
| KR20060018144 | 2006-02-24 | ||
| KR1020060131936 | 2006-12-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101026086A true CN101026086A (en) | 2007-08-29 |
| CN100550288C CN100550288C (en) | 2009-10-14 |
Family
ID=38549355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100792890A Expired - Fee Related CN100550288C (en) | 2006-02-24 | 2007-02-16 | Form the method for the fine pattern of semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP4901526B2 (en) |
| KR (1) | KR100861212B1 (en) |
| CN (1) | CN100550288C (en) |
| TW (1) | TWI349306B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101447458B (en) * | 2007-11-29 | 2011-01-19 | 海力士半导体有限公司 | Hard mask patterns of a semiconductor device and a method for forming the same |
| US8198183B2 (en) | 2007-10-26 | 2012-06-12 | Tokyo Electron Limited | Forming method of etching mask, control program and program storage medium |
| CN103681255A (en) * | 2012-09-14 | 2014-03-26 | 南亚科技股份有限公司 | Double patterning process |
| CN103839781A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fine patterns on semiconductor |
| CN103999191A (en) * | 2011-12-15 | 2014-08-20 | 英特尔公司 | Methods for single exposure-self-aligned double, triple, and quadruple patterning |
| CN105742163A (en) * | 2010-12-17 | 2016-07-06 | 赛普拉斯半导体公司 | Self-aligned nand flash select-gate wordlines for spacer double patterning |
| CN108138030A (en) * | 2015-10-02 | 2018-06-08 | 三星Sdi株式会社 | For organic film chemical and mechanical grinding paste material composition and use its grinding method |
| CN113363217A (en) * | 2020-03-04 | 2021-09-07 | 华邦电子股份有限公司 | Semiconductor memory structure and forming method thereof |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7314810B2 (en) * | 2006-05-09 | 2008-01-01 | Hynix Semiconductor Inc. | Method for forming fine pattern of semiconductor device |
| KR100763538B1 (en) * | 2006-08-29 | 2007-10-05 | 삼성전자주식회사 | Method of forming mask pattern and method of forming fine pattern using the same in a semiconductor device fabricating |
| KR101439394B1 (en) | 2008-05-02 | 2014-09-15 | 삼성전자주식회사 | Method for forming fine patterns by double patterning process using acid diffusion |
| KR101087835B1 (en) * | 2009-11-26 | 2011-11-30 | 주식회사 하이닉스반도체 | Method for fabricating fine pattern of semiconductor device |
| US10700072B2 (en) * | 2018-10-18 | 2020-06-30 | Applied Materials, Inc. | Cap layer for bit line resistance reduction |
| TWI750574B (en) * | 2020-01-31 | 2021-12-21 | 華邦電子股份有限公司 | Semiconductor memory structure and method for forming the same |
| US11205574B2 (en) | 2020-03-05 | 2021-12-21 | Winbond Electronics Corp. | Method for forming a semiconductor memory structure |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54155771A (en) * | 1978-05-29 | 1979-12-08 | Nec Corp | Pattern forming method |
| JPS62166520A (en) * | 1986-01-20 | 1987-07-23 | Nec Corp | Patterning method for fine pattern |
| JPH02266517A (en) * | 1989-04-06 | 1990-10-31 | Rohm Co Ltd | Manufacture of semiconductor device |
| JP3906037B2 (en) * | 2001-04-20 | 2007-04-18 | 株式会社東芝 | Manufacturing method of semiconductor device |
| KR100694412B1 (en) | 2006-02-24 | 2007-03-12 | 주식회사 하이닉스반도체 | Method for forming fine patterns of semiconductor devices |
| KR100744683B1 (en) | 2006-02-27 | 2007-08-01 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
-
2006
- 2006-12-21 KR KR1020060131936A patent/KR100861212B1/en not_active IP Right Cessation
-
2007
- 2007-02-13 TW TW096105208A patent/TWI349306B/en not_active IP Right Cessation
- 2007-02-16 CN CNB2007100792890A patent/CN100550288C/en not_active Expired - Fee Related
- 2007-02-23 JP JP2007043716A patent/JP4901526B2/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8198183B2 (en) | 2007-10-26 | 2012-06-12 | Tokyo Electron Limited | Forming method of etching mask, control program and program storage medium |
| CN101447458B (en) * | 2007-11-29 | 2011-01-19 | 海力士半导体有限公司 | Hard mask patterns of a semiconductor device and a method for forming the same |
| CN105742163A (en) * | 2010-12-17 | 2016-07-06 | 赛普拉斯半导体公司 | Self-aligned nand flash select-gate wordlines for spacer double patterning |
| CN103999191A (en) * | 2011-12-15 | 2014-08-20 | 英特尔公司 | Methods for single exposure-self-aligned double, triple, and quadruple patterning |
| CN103681255A (en) * | 2012-09-14 | 2014-03-26 | 南亚科技股份有限公司 | Double patterning process |
| CN103681255B (en) * | 2012-09-14 | 2016-04-20 | 南亚科技股份有限公司 | The method of double patterning |
| CN103839781A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fine patterns on semiconductor |
| CN103839781B (en) * | 2012-11-21 | 2016-05-25 | 中芯国际集成电路制造(上海)有限公司 | The formation method of semiconductor fine pattern |
| CN108138030A (en) * | 2015-10-02 | 2018-06-08 | 三星Sdi株式会社 | For organic film chemical and mechanical grinding paste material composition and use its grinding method |
| CN113363217A (en) * | 2020-03-04 | 2021-09-07 | 华邦电子股份有限公司 | Semiconductor memory structure and forming method thereof |
| CN113363217B (en) * | 2020-03-04 | 2024-02-06 | 华邦电子股份有限公司 | Semiconductor memory structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100861212B1 (en) | 2008-09-30 |
| TWI349306B (en) | 2011-09-21 |
| KR20070088248A (en) | 2007-08-29 |
| JP4901526B2 (en) | 2012-03-21 |
| TW200733225A (en) | 2007-09-01 |
| CN100550288C (en) | 2009-10-14 |
| JP2007227934A (en) | 2007-09-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100550288C (en) | Form the method for the fine pattern of semiconductor device | |
| CN100550289C (en) | Form the method for the fine pattern of semiconductor device | |
| CN101145515B (en) | Method for forming a fine pattern of a semiconductor device | |
| US7314810B2 (en) | Method for forming fine pattern of semiconductor device | |
| CN101681812B (en) | Pitch multiplication using self-assembling materials | |
| CN101278233B (en) | Process margin using discrete assist features | |
| CN101490807B (en) | Method using during the formation of a semiconductor device | |
| CN101299408B (en) | Method for forming fine pattern of semiconductor device | |
| CN101533215B (en) | Tools and method for manufacturing integrated circuit mask | |
| CN101207037A (en) | Method for forming a pattern in the same with double exposure technology | |
| JP2001230186A5 (en) | ||
| CN100517562C (en) | Method for forming fine pattern of semiconductor device | |
| CN101145514B (en) | Method of forming fine pattern of semiconductor device | |
| KR100606294B1 (en) | Photomask and exposure method using the same, data creating method | |
| CN100576445C (en) | Form the method for patterning of semiconductor device | |
| CN101750879A (en) | Exposure mask and method for manufacturing semiconductor device using the same | |
| US20100209824A1 (en) | Photomask | |
| JP2008102555A (en) | Photomask and method for manufacturing semiconductor device using the same | |
| CN101446756B (en) | Photo mask and method for manufacturing semiconductor device using same | |
| KR101039136B1 (en) | Fabrication method of semiconductor device for reducing design rule in a core region | |
| CN101424875B (en) | Mask and method for forming a semiconductor device using the same | |
| KR100653991B1 (en) | Exposure system and method for manufacturing active region of the semiconductor memory device by using it | |
| CN101276728A (en) | Method for transferring graphic pattern | |
| US8242021B2 (en) | Method for manufacturing semiconductor device | |
| Bok et al. | 0.31 k1 ArF lithography for 70-nm DRAM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091014 Termination date: 20140216 |