JPS54155771A - Pattern forming method - Google Patents

Pattern forming method

Info

Publication number
JPS54155771A
JPS54155771A JP6466878A JP6466878A JPS54155771A JP S54155771 A JPS54155771 A JP S54155771A JP 6466878 A JP6466878 A JP 6466878A JP 6466878 A JP6466878 A JP 6466878A JP S54155771 A JPS54155771 A JP S54155771A
Authority
JP
Japan
Prior art keywords
layer
pattern
interval
etching
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6466878A
Other languages
Japanese (ja)
Other versions
JPS6326536B2 (en
Inventor
Yoshimasa Kato
Hiroshi Gokan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6466878A priority Critical patent/JPS54155771A/en
Publication of JPS54155771A publication Critical patent/JPS54155771A/en
Publication of JPS6326536B2 publication Critical patent/JPS6326536B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks

Abstract

PURPOSE:To obtain an extremely-fine pattern by forming the 2nd layer for controlling a pattern interval on the 1st layer on the substrate where the pattern is formed and by sequentially etching the 2nd layer and 1st layer after providing a mask pattern. CONSTITUTION:On substrate 1, the 1st layer 2 of (d1) in thickness to be patterned is adhered and on it, the 2nd layer 3 of (d2) for pattern-interval control is bonded by stacking. In this case, the 2nd layer 3 should be made of a material which can be etched by ions faster than the 1st layer 2. Next, resists with an pattern interval of W1 are provided onto layer 3 and upper layer 3 and lower layer 2 are ion-etched in sequence. Consequently, re-sticking matter is deposited on the pattern flank and when etching conditions are represented by (alpha1) and (alpha2), pattern interval W2 after etching is expressed by W2=W1-(alpha1alpha1+alpha2alpha2), so that the pattern interval will be narrowed by alpha2alpha2. Therefore, a fine pattern can be obtained which surpasses the manufacture limit of a exposure mask and is suitable for a LSI.
JP6466878A 1978-05-29 1978-05-29 Pattern forming method Granted JPS54155771A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6466878A JPS54155771A (en) 1978-05-29 1978-05-29 Pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6466878A JPS54155771A (en) 1978-05-29 1978-05-29 Pattern forming method

Publications (2)

Publication Number Publication Date
JPS54155771A true JPS54155771A (en) 1979-12-08
JPS6326536B2 JPS6326536B2 (en) 1988-05-30

Family

ID=13264792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6466878A Granted JPS54155771A (en) 1978-05-29 1978-05-29 Pattern forming method

Country Status (1)

Country Link
JP (1) JPS54155771A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130926A (en) * 1980-03-18 1981-10-14 Nec Corp Forming method of mask pattern
JPS57145377A (en) * 1981-03-03 1982-09-08 Nec Corp Manufacture of schottky barrier type field effect transistor
EP0147322A2 (en) * 1983-12-26 1985-07-03 Fujitsu Limited Method for forming a pattern having a fine gap.
JP2007227934A (en) * 2006-02-24 2007-09-06 Hynix Semiconductor Inc Method for forming fine pattern of semiconductor device and method for forming pattern for substrate
US7745339B2 (en) 2006-02-24 2010-06-29 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US7754591B2 (en) 2006-02-24 2010-07-13 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US20220189772A1 (en) * 2020-12-15 2022-06-16 Applied Materials, Inc. Directional modification of patterning structure to enhance pattern elongation process margin
US11984318B2 (en) * 2020-12-15 2024-05-14 Applied Materials, Inc. Directional modification of patterning structure to enhance pattern elongation process margin

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5324277A (en) * 1976-08-18 1978-03-06 Nec Corp Semiconductor devic e and its production

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5324277A (en) * 1976-08-18 1978-03-06 Nec Corp Semiconductor devic e and its production

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130926A (en) * 1980-03-18 1981-10-14 Nec Corp Forming method of mask pattern
JPS57145377A (en) * 1981-03-03 1982-09-08 Nec Corp Manufacture of schottky barrier type field effect transistor
EP0147322A2 (en) * 1983-12-26 1985-07-03 Fujitsu Limited Method for forming a pattern having a fine gap.
JP2007227934A (en) * 2006-02-24 2007-09-06 Hynix Semiconductor Inc Method for forming fine pattern of semiconductor device and method for forming pattern for substrate
US7745339B2 (en) 2006-02-24 2010-06-29 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US7754591B2 (en) 2006-02-24 2010-07-13 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US20220189772A1 (en) * 2020-12-15 2022-06-16 Applied Materials, Inc. Directional modification of patterning structure to enhance pattern elongation process margin
US11984318B2 (en) * 2020-12-15 2024-05-14 Applied Materials, Inc. Directional modification of patterning structure to enhance pattern elongation process margin

Also Published As

Publication number Publication date
JPS6326536B2 (en) 1988-05-30

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