JPS57145377A - Manufacture of schottky barrier type field effect transistor - Google Patents

Manufacture of schottky barrier type field effect transistor

Info

Publication number
JPS57145377A
JPS57145377A JP3031981A JP3031981A JPS57145377A JP S57145377 A JPS57145377 A JP S57145377A JP 3031981 A JP3031981 A JP 3031981A JP 3031981 A JP3031981 A JP 3031981A JP S57145377 A JPS57145377 A JP S57145377A
Authority
JP
Japan
Prior art keywords
layer
gate electrode
etching
groove
operating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3031981A
Other languages
Japanese (ja)
Inventor
Yoichi Aono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3031981A priority Critical patent/JPS57145377A/en
Publication of JPS57145377A publication Critical patent/JPS57145377A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain an electrode in the order of submicron, by depositing a metal layer, which is to become source and drain electrodes later, on an operating layer constituting the FET, providing a groove reaching the operating layer by etching, and providing a gate electrode therein. CONSTITUTION:The N type GaAs operating layer 31 is epitaxially grown on a semiinsulating GaAs substrate 30. An AuGe alloy layer 32 and an Au layer 33 are layered thereon and alloy treatment is performed to obtain low contact resistance. The layers are used as the source and drain electrodes later on. Then a pattern 34 of a resist film having a specified opening is provided thereon. Ion etching is performed, and the operating layer 31 is exposed in the opening. At this time, by ion milling, an reatached layer 35 of Au is generated, and the size of the opening part 321 is reduced. Then, the reduced opening part 321 is utilized, etching is performed, and the groove whose depth is such that a pinch off voltage to be obtained in provided in the layer 31. The pattern 34 is removed, a gate electrode 361 of Ti/Pt/Au is provided in the groove, and a gate electrode 36 is deposited on the surface.
JP3031981A 1981-03-03 1981-03-03 Manufacture of schottky barrier type field effect transistor Pending JPS57145377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3031981A JPS57145377A (en) 1981-03-03 1981-03-03 Manufacture of schottky barrier type field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3031981A JPS57145377A (en) 1981-03-03 1981-03-03 Manufacture of schottky barrier type field effect transistor

Publications (1)

Publication Number Publication Date
JPS57145377A true JPS57145377A (en) 1982-09-08

Family

ID=12300471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3031981A Pending JPS57145377A (en) 1981-03-03 1981-03-03 Manufacture of schottky barrier type field effect transistor

Country Status (1)

Country Link
JP (1) JPS57145377A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4889827A (en) * 1987-09-23 1989-12-26 Siemens Aktiengesellschaft Method for the manufacture of a MESFET comprising self aligned gate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5382277A (en) * 1976-12-28 1978-07-20 Toshiba Corp Schottky gate field effect transistor
JPS5412573A (en) * 1977-06-29 1979-01-30 Matsushita Electric Ind Co Ltd Junction type field effect transistor and production of the same
JPS54155771A (en) * 1978-05-29 1979-12-08 Nec Corp Pattern forming method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5382277A (en) * 1976-12-28 1978-07-20 Toshiba Corp Schottky gate field effect transistor
JPS5412573A (en) * 1977-06-29 1979-01-30 Matsushita Electric Ind Co Ltd Junction type field effect transistor and production of the same
JPS54155771A (en) * 1978-05-29 1979-12-08 Nec Corp Pattern forming method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4889827A (en) * 1987-09-23 1989-12-26 Siemens Aktiengesellschaft Method for the manufacture of a MESFET comprising self aligned gate

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