JP2007227934A - Method for forming fine pattern of semiconductor device and method for forming pattern for substrate - Google Patents
Method for forming fine pattern of semiconductor device and method for forming pattern for substrate Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 107
- 239000000758 substrate Substances 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000005530 etching Methods 0.000 claims abstract description 72
- 238000009966 trimming Methods 0.000 claims abstract description 23
- 238000001459 lithography Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 26
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 5
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- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 claims description 2
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- 238000004528 spin coating Methods 0.000 claims description 2
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- 150000001875 compounds Chemical class 0.000 claims 1
- 230000007261 regionalization Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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Abstract
Description
本発明は半導体素子の微細パターン形成方法に関し、より詳しくは、微細パターンを形成するため、食刻マスクのハードマスクパターンを形成する方法に関するものである。 The present invention relates to a method for forming a fine pattern of a semiconductor device, and more particularly to a method for forming a hard mask pattern of an etching mask in order to form a fine pattern.
次第に微細化する半導体素子を製造するため、パターンの大きさも次第に小さくなる傾向である。これまで、微細なパターンを得るため、露光装備とそれに対応するレジストを開発する方向で研究が進められてきた。
前記露光工程は、従来２４８ｎｍ波長のＫｒＦまたは１９３ｎｍ波長のＡｒＦ露光源を用いていたが、現在の量産工程においてはＦ２（１５７ｎｍ）またはＥＵＶ（１３ｎｍ）などのように、短波長化光源が適用されている。
In order to manufacture semiconductor elements that are gradually miniaturized, the pattern size tends to gradually decrease. So far, in order to obtain fine patterns, research has been conducted in the direction of developing exposure equipment and corresponding resist.
The exposure process conventionally used a 248 nm wavelength KrF or 193 nm wavelength ArF exposure source, but in the current mass production process, a short wavelength light source such as F 2 (157 nm) or EUV (13 nm) is applied. Has been.
しかし、Ｆ２またはＥＵＶなどの新しい光源を採用する場合は、新しい露光装置が必要になるので、製造コストの面で効率的でないだけでなく、焦点深度の幅が低下するという問題点がある。
さらに、このような短波長光源を用いる露光装備から得られるパターンの解像度は０．１μｍ程度に限定されているため、微細なパターンからなる高集積化の半導体素子を製造することは困難である。
However, when a new light source such as F 2 or EUV is used, a new exposure apparatus is required, which is not only efficient in terms of manufacturing cost but also has a problem that the depth of focus is reduced.
Furthermore, since the resolution of the pattern obtained from the exposure equipment using such a short wavelength light source is limited to about 0.1 μm, it is difficult to manufacture a highly integrated semiconductor element having a fine pattern.
本発明は、新しい装備の開発や、これに伴う工程費用の増加を防止するため、簡単な工程方法を追加することだけで半導体素子の微細パターンを形成することができる方法を提供する。 The present invention provides a method capable of forming a fine pattern of a semiconductor device only by adding a simple process method in order to prevent the development of new equipment and the accompanying increase in process cost.
本発明のパターンの形成方法は、次のような一実施形態を提供する。
半導体基板上に形成された被食刻層の上部に第１幅と第１厚さを有する第１ハードマスクパターンを形成する。前記第１ハードマスクパターン上に第２ハードマスク膜を形成する。前記第１ハードマスク膜が露出するまで第２ハードマスク膜を除去する。第２ハードマスク膜の上部より低くなるよう前記第１ハードマスクパターンの上部を除去する。側面が傾いた第２ハードマスクパターンを形成するため、第２ハードマスク膜に対する１次トリミング食刻工程を行う。第２ハードマスクパターンが第２幅を有する第３ハードマスクパターンに変形されるよう、第２ハードマスクパターンに対する２次トリミング工程を行い、被食刻層の露光領域上に第１及び第３ハードマスクパターンをともに形成する。前記第１及び第３ハードマスクパターンを食刻マスクに用いて前記被食刻層のパターニングを行う。
The pattern forming method of the present invention provides the following embodiment.
A first hard mask pattern having a first width and a first thickness is formed on the etched layer formed on the semiconductor substrate. A second hard mask film is formed on the first hard mask pattern. The second hard mask film is removed until the first hard mask film is exposed. The upper part of the first hard mask pattern is removed so as to be lower than the upper part of the second hard mask film. In order to form a second hard mask pattern having an inclined side surface, a primary trimming etching process is performed on the second hard mask film. A secondary trimming process is performed on the second hard mask pattern so that the second hard mask pattern is transformed into a third hard mask pattern having the second width, and the first and third hard masks are formed on the exposed region of the etched layer. A mask pattern is formed together. The etched layer is patterned using the first and third hard mask patterns as an etching mask.
さらに、本発明の方法は次のような他の一実施形態を提供する。
被食刻層上に第１及び第２構造を有する第１マスクパターンを形成するものの、前記第１及び第２構造は第１間隔を画成し、被食刻層の一部を露光する。第２ハードマスク膜は第１マスクパターンと第１間隔内に形成され、被食刻層は第１マスクパターンと第２ハードマスク膜で覆われる。前記第２ハードマスク膜を除去し、第１間隔内に画成される第３構造を形成し、第１マスクパターンの第１及び第２構造を露出させる。第３構造は、第１及び第３構造の間の第２間隔、並びに第１及び第３構造の間の第３間隔を画成するため食刻される。第２及び第３間隔は、被食刻層の一部分を露出する。第２及び第３間隔により露出した被食刻層の一部は食刻される。
Furthermore, the method of the present invention provides another embodiment as follows.
Although a first mask pattern having first and second structures is formed on the etched layer, the first and second structures define a first interval and expose a portion of the etched layer. The second hard mask film is formed within the first interval with the first mask pattern, and the etched layer is covered with the first mask pattern and the second hard mask film. The second hard mask layer is removed to form a third structure defined within the first interval, and the first and second structures of the first mask pattern are exposed. The third structure is etched to define a second spacing between the first and third structures and a third spacing between the first and third structures. The second and third intervals expose a portion of the etched layer. A portion of the etched layer exposed by the second and third intervals is etched.
この際、本発明は次のようなさらに他の一実施形態をさらに含む。
第１及び第２構造が第３構造より低い高さになるまで、露出した第１及び第２構造の上部一部を除去する。第３構造が第１構造と同じ厚さになるまで第３構造を食刻する。被食刻層は基板の一部分、または基板上に提供される一つの層である。
At this time, the present invention further includes another embodiment as follows.
The exposed upper portions of the first and second structures are removed until the first and second structures have a lower height than the third structure. The third structure is etched until the third structure is the same thickness as the first structure. The etched layer is a portion of the substrate or a layer provided on the substrate.
さらに、本発明の方法は次のようなさらに他の一実施形態を提供する。
被食刻層上に第１及び第２構造を有する第１マスクパターンを形成する。前記第１及び第２構造は第１間隔を画成し、基板の一部を露光する。第２ハードマスク膜は第１マスクパターンと第１間隔内に形成され、被食刻層は第１マスクパターンと第２ハードマスク膜で覆われる。前記第２ハードマスク膜を除去し、第１間隔内に画成される第３構造を形成し、第１マスクパターンの第１及び第２構造を露出させる。第３構造は第１、第２及び第３構造が被食刻層の一部を露出するパターンに画成されるまで食刻される。被食刻層で前記第１、第２及び第３構造のパターンを転写する。
前記方法は、第１及び第２構造が第３構造より低い高さを有するまで露出した第１及び第２構造の上部一部を除去する。第３構造が第１構造と同じ厚さに提供されるまで第３構造は食刻される。
Furthermore, the method of the present invention provides still another embodiment as follows.
A first mask pattern having first and second structures is formed on the etched layer. The first and second structures define a first interval and expose a portion of the substrate. The second hard mask film is formed within the first interval with the first mask pattern, and the etched layer is covered with the first mask pattern and the second hard mask film. The second hard mask layer is removed to form a third structure defined within the first interval, and the first and second structures of the first mask pattern are exposed. The third structure is etched until the first, second, and third structures are defined in a pattern that exposes a portion of the etched layer. The patterns of the first, second and third structures are transferred by the etched layer.
The method removes exposed upper portions of the first and second structures until the first and second structures have a lower height than the third structure. The third structure is etched until the third structure is provided to the same thickness as the first structure.
本発明の方法は食刻選択比が異なる2種類のハードマスク膜に対する二重食刻工程を行い、最小限の離隔間隔を有するハードマスクパターンを形成することができ、これを被食刻層に対するパターニング工程時に食刻マスクに用いることにより、リソグラフィ装備の解像度以上の微細パターンを形成することができる。 The method of the present invention can perform a double etching process on two types of hard mask films having different etching selection ratios to form a hard mask pattern having a minimum separation distance, which can be applied to an etched layer. By using it as an etching mask during the patterning step, it is possible to form a fine pattern having a resolution higher than that of lithography equipment.
本発明は、食刻選択比が異なる２種類のハードマスクに対する二重食刻工程(１次及び２次トリミング食刻工程)を行い、半導体素子の微細パターンを形成する方法を提供する。
以下、図１ａ〜図１ｉを参照しながら本発明の一実施形態を説明するが、この際、本発明の範囲が以下に説明する実施形態に限定されるものではない。
The present invention provides a method for forming a fine pattern of a semiconductor device by performing a double etching process (primary and secondary trimming etching processes) on two types of hard masks having different etching selection ratios.
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 a to 1 i, but the scope of the present invention is not limited to the embodiment described below.
図１ａは、半導体基板１１１上に形成された被食刻層１１３の上部に第１ハードマスク膜１１５を形成する。その上部に感光膜を塗布し、前記感光膜の上側に位置した露光マスクを用いた露光及び現像工程を行い、感光膜パターン１１６を形成する。
前記被食刻層は、ワードライン、ビットラインまたは金属配線である。
前記第１ハードマスク膜は、前記被食刻層と食刻選択比の差を有するポリシリコン、酸化膜、窒化膜、金属またはこれらの組合せで形成する。
In FIG. 1 a, a first
The etched layer is a word line, a bit line, or a metal wiring.
The first hard mask film is formed of polysilicon, an oxide film, a nitride film, a metal having a difference in etching selectivity from the etched layer, or a combination thereof.
図１ｂは、前記感光膜パターン１１６を食刻マスクに用いて前記第１ハードマスク膜をパターニングし、第１（Ｗ１）の幅と第１（Ｔ１）の厚さを有する第１ハードマスクパターン１１５−１を形成する。前記感光膜パターンを除去する段階を含む。
一方、前記フォトレジストパターンを形成するための露光工程において、露光マスクは最小線幅の大きさと最小離隔の間隔（pitch）を有するパターンに形成されており、露光工程は露光マスクの遮光領域に位置する感光膜の側面まで露光されるよう、露光エネルギー及び露光時間を増加させる過渡な露光工程で行われる。その結果、現像工程後に得られた感光膜パターンの線幅の大きさは、現在リソグラフィ装備から得られる最小限の大きさ、好ましくは最小の大きさより最大１／２倍程度小さい線幅を有する。従って、前記第１ハードマスクパターンの幅（Ｗ１）は、リソグラフィ装備から得られる最小限のパターン線幅値を有する。
FIG. 1B illustrates a first
On the other hand, in the exposure process for forming the photoresist pattern, the exposure mask is formed into a pattern having a minimum line width and a minimum pitch, and the exposure process is positioned in a light shielding region of the exposure mask. It is performed in a transient exposure process that increases exposure energy and exposure time so that the side surface of the photosensitive film to be exposed is exposed. As a result, the line width of the photosensitive film pattern obtained after the development process has a minimum line width that is currently obtained from the lithography equipment, preferably about 1/2 times smaller than the minimum line width. Accordingly, the width (W1) of the first hard mask pattern has a minimum pattern line width value obtained from the lithography equipment.
図１ｃは、前記結果物の全面に第２ ハードマスク膜１１７が形成された構造を示す図である。
前記第２ハードマスク膜は、前記第１ハードマスク膜と食刻選択比の差が大きい有機膜または無機膜で形成する。
より具体的に、前記有機膜はスピンコーティングの方法で形成可能な有機膜であれば特に限定はしていないが、通常感光膜または反射防止膜などを用いることができる。例えば、大韓民国特許公開番号第１９８４−０００３１４５号、大韓民国特許公開番号 第１９８５−０００８５６５号、ＵＳ ５，２１２，０４３（１９９３．５．１８）、ＷＯ９７／３３１９８（１９９７．９．１２）、ＷＯ ９６／３７５２６ （１９９６．１１．２８）、ＵＳ ５，７５０，６８０（１９９８．５．１２）、ＵＳ ６，０５１，６７８（２０００．４．１８）、ＧＢ２，３４５，２８６ Ａ（２０００．７．５）、ＵＳ６，１３２，９２６（２０００．１０．１７）、ＵＳ ６，２２５，０２０ Ｂ１（２００１．５．１）、ＵＳ ６，２３５，４４８ Ｂ１（２００１．５．２２）及びＵＳ ６，２３５，４４７ Ｂ１（２００１．５．２２）などに開示されたポリビニルフェノール系、ポリヒドロキシスチレン系、ポリノルボルネン系、ポリアダマンチル系、ポリイミド系、ポリアクリレート系、ポリメタアクリレート系及びポリフルオリン系の中から選ばれた一つ以上をベース樹脂として含む感光剤等を用いることができ、さらにフェニルアミン系樹脂、メラミン誘導体系樹脂、アルカリ可溶性系樹脂、アクリレート系樹脂及びエポキシ系樹脂でなる群から選ばれた反射防止膜などを用いることができる。
FIG. 1c is a view showing a structure in which a second
The second hard mask film is formed of an organic film or an inorganic film having a large difference in etching selectivity from the first hard mask film.
More specifically, the organic film is not particularly limited as long as it is an organic film that can be formed by a spin coating method, but a photosensitive film or an antireflection film can be usually used. For example, Korea Patent Publication No. 1984-0003145, Korea Patent Publication No. 1985-0008565, US 5,212,043 (1993.5.18), WO 97/33198 (1997.9.12), WO 96 / 37526 (1996.11.28), US 5,750,680 (1998.5.12), US 6,051,678 (2000.4.18), GB 2,345,286 A (2000.7.5) US 6,132,926 (2000.10.17), US 6,225,020 B1 (2001.5.1), US 6,235,448 B1 (2001.5.22) and US 6,235,447. Polyvinylphenol type, polyhydroxystyrene type, polynorbornene disclosed in B1 (2001.5.22), etc. A photosensitizer containing one or more selected from the group consisting of polyamines, polyadamantyl, polyimides, polyacrylates, polymethacrylates and polyfluorines, as well as phenylamine resins, An antireflection film selected from the group consisting of melamine derivative resins, alkali-soluble resins, acrylate resins, and epoxy resins can be used.
さらに、前記無機膜は前記第１ハードマスク膜と食刻選択比の差を有する酸化膜、窒化膜またはポリシリコン層を用いる。
例えば、第１ハードマスクパターンをポリシリコン層で形成する場合、第２ハードマスク膜は有機膜、特に感光膜を用いて形成するのが好ましい。
図１ｄは、第１ハードマスクパターン１１５−１が露出するまで前記第２ハードマスク膜１１７に対する平坦化食刻工程を行い、プラナー（planar）形態の第２ハードマスク膜１１７が形成された構造を示す図である。
前記平坦化食刻工程は、ＣＭＰ工程または窒素、酸素、アルゴン、水素、塩素及びこれらの組合せでなる群から選ばれた一つ以上の食刻ガスを用いたエッチバック工程で行う。
Further, the inorganic film is an oxide film, a nitride film or a polysilicon layer having a difference in etching selectivity from the first hard mask film.
For example, when the first hard mask pattern is formed of a polysilicon layer, the second hard mask film is preferably formed using an organic film, particularly a photosensitive film.
FIG. 1d shows a structure in which a planar
The planarization etching process is performed by a CMP process or an etch-back process using one or more etching gases selected from the group consisting of nitrogen, oxygen, argon, hydrogen, chlorine, and combinations thereof.
図１ｅは、前記結果物の全面に対するエッチバック食刻工程を行い、第２ハードマスク膜の表面から前記第１ハードマスクパターンの上部を所定厚さ（Ｔ２）まで除去した工程の断面図である。この際、前記Ｔ２は０＜Ｔ２≦１／３Ｔ１の値を有する。得られた第１ハードマスクパターンはＴ３の厚さを有する（０＜Ｔ３＜Ｔ１）。即ち、第１ハードマスクパターンの高さは、前記エッチバックの工程時にオーバーエッチングし、第２ハードマスク膜より低く形成する。 FIG. 1E is a cross-sectional view illustrating a process of performing an etch-back etching process on the entire surface of the resultant product, and removing the upper portion of the first hard mask pattern from the surface of the second hard mask film to a predetermined thickness (T2). . At this time, T2 has a value of 0 <T2 ≦ 1 / 3T1. The obtained first hard mask pattern has a thickness of T3 (0 <T3 <T1). That is, the height of the first hard mask pattern is over-etched during the etch back process, and is formed lower than the second hard mask film.
前記エッチバック食刻工程は、ＣＦ４、Ｃｌ２、ＨＢｒ及びこれらの組合せでなる群から選ばれた食刻ガスを用いて行われるが、例えば前記第２ハードマスク膜が有機膜であり、第１ハードマスク膜がポリシリコン膜の場合、ＣＦ４ガスを食刻ガスに用いることができる。 The etch-back etching process is performed using an etching gas selected from the group consisting of CF 4 , Cl 2 , HBr, and combinations thereof. For example, the second hard mask film is an organic film, When the hard mask film is a polysilicon film, CF 4 gas can be used as the etching gas.
図１ｆは、前記図１ｅの結果物に対する１次トリミング食刻工程により傾いた側面を有する第２ハードマスクパターン１１７−１が形成された工程断面図である。
前記１次トリミング食刻工程は、第２ハードマスクパターン:第１ハードマスクパターンの食刻速度が９〜１０：１になるよう、四フッ化炭素（ＣＦ４）、窒素（Ｎ2）、酸素（Ｏ２）、アルゴン（Ａｒ）、水素及びこれらの組合せでなる群から選ばれた食刻ガスを用いる。好ましくは、前記１次トリミング食刻工程における食刻ガスは、酸素、四フッ化炭素及びアルゴンガスを主成分として含み、酸素:四フッ化炭素:アルゴンの混合濃度比は１：７〜１０：２５〜４５であるのが好ましい。
FIG. 1f is a process cross-sectional view in which a second hard mask pattern 117-1 having a side surface inclined by a primary trimming etching process is formed on the resultant structure of FIG. 1e.
In the first trimming etching process, carbon tetrafluoride (CF 4 ), nitrogen (N 2), oxygen (oxygen) is used so that the etching speed of the second hard mask pattern: the first hard mask pattern is 9 to 10: 1. An etching gas selected from the group consisting of O 2 ), argon (Ar), hydrogen, and combinations thereof is used. Preferably, the etching gas in the primary trimming etching process includes oxygen, carbon tetrafluoride, and argon gas as main components, and the mixed concentration ratio of oxygen: carbon tetrafluoride: argon is 1: 7-10: It is preferable that it is 25-45.
例えば、第１ハードマスクパターンがポリシリコン層からなっており、第２ハードマスク膜が有機膜、特に感光膜からなっている場合、前記１次トリミング食刻工程はＯ２３〜４ｓｃｃｍ、ＣＦ４ ３０ｓｃｃｍ及びＡｒ １３０ｓｃｃｍ条件下で行われる。
さらに、前記１次トリミング食刻工程は、被食刻層が露出するまで第２ハードマスク膜を食刻する。その結果、第１ハードマスクパターン及び第２ハードマスクパターンの間に被食刻層が露出する。この際、以前の前記エッチバック食刻工程により第２ハードマスク膜の側面が露出した状態なので、露出した第２ハードマスク膜の角部分が食刻ガスの影響をより大きく受け、傾いたパターン形態に形成される。
For example, when the first hard mask pattern is formed of a polysilicon layer and the second hard mask film is formed of an organic film, particularly a photosensitive film, the primary trimming etching process includes O 2 3 to 4 sccm, CF 4. It is performed under the conditions of 30 sccm and Ar 130 sccm.
Further, in the primary trimming etching process, the second hard mask film is etched until the etched layer is exposed. As a result, the etched layer is exposed between the first hard mask pattern and the second hard mask pattern. At this time, since the side surface of the second hard mask film is exposed by the previous etch-back etching process, the exposed corner portions of the second hard mask film are more greatly affected by the etching gas, and the inclined pattern form is formed. Formed.
図１ｇは、前記結果物に対し第１ハードマスクパターンと同一の幅（Ｗ２）を有する第３ハードマスクパターン１１７−２が形成されるまで、第２ハードマスクパターンに対して２次トリミング食刻工程を行った工程断面図である。
前記２次トリミング食刻の条件は、第２ハードマスクパターン:第１ハードマスクパターンの食刻速度が９〜１０：１の条件になるよう、四フッ化炭素、窒素、酸素、アルゴン、水素及びこれらの組合せでなる群から選ばれた一つ以上の食刻ガスを用いて行う。好ましくは、前記２次トリミング食刻工程の食刻ガスは酸素、四フッ化炭素及びアルゴンガスを主成分として含み、酸素:四フッ化炭素:アルゴンの混合濃度比は１：４０〜８０：２５〜５０であるのが好ましい。
FIG. 1g shows a second trimming etch for the second hard mask pattern until a third hard mask pattern 117-2 having the same width (W2) as the first hard mask pattern is formed. It is process sectional drawing which performed the process.
The secondary trimming etching conditions are as follows: second hard mask pattern: carbon tetrafluoride, nitrogen, oxygen, argon, hydrogen and the like so that the etching speed of the first hard mask pattern is 9-10: 1. One or more etching gases selected from the group consisting of these combinations are used. Preferably, the etching gas of the secondary trimming etching process includes oxygen, carbon tetrafluoride, and argon gas as main components, and a mixed concentration ratio of oxygen: carbon tetrafluoride: argon is 1: 40-80: 25. It is preferably ~ 50.
例えば、第１ハードマスクパターンがポリシリコン層からなっており、第２ハードマスク膜が有機膜、特に感光膜からなっている場合、前記２次トリミング食刻工程はＯ２ １〜２ｓｃｃｍ、ＣＦ４８０ｓｃｃｍ及びＡｒ ５０ｓｃｃｍの条件下で行われる。
前記２次トリミング食刻工程を行う間に食刻時間を適切に調整し、第１ハードマスクパターン幅（Ｗ１）と同一の幅（Ｗ２）を有しながら、第１ハードマスクパターンと所定距離に離隔されている第３ハードマスクパターン１１７−２を得た。この際、第３ハードマスクパターンはＴ４の厚さを有する（０＜Ｔ４＜Ｔ３）。
For example, when the first hard mask pattern is made of a polysilicon layer and the second hard mask film is made of an organic film, particularly a photosensitive film, the second trimming etching process is O 2 1-2 sccm, CF 4. It is performed under the conditions of 80 sccm and Ar 50 sccm.
The etching time is appropriately adjusted during the secondary trimming etching process, and has the same width (W2) as the first hard mask pattern width (W1), while keeping a predetermined distance from the first hard mask pattern. A third hard mask pattern 117-2 that was separated was obtained. At this time, the third hard mask pattern has a thickness of T4 (0 <T4 <T3).
図１ｈは、前記形成された第１及び第３ハードマスクパターンを食刻マスクに通常の食刻工程で前記被食刻層をパターニングして得られた構造を示している。 FIG. 1h shows a structure obtained by patterning the etched layer using the formed first and third hard mask patterns as an etching mask in a normal etching process.
図１ｉは、前記結果物に対する後続の洗浄工程を行い、前記第１ハードマスクパターン１１５−１及び第３ハードマスクパターン１１７−２が除去された被食刻層パターン113-1を示している。
前述したように、本発明は１次トリミング食刻工程及び２次トリミング食刻工程のような簡単な２つの段階の食刻工程を行うことだけで、第１ハードマスクパターンの間に現在リソグラフィ装備から得られるパターンの離隔間隔よりさらに小さいパターンの離隔間隔を有するもう一つの第３ハードマスクパターンを形成することができる。従って、第１ハードマスクパターンと第１ハードマスクパターンの間に形成された第３ハードマスクパターンを食刻マスクに用いて被食刻層を食刻する場合、現在リソグラフィ装備の解像度から得ることのできない最小限のパターン線幅とパターン離隔間隔を有する微細パターンを形成することができる。
さらに、本発明の方法によって食刻工程のための重畳度、整列度及び食刻マージンの確保が容易であり、半導体素子の製造コスト及び工程時間などを縮小することができる。
FIG. 1 i shows an etched layer pattern 113-1 in which the first hard mask pattern 115-1 and the third hard mask pattern 117-2 are removed by performing a subsequent cleaning process on the resultant product.
As described above, the present invention provides a lithographic apparatus between the first hard mask pattern by performing a simple two-step etching process such as a primary trimming etching process and a secondary trimming etching process. Thus, another third hard mask pattern having a pattern separation interval smaller than the pattern separation interval obtained from (1) can be formed. Therefore, when the etching layer is etched using the third hard mask pattern formed between the first hard mask pattern and the first hard mask pattern as an etching mask, it can be obtained from the resolution of the current lithography equipment. A fine pattern having the smallest possible pattern line width and pattern separation interval can be formed.
Furthermore, the method of the present invention makes it easy to ensure the degree of superimposition, alignment, and etching margin for the etching process, and reduce the manufacturing cost and process time of the semiconductor device.
なお、本発明について、好ましい実施の形態を基に説明したが、これらの実施の形態は、例を示すことを目的として開示したものであり、当業者であれば、本発明に係る技術思想の範囲内で、多様な改良、変更、付加等が可能である。このような改良、変更等も、特許請求の範囲に記載した本発明の技術的範囲に属することは言うまでもない。 Although the present invention has been described based on preferred embodiments, these embodiments are disclosed for the purpose of illustrating examples, and those skilled in the art will be able to understand the technical idea of the present invention. Various improvements, changes, additions, and the like are possible within the scope. It goes without saying that such improvements and changes belong to the technical scope of the present invention described in the claims.
１１１ 半導体基板
１１３ 被食刻層
１１３−１ 被食刻層パターン
１１５ 第１ハードマスク膜
１１５−１ 第１ハードマスクパターン
１１６ フォトレジストパターン
１１７ 第２ハードマスク膜
１１７−１ 第２ハードマスクパターン
１１７−２ 第３ハードマスクパターン
Ｗ１ 第１ハードマスクパターンの線幅
Ｗ２ 第２ハードマスクパターンの線幅
Ｔ１ 第１ハードマスクパターンの厚さ
Ｔ２ 第１ハードマスクパターンの除去厚さ
Ｔ３ 食刻工程後得られた第１ハードマスクパターンの厚さ
Ｔ４ 第３ハードマスクパターンの厚さ
Claims (21)
第１ハードマスクパターン上に第２ハードマスク膜を形成する段階と、
第１ハードマスクパターンが露出するまで、第２ハードマスク膜を除去する段階と、
露出した第１ハードマスクパターン上部の一部分を除去し、第２ハードマスクパターンの上部表面より第１ハードマスクパターンの上部表面を低く形成する段階と、
前記結果物に対する１次トリミング食刻工程を行い、傾いた側面を有する第２ハードマスクパターンを形成する段階と、
前記第２ハードマスクパターンに対する２次トリミング食刻工程を行い、第２ハードマスクパターンを第２幅を有する第３ハードマスクパターンに変換させ、前記第１及び第３ハードマスクパターンにより被食刻層の一部分を同時に露出させる段階と、
前記第１及び第２ハードマスクパターンを食刻マスクに用い、前記被食刻層をパターニングする段階と、
を含むことを特徴とする半導体素子の微細パターン形成方法。 Forming a first hard mask pattern having a first width and a first thickness on an etched layer formed on a semiconductor substrate;
Forming a second hard mask film on the first hard mask pattern;
Removing the second hard mask film until the first hard mask pattern is exposed;
Removing a portion of the exposed upper portion of the first hard mask pattern and forming an upper surface of the first hard mask pattern lower than an upper surface of the second hard mask pattern;
Performing a first trimming etching process on the resultant to form a second hard mask pattern having inclined side surfaces;
A secondary trimming etching process is performed on the second hard mask pattern, the second hard mask pattern is converted into a third hard mask pattern having a second width, and the etched layer is formed by the first and third hard mask patterns. Simultaneously exposing a portion of
Patterning the etched layer using the first and second hard mask patterns as an etching mask;
A method for forming a fine pattern of a semiconductor device, comprising:
四フッ化炭素（ＣＦ４）、窒素（Ｎ２)、酸素（Ｏ２)、アルゴン（Ａｒ)、水素及びこれらの組合せでなる群から選ばれた食刻ガスで行われることを特徴とする請求項１に記載の半導体素子の微細パターン形成方法。 The primary trimming etching step is performed under a condition that the etching speed of the second hard mask pattern: first hard mask pattern is 9 to 10: 1.
The etching is performed with an etching gas selected from the group consisting of carbon tetrafluoride (CF 4 ), nitrogen (N 2 ), oxygen (O 2 ), argon (Ar), hydrogen, and combinations thereof. Item 12. A method for forming a fine pattern of a semiconductor element according to Item 1.
四フッ化炭素（ＣＦ４）、窒素（Ｎ２）、酸素（Ｏ２）、アルゴン（Ａｒ）、水素及びこれらの組合せでなる群から選ばれた食刻ガスで行われることを特徴とする請求項１に記載の半導体素子の微細パターン形成方法。 The secondary trimming etching conditions are as follows: the second hard mask pattern: the etching speed of the first hard mask pattern is 9 to 10: 1.
The etching is performed using an etching gas selected from the group consisting of carbon tetrafluoride (CF 4 ), nitrogen (N 2 ), oxygen (O 2 ), argon (Ar), hydrogen, and combinations thereof. Item 12. A method for forming a fine pattern of a semiconductor element according to Item 1.
第１ハードマスクパターンの上部及び第１間隔内に第２ハードマスク膜を形成するものの、被食刻層は第１ハードマスクパターン及び第２ハードマスク膜により覆われており、
第２ハードマスク膜を除去して第１間隔内に画成された第３構造を提供するものの、第１ハードマスクパターンの第１及び第２構造は露出しており、
第３構造を食刻して第１構造と第３構造との間の第２間隔と、第２構造と第３構造との間の第３間隔を画成するものの、第２間隔及び第３間隔は被食刻層の一部をそれぞれ露出し、
第２間隔及び第３間隔により露出した被食刻層の一部を食刻する段階を含むことを特徴とする基板用パターン形成方法。 A first hard mask pattern having first and second structures is formed on the etched layer, but the first and second structures define a first interval and expose a part of the etched layer. And
Although the second hard mask film is formed on the first hard mask pattern and within the first interval, the etched layer is covered with the first hard mask pattern and the second hard mask film,
The second hard mask film is removed to provide a third structure defined within the first interval, but the first and second structures of the first hard mask pattern are exposed,
Although the third structure is etched to define a second distance between the first structure and the third structure and a third distance between the second structure and the third structure, the second distance and the third distance The interval exposes part of the etched layer,
A pattern forming method for a substrate, comprising: etching a part of an etching layer exposed by the second interval and the third interval.
このとき第３構造は第１構造と同一の厚さに提供されるまで食刻され、
前記被食刻層は基板上に提供される段階をさらに含むことを特徴とする請求項１７に記載の基板用パターン形成方法。 While the method removes the upper portions of the first and second structures exposed until the first and second structures have a lower height than the third structure,
The third structure is then etched until it is provided to the same thickness as the first structure,
The method of claim 17, further comprising providing the etched layer on the substrate.
第１ハードマスクパターンの上部及び第１間隔内に第２ハードマスク膜を形成するものの、被食刻層は第１ハードマスクパターン及び第２ハードマスク膜により覆われており、
第２ハードマスク膜を除去して第１間隔内に画成された第３構造を提供するものの、第１ハードマスクパターンの第１及び第２構造は露出しており、
第１、第２及び第３構造が被食刻層の一部を露出する所定パターンを画成するまで第３構造を食刻し、
所定のパターンが被食刻層に転写されるよう被食刻層を食刻する段階を含むことを特徴とする基板用パターン形成方法。 A first hard mask pattern having first and second structures is formed on the etched layer, but the first and second structures define a first interval and expose a part of the etched layer. And
Although the second hard mask film is formed on the first hard mask pattern and within the first interval, the etched layer is covered with the first hard mask pattern and the second hard mask film,
The second hard mask film is removed to provide a third structure defined within the first interval, but the first and second structures of the first hard mask pattern are exposed,
Etching the third structure until the first, second and third structures define a predetermined pattern exposing a portion of the etched layer;
A pattern forming method for a substrate, comprising: etching an etching layer so that a predetermined pattern is transferred to the etching layer.
このとき第３構造は第１構造と同一の厚さに提供されるまで食刻され、
前記被食刻層は基板上に提供される段階をさらに含むことを特徴とする請求項２０に記載の基板用パターン形成方法。 While the method removes the upper portions of the first and second structures exposed until the first and second structures have a lower height than the third structure,
The third structure is then etched until it is provided to the same thickness as the first structure,
21. The method of claim 20, further comprising providing the etched layer on the substrate.
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| JP2007305976A (en) * | 2006-05-09 | 2007-11-22 | Hynix Semiconductor Inc | Method of forming fine pattern in semiconductor device |
| JP2008060517A (en) * | 2006-08-29 | 2008-03-13 | Samsung Electronics Co Ltd | Method of forming mask structure and method of forming fine pattern using the same |
| WO2009054131A1 (en) * | 2007-10-26 | 2009-04-30 | Tokyo Electron Limited | Forming method of etching mask, control program and program storage medium |
| JP2009272623A (en) * | 2008-05-02 | 2009-11-19 | Samsung Electronics Co Ltd | Method for forming fine pattern of semiconductor device by means of double patterning process utilizing acid diffusion |
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| KR100932333B1 (en) * | 2007-11-29 | 2009-12-16 | 주식회사 하이닉스반도체 | Hard Mask Pattern of Semiconductor Device and Formation Method |
| KR101087835B1 (en) * | 2009-11-26 | 2011-11-30 | 주식회사 하이닉스반도체 | Method for fabricating fine pattern of semiconductor device |
| US8461053B2 (en) * | 2010-12-17 | 2013-06-11 | Spansion Llc | Self-aligned NAND flash select-gate wordlines for spacer double patterning |
| KR101624814B1 (en) | 2011-12-15 | 2016-05-26 | 인텔 코포레이션 | Methods for single exposure-self-aligned double, triple, and quadruple patterning |
| US8765612B2 (en) * | 2012-09-14 | 2014-07-01 | Nanya Technology Corporation | Double patterning process |
| CN103839781B (en) * | 2012-11-21 | 2016-05-25 | 中芯国际集成电路制造(上海)有限公司 | The formation method of semiconductor fine pattern |
| KR101882561B1 (en) * | 2015-10-02 | 2018-07-26 | 삼성에스디아이 주식회사 | Cmp slurry composition for organic film and polishing method using the same |
| US10700072B2 (en) * | 2018-10-18 | 2020-06-30 | Applied Materials, Inc. | Cap layer for bit line resistance reduction |
| TWI750574B (en) * | 2020-01-31 | 2021-12-21 | 華邦電子股份有限公司 | Semiconductor memory structure and method for forming the same |
| CN113363217B (en) * | 2020-03-04 | 2024-02-06 | 华邦电子股份有限公司 | Semiconductor memory structure and forming method thereof |
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| JP2007305976A (en) * | 2006-05-09 | 2007-11-22 | Hynix Semiconductor Inc | Method of forming fine pattern in semiconductor device |
| JP2008060517A (en) * | 2006-08-29 | 2008-03-13 | Samsung Electronics Co Ltd | Method of forming mask structure and method of forming fine pattern using the same |
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| JP2009272623A (en) * | 2008-05-02 | 2009-11-19 | Samsung Electronics Co Ltd | Method for forming fine pattern of semiconductor device by means of double patterning process utilizing acid diffusion |
| US8778598B2 (en) | 2008-05-02 | 2014-07-15 | Samsung Electronics Co., Ltd. | Method of forming fine patterns of semiconductor device by using double patterning process which uses acid diffusion |
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| KR20070088248A (en) | 2007-08-29 |
| TWI349306B (en) | 2011-09-21 |
| JP4901526B2 (en) | 2012-03-21 |
| CN100550288C (en) | 2009-10-14 |
| CN101026086A (en) | 2007-08-29 |
| KR100861212B1 (en) | 2008-09-30 |
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