CN113363217B - Semiconductor memory structure and forming method thereof - Google Patents
Semiconductor memory structure and forming method thereof Download PDFInfo
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- CN113363217B CN113363217B CN202010142975.3A CN202010142975A CN113363217B CN 113363217 B CN113363217 B CN 113363217B CN 202010142975 A CN202010142975 A CN 202010142975A CN 113363217 B CN113363217 B CN 113363217B
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor memory structure and a method for forming the same, the method comprises forming a hard mask layer on a semiconductor substrate, etching the hard mask layer to form a plurality of first mask patterns and a plurality of second mask patterns, transferring the first mask patterns and the second mask patterns to the semiconductor substrate to form a plurality of semiconductor blocks, and thinning the second mask patterns. After thinning the second mask pattern, the thickness of the second mask pattern is smaller than the thickness of the first mask pattern. The method further includes forming a first cap layer extending laterally over the first and second mask patterns, and etching the first cap layer and the second mask patterns to form a plurality of contact openings. The invention can improve the reliability and the manufacturing yield of the semiconductor memory device.
Description
Technical Field
The present invention relates to a semiconductor memory structure, and more particularly to a dynamic random access memory.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) devices are widely used in consumer electronics. In order to increase the device density and improve the overall performance within a dram device, current dram device fabrication techniques continue to strive toward the miniaturization of device dimensions.
However, as device sizes continue to shrink, many challenges are presented. For example, in a semiconductor manufacturing process, openings for conductive features (e.g., contact plugs) are formed by photolithography and etching processes. However, overlay shift (overlay shift) problems of the photolithography process may cause short circuits between conductive features in the same layer (plane). Accordingly, there remains a need for improved methods of manufacturing DRAM devices that overcome the problems associated with reduced device sizes.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor memory structure. The method includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form a plurality of first mask patterns and a plurality of second mask patterns, transferring the first mask patterns and the second mask patterns to the semiconductor substrate to form a plurality of semiconductor blocks, and thinning the second mask patterns. After thinning the second mask pattern, the thickness of the second mask pattern is smaller than the thickness of the first mask pattern. The method further includes forming a first cap layer extending laterally over the first and second mask patterns, and etching the first cap layer and the second mask patterns to form a plurality of contact openings.
The embodiment of the invention provides a semiconductor memory structure, which comprises an active region of a semiconductor substrate, wherein the active region comprises a first semiconductor block. The semiconductor memory structure further includes word lines disposed adjacent to the first semiconductor blocks, a cap layer disposed over the mask patterns of the first semiconductor blocks, and a cap layer disposed beside the mask patterns. The cap layer is also disposed in the semiconductor substrate to abut the word line, and an upper surface of the cap layer is substantially flush with an upper surface of the mask pattern.
Drawings
In order to make the features and advantages of the present invention more comprehensible, various embodiments accompanied with figures are described in detail below:
fig. 1 is a schematic top view of a semiconductor memory structure according to some embodiments of the invention.
Fig. 2-16 are schematic cross-sectional views illustrating various stages in the formation of a semiconductor memory structure, in accordance with some embodiments of the present invention.
Symbol description
100: a semiconductor memory structure;
102: a semiconductor substrate;
104: an isolation member;
104A: an isolation member;
104B: an isolation member;
104C: an isolation member;
106A: an active region;
106B: an active region;
106C: an active region;
107 1 : a first semiconductor block;
107 2 : a second semiconductor block;
107 3 : a third semiconductor block;
108: a first hard mask;
108A: a mask pattern;
108B: a mask pattern;
108B': a mask pattern;
110: a second hard mask layer;
110A: a mask pattern;
110B: mask pattern
110B': a mask pattern;
112: a third hard mask layer;
112A: a mask pattern;
112B: a mask pattern;
114: a mask pattern;
116: a compliant layer;
116': a mask pattern;
118: a filling layer;
118': a filling layer;
119: patterning the layer;
120: a gap;
122: a groove;
123: a recess;
124: a groove;
126: a groove;
127: a recess;
130: a word line;
132: a gate dielectric layer;
134: a gate liner;
136: a gate electrode;
138: a first cap layer;
138A: a convex portion;
138B: a concave portion;
138C: a vertical extension;
138R: a first cap layer;
140: a second cap layer;
142: an opening;
144: a void;
146: a contact opening;
148: a contact plug;
150: a bit line;
152: a barrier layer;
154: a conductive layer;
156: a dielectric layer;
1000: etching;
1050: etching;
1100: etching;
1150: etching;
1200: etching;
1250: etching;
1300: etching;
1350: etching;
1400: etching;
d1: thickness;
d2: thickness;
d3: thickness;
d4: thickness;
d5: thickness;
d6: thickness;
d7: thickness;
d8: thickness.
Detailed Description
The present invention will be described more fully hereinafter with reference to the accompanying drawings of embodiments of the invention. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity and the same or similar reference numbers denote the same or similar elements in the various drawings.
Fig. 1 is a schematic top view of a semiconductor memory structure according to some embodiments of the invention. According to some embodiments, a semiconductor memory structure 100 is provided, as shown in fig. 1. In some embodiments, the semiconductor memory structure 100 is part of a Dynamic Random Access Memory (DRAM). According to some embodiments, the semiconductor memory structure 100 includes isolation features 104, active regions 106, word lines 130, contacts 148, and bit lines 150. For illustration, fig. 1 shows only the above components, the remaining components being visible in the cross-sectional schematic view of fig. 16, taken along line I-I of fig. 1.
According to some embodiments, the isolation feature 104 is formed in a semiconductor substrate and includes an isolation feature 104A, an isolation feature 104B, and an isolation feature 104C. According to some embodiments, the isolation members 104A extend along the direction D2 and are aligned in the direction D1. According to some embodiments, isolation member 104B extends along direction D3, while isolation member 104C extends along direction D4. According to some embodiments, the isolation members 104B and the isolation members 104C are each arranged in the direction D2, and the isolation members 104B and the isolation members 104C are alternately arranged in the direction D1.
According to some embodiments, direction D1 is substantially perpendicular to direction D2, direction D1 intersects direction D3 at an acute angle θ1, and direction D1 intersects direction D4 at an obtuse angle θ2.
According to some embodiments, the isolation feature 104 defines a plurality of active regions 106A, 106B, 106C, and 106D in the semiconductor substrate. The active regions 106A-106D are arranged sequentially along the direction D1, and according to some embodiments, two isolation features 104A and two isolation features 104B define one active region 106A and one active region 106C, and two isolation features 104A and two isolation features 104C define one active region 106B and one active region 106D.
According to some embodiments, the bit line 150 is formed over the semiconductor substrate and extends along the direction D1. According to some embodiments, the bit lines 150 are arranged in the direction D2 corresponding to the active regions 106. The word line 130 is formed in the semiconductor substrate and extends along the direction D2. According to some embodiments, the word lines 130 are arranged in the direction D1 in such a way that a pair of word lines 130 corresponds to one active region 106. According to some embodiments, a pair of word lines 130 divide one active region 106 into three semiconductor regions 107 1 、107 2 And 107 3 Wherein the semiconductor region 107 2 Located in semiconductor region 107 1 And semiconductor block 107 3 Between them.
In some embodiments, the contact 148 is located at the intersection of the bit line 150 and the active regions 106A-106D. According to some embodiments, the bit lines 150 are electrically connected to the semiconductor regions 107 of the active regions 106A-106D through the contacts 148 as the bit lines 150 traverse the adjacent pair of word lines 108 2 。
Fig. 2-16 are schematic cross-sectional views illustrating various stages in the formation of a semiconductor memory structure, in accordance with some embodiments of the present invention. The cross-sectional views of fig. 2-16 are taken along line I-I of fig. 1. According to some embodiments, a semiconductor memory structure 100 is provided, as shown in fig. 2. According to some embodiments, the semiconductor memory structure 100 includes a semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 may be an elemental semiconductor substrate, such as a silicon substrate, or a germanium substrate; or a compound semiconductor substrate such as a silicon carbide substrate, or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate.
According to some embodiments, isolation features 104A, 104B, 104C are formed in the semiconductor substrate 102, as shown in fig. 1 and 2. According to some embodiments, the isolation member 104 extends downward from the upper surface of the semiconductor substrate 102 to define the active regions 106A, 106B, 106C, 106D (the active region 106D is not shown in fig. 2-16) of the semiconductor substrate 102. In some embodiments, the isolation feature 104 is formed of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and/or combinations of the foregoing. In some embodiments, the isolation features 104 are formed by a patterning process (e.g., photolithography process and etching process), a deposition process (e.g., chemical vapor deposition (chemical vapor deposition, CVD)), a planarization process (e.g., chemical mechanical polishing (chemical mechanical polish, CMP)).
According to some embodiments, a hard mask layer of a multi-layer structure is formed over the upper surface of the semiconductor substrate 102, the multi-layer structure including a first hard mask layer 108, a second hard mask layer 110, and a third hard mask layer 112, as shown in fig. 2. In some embodiments, the hard mask layer of the multi-layer structure will be patterned into a mask pattern that defines trenches for forming word lines.
In some embodiments, the first hard mask layer 108 is formed of an oxide, such as a silicon oxide layer formed of Tetraethoxysilane (TEOS). In some embodiments, the second hard mask layer 110 is formed of a carbon-rich material, e.g., a carbon layer. In some embodiments, the third hard mask layer 112 is a nitride layer, such as silicon nitride (SiN) or silicon oxynitride (SiON). In some embodiments, the first hard mask layer 108, the second hard mask layer 110, and the third hard mask layer 112 are formed by a deposition process, such as Chemical Vapor Deposition (CVD), atomic layer deposition (atomic layer deposition, ALD), and/or combinations of the foregoing.
According to some embodiments, a plurality of mask patterns 114 are formed over the upper surface of the third hard mask layer 112, as shown in FIG. 2. According to some embodiments, the mask patterns 114 are arranged in the direction D1 (fig. 1), and gaps 120 exist between the mask patterns 114. According to some embodiments, these mask patterns 114 extend in the direction D2 (fig. 1). In some embodiments, the mask pattern 114 is formed of a semiconductor material, such as polysilicon (polysilicon). In some embodiments, a semiconductor material is deposited over the third hard mask layer 112, followed by a photolithography process and an etching process to form a mask pattern 114.
According to some embodiments, a compliant layer 116 is formed along the sidewalls and upper surface of the mask pattern 114 and the upper surface of the third hard mask layer 112, as shown in fig. 2. The compliant layer 116 partially fills the gap 120 as shown in fig. 2. In some embodiments, the compliant layer 116 is formed of an oxide, such as silicon oxide. In some embodiments, the compliant layer 116 is formed by a low-temperature chemical vapor deposition process (low-temperature CVD).
According to some embodiments, a fill layer 118 is formed over the compliant layer 116 as shown in fig. 2. According to some embodiments, the filler layer 118 fills in the remainder of the gap 120. In some embodiments, the fill layer 118 is formed of a carbon-rich material, such as spin-on coating (SOC). In some embodiments, the filler layer 118 is formed by a spin-on process.
According to some embodiments, the semiconductor memory structure 100 is subjected to an etching step 1000 to remove the filler layer 118 over the upper surface of the compliant layer 116 until the upper surface of the compliant layer 116 is exposed, as shown in fig. 3. The remaining fill layer 118 is denoted as fill layer 118'. In some embodiments, the etching step 1000 is a dry etch, e.g., using O 2 And/orCO acts as an etchant.
According to some embodiments, the semiconductor memory structure 100 is subjected to an etching step 1050, removing the portion of the compliant layer 116 not covered by the fill layer 118', until the upper surface of the third hard mask layer 112 is exposed, as shown in fig. 4. The compliant layer 116 covered by the remaining fill layer 118 'is referred to as a mask pattern 116'. In some embodiments, the etching step 1050 is a dry etch, e.g., using CF 4 CHF and/or CHF 3 As an etchant.
According to some embodiments, the etching step 1050 creates a pair of trenches 122 within the confines of the gap 120. According to some embodiments, the pair of trenches 122 are separated from each other by the fill layer 118 'and the mask pattern 116'.
According to some embodiments, the semiconductor memory structure 100 is subjected to an etching step 1100, removing the remaining fill layer 118 'until the upper surface of the mask pattern 116' is exposed, as shown in fig. 5. In some embodiments, the etching step 1100 is a dry etch, e.g., using O 2 As an etchant. According to some embodiments, the mask pattern 114 and the mask pattern 116' are collectively referred to as a patterned layer 119. In some embodiments, the mask patterns 114 alternate with the mask patterns 116' along the direction D1. In some embodiments, the width of the mask pattern 114 is greater than the width of the mask pattern 116', and the thickness of the mask pattern 114 is greater than the thickness of the mask pattern 116'.
According to some embodiments, the etching step 1100 creates a recess 123 over the mask pattern 116' between the pair of trenches 122 such that the pair of trenches 122 are connected to each other by the recess 123.
According to some embodiments, the semiconductor memory structure 100 is subjected to an etching step 1150 using the patterned layer 119 to sequentially etch and remove portions of the third hard mask layer 112 and the second hard mask layer 110 not covered by the mask patterns 114 and 116' until an upper surface of the first hard mask layer 108 is exposed, as shown in fig. 6. In some embodiments, the etching step 1150 is a dry etch, e.g., using SF 6 To etch the third hard mask layer 112 and use O 2 To etch the second hard mask layer 110. In addition, an etching step 1150 extends the trenches 122 toA trench 124 is formed in the third hard mask layer 112 and the second hard mask layer 110.
According to some embodiments, the mask pattern 114 of the patterned layer 119 is transferred to the third hard mask layer 112 and the second hard mask layer 110 such that the third hard mask layer 112 forms a mask pattern 112A and the second hard mask layer 110 forms a mask pattern 110A. According to some embodiments, the mask pattern 116' (fig. 5) of the patterned layer 119 is transferred to the third hard mask layer 112 and the second hard mask layer 110 such that the third hard mask layer 112 forms a mask pattern 112B and the second hard mask layer 110 forms a mask pattern 110B.
In some embodiments, during the etching step 1150, the mask pattern 116' of the patterned layer 119 is substantially completely consumed such that the mask pattern 112B is undercut. Therefore, the thickness D1 of the mask pattern 112A is larger than the thickness D2 of the mask pattern 112B. In some embodiments, the ratio of thickness D2 to thickness D1 ranges from about 0.2 to about 0.4.
According to some embodiments, the second hard mask layer 110 is used to perform an etching step 1200 on the semiconductor memory structure 100 to sequentially etch and remove the first hard mask layer 108 and portions of the semiconductor substrate 102 not covered by the mask patterns 110A and 110B, as shown in fig. 7. In some embodiments, the etching step 1200 is a dry etch, e.g., using CF 3 As an etchant.
According to some embodiments, the etching step 1200 extends the trench 124 into the first hard mask layer 108 and the semiconductor substrate 102, thereby forming the trench 126, as shown in fig. 7. According to some embodiments, the trench 126 divides the active regions 106A-106D into semiconductor regions 107 1 、107 2 、107 3 As shown in fig. 1 and 7. According to some embodiments, a portion of the groove 126 also extends into the isolation member 104. For example, fig. 1 and 7 show portions of trench 126 passing through isolation features 104B and 104C.
According to some embodiments, the mask pattern 110A of the second hard mask layer 110 is transferred to the first hard mask layer 108 such that the first hard mask layer 108 forms the mask pattern 108A. Then, according to some embodiments, the mask pattern 108A of the first hard mask layer 108 is transferred to the semiconductor substrate 102,thereby forming a semiconductor region 107 in the active region 106 1 And semiconductor region 107 in adjacent active region 106 3 。
According to some embodiments, the mask pattern 110B of the second hard mask layer 110 is transferred to the first hard mask layer 108 such that the first hard mask layer 108 forms the mask pattern 108B. Next, according to some embodiments, the mask pattern 108B of the first hard mask layer 108 is transferred to the semiconductor substrate 102 such that the semiconductor substrate 102 forms the second semiconductor region 107 in the active region 106 2 . In some embodiments, the mask patterns 108A and the mask patterns 108B are alternately arranged along the direction D1.
In some embodiments, during the etching step 1200, the mask pattern 114 of the patterned layer 119 and the third hard mask layer 112 are substantially completely consumed, and the mask pattern 110B of the second mask layer 110 is undercut. The undercut mask pattern 110B is denoted as mask pattern 110B'. In some embodiments, the thickness D3 of the mask pattern 110A is greater than the thickness D4 of the mask pattern 110B'. In some embodiments, the ratio of thickness D4 to thickness D3 ranges from about 0.33 to about 0.5.
According to some embodiments, the semiconductor memory structure 100 is subjected to an etching step 1250, removing the mask pattern 110B' of the second hard mask layer 110 until the mask pattern 108B of the first hard mask layer 108 is exposed, as shown in fig. 8. In some embodiments, the etching step 1250 is a dry etch, e.g., using O 2 As an etchant.
According to some embodiments, the etching step 1300 is performed to the semiconductor memory structure 100 to recess the mask pattern 108B of the first hard mask layer 108 to thin the mask pattern 108B, as shown in fig. 9. According to some embodiments, during the etching step 1300, the mask pattern 110A protects the mask pattern 108A such that the mask pattern 108A is not thinned. The undercut mask pattern 108B is denoted as mask pattern 108B'. According to some embodiments, the etching step 1300 creates the recess 127 over the mask pattern 108B' such that the pair of trenches 126 are connected to each other by the recess 127. In some embodiments, the etching step 1300 is a dry etch, e.g., using CF 4 CHF and/or CHF 3 As an etchant.
According to some embodiments, an etching step 1350 is performed on the semiconductor memory structure 100, removing the mask pattern 110A of the second hard mask layer 110 until the mask pattern 108A of the first hard mask layer 108 is exposed, as shown in fig. 10. In some embodiments, the etching step 1350 is a dry etch, e.g., using O 2 As an etchant. In some embodiments, the thickness D5 of the mask pattern 108A is greater than the thickness D6 of the mask pattern 108B'. In some embodiments, the ratio of thickness D6 to thickness D5 ranges from about 0.33 to about 0.5.
According to some embodiments, pairs of word lines 130 are formed in trenches 126, as shown in fig. 1 and 11. According to some embodiments, the word line 130 may be referred to as a buried word line (buried word line). According to some embodiments, these word lines 130 are arranged in the direction D1 (fig. 1). According to some embodiments, these word lines 130 extend in the direction D2 (fig. 1). According to some embodiments, in one active region 106, word line 130 and semiconductor region 107 1 、107 2 、107 3 Are alternately arranged in the transverse direction.
According to some embodiments, word line 130 includes a gate dielectric layer 132, a gate liner layer 134, and a gate electrode 136. According to some embodiments, a gate dielectric layer 132 is formed on the surfaces of the semiconductor substrate 102 and the isolation feature 104 exposed by the trench 126. In some embodiments, gate dielectric layer 132 is formed of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. In some embodiments, gate dielectric layer 132 is formed by thermal oxidation, chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).
According to some embodiments, a gate liner 134 is formed on the gate dielectric layer 132. In some embodiments, the gate liner 134 is formed of tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the gate liner 134 is formed by Chemical Vapor Deposition (CVD), physical vapor deposition (physical vapor deposition, PVD), or Atomic Layer Deposition (ALD).
According to some embodiments, a gate electrode 136 is formed on the gate liner 134. In some embodiments, the gate electrode 136 is formed of a conductive material, such as polysilicon, metal, or metal nitride. In some embodiments, gate electrode 136 is formed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). According to some embodiments, after depositing the materials for gate dielectric layer 132, gate liner 134, and gate electrode 136, gate liner 134 and gate electrode 136 are etched back such that the upper portion of trench 126 is again exposed and a wordline 130 is formed filling the lower portion of trench 126.
According to some embodiments, a first cap layer 138 is formed over the semiconductor memory structure 100, as shown in fig. 12. In some embodiments, first cap layer 138 is formed of a dielectric material, such as silicon nitride or silicon oxide. In some embodiments, the first cap layer 138 is formed by a deposition process having high step coverage (step coverage) or high conformality (uniformity), such as Atomic Layer Deposition (ALD). According to some embodiments, first cap layer 138 includes horizontal extensions 138A and 138B, and vertical extension 138C.
According to some embodiments, the vertical extension 138C of the first cap layer 138 fills the upper portion of the trench 126 and abuts the underlying word line 130. According to some embodiments, the horizontal extension of the first cap layer 138 has an alternating convex-concave profile extending laterally over the mask patterns 108A and 108B' of the first hard mask layer 108. According to some embodiments, the portion of the first cap layer 138 corresponding to the mask pattern 108A is referred to as a protrusion 138A, and the portion of the first cap layer 138 corresponding to the mask pattern 108B is referred to as a recess 138B. According to some embodiments, the upper surface of the protrusion 138A is level higher than the upper surface of the recess 138B such that the two protrusions 138A and the recess 138B therebetween define an opening 142.
According to some embodiments, a second cap layer 140 is formed over the first cap layer 138, as shown in fig. 12. According to some embodiments, second cap layer 140 conforms to the contour of first cap layer 138 such that second cap layer 140 also has an alternating convex-concave contour extending laterally over first cap layer 138. According to some embodiments, the second cap layer 140 includes a protrusion 140A (corresponding to the protrusion 138A) and a recess 140B (corresponding to the recess 138B). According to some embodiments, the upper surface of the convex portion 140A is higher in level than the upper surface of the concave portion 140B.
In some embodiments, the second cap layer 140 is formed of a dielectric material, such as silicon nitride, and/or silicon oxide. In some embodiments, second cap layer 140 is formed by a deposition process having a lower step coverage or lower conformality than first cap layer 138, such as a Plasma Enhanced CVD (PECVD) process. Accordingly, the protrusions 140A have overhanging portions (overhanging) such that upper edges of two adjacent protrusions 140A are close to each other, forming a void 144 having an upwardly tapered profile between the protrusions 140A. In some embodiments, adjacent protrusions 140A merge with one another, forming a closed void 144.
According to some embodiments, an etching step 1400 is performed on the semiconductor memory structure 100 to form the contact openings 146, as shown in fig. 13. According to some embodiments, the etching step 1400 uses the protrusions 140A of the second cap layer 140 as an etch mask. The etchant sequentially and vertically removes the recess 140B of the second cap layer 140, the recess 138B of the first cap layer 138, and the mask pattern 108B' of the first hard mask layer 108 through the void 144 until the semiconductor substrate 102 (i.e., the semiconductor region 107 is exposed 2 ) Is provided. In some embodiments, the contact opening 146 exposes a portion of the isolation member 104B and a portion of the isolation member 104C. In some embodiments, the contact opening 146 tapers downward. In some embodiments, the etching step 1400 is a dry etch, e.g., using CF 4 CHF and/or CHF 3 As an etchant. According to some embodiments, the etching step 1400 is a self-aligned etching step. That is, the etching step 1400 is performed without requiring the formation of additional masking elements (e.g., a patterned photoresist layer) over the semiconductor memory structure 100 by a photolithographic process.
According to some embodiments, during the etching step 1400, the protrusions 140A of the second cap layer 140 are substantially completely consumed such that the etchant laterally removes portions of the protrusions 138A of the first cap layer 138, thereby expanding the voids 144 into the contact openings 146 in the lateral and longitudinal directions. According to some embodiments, after the etching step 1400, the protrusions 138A of the first cap layer 138 remain over the mask pattern 108A of the first hard mask layer 108 and cover the sidewalls and upper surface of the mask pattern 108A.
Embodiments of the present invention achieve self-aligned contact openings 146 by forming cap layers 138 and 140 having a convex-concave profile over mask patterns 108A and 108B' having a thickness differential such that the etching process 1400 is performed without the need for an additional mask formed by a photolithographic process. Therefore, one photoetching process can be saved, the manufacturing efficiency of the semiconductor memory structure can be improved, and the problem of overlay deviation of the photoetching process can be avoided.
In addition, contact openings 146 having desired critical dimensions may be achieved by adjusting the shape and size of voids 144. In some embodiments, the shape and size of the void 144 may be adjusted by adjusting the thickness ratio (D6/D5) of the mask patterns 108B' and 108A, as well as the deposition parameters of the deposition process selected for the first cap layer 138 and the second cap layer 140. For example, if the ratio of thickness D6 to thickness D5 is too large, the size of the void 144 may be too small, such that the critical dimension of the contact opening 146 is small. Conversely, if the ratio of thickness D6 to thickness D5 is too small, the size of the void 144 may be too large, resulting in a larger critical dimension of the contact opening 146.
According to some embodiments, a contact plug 148 is formed in the contact opening 146, as shown in fig. 1 and 14. According to some embodiments, the contact plug 148 falls on the semiconductor region 107 of the semiconductor substrate 102 through the protrusion 138A of the first cap layer 138 2 And (3) upper part. According to some embodiments, a doped region (e.g., a source region or a drain region) is formed in the semiconductor region 107 2 Is in contact with the contact plug 148. According to some embodiments, the contact plug 148 covers a portion of the isolation member 104B and a portion of the isolation member 104B. In some embodiments, since the contact openings 146 for the contact plugs 148 are not formed by a photolithographic process, the contact plugs 148 may be referred to as self-aligned contact plugs. Because of avoiding the problem of overlay shift of the photolithography process, the contact plug 148 and other conductive features (e.g., to the semiconductor region 107) formed later are avoided 1 And 107 3 A contact plug) of the contact plug is short-circuited.
In some embodiments, contact plug 148 is formed of a conductive material. Such as polysilicon, metal, or metal nitride. The metal may be tungsten (W), aluminum (Al), copper (Cu). The metal nitride may be tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the contact plug 148 is formed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), followed by a planarization process (e.g., chemical Mechanical Polishing (CMP)).
In some embodiments, the first cap layer 138 has a thickness D7 along the upper surface of the mask pattern 108A, which ranges from about 20 nanometers (nm) to about 25 nm. In some embodiments, the mask pattern 108A has a thickness D8 ranging from about 70 nanometers to about 90 nanometers. In some embodiments, thickness D7 is less than thickness D8. In some embodiments, the ratio of thickness D7 to thickness D8 ranges from about 0.25 to about 0.33.
According to some embodiments, an etch back process is performed on the semiconductor memory structure 100 to partially remove the protrusion 138A and the contact plug 148 of the first cap layer 138 until the mask pattern 108A is exposed, as shown in fig. 15, the remaining portion of the first cap layer 138 (protrusion 138A and vertical extension 138C) is denoted as a first cap layer 138R. According to some embodiments. After the etching back process, the upper surface of the contact plug 148, the upper surface of the first cap layer 138R, and the upper surface of the mask pattern 108A are substantially flush. According to some embodiments. The contact plug 148 has a height substantially the same as that of the mask pattern 108A. According to some embodiments, the mask pattern 108A serves as an etch stop layer for the etch back process, and thus the contact plug 148 having a desired height may be formed by adjusting the height of the mask pattern 108A.
According to some embodiments, a bit line 150 is formed over the semiconductor memory structure 100, as shown in fig. 1-16. In some embodiments, the bit line 150 is formed over the semiconductor substrate 102 and extends along the direction D1 (fig. 1). In some embodiments, the bit line 150 includes a barrier layer 152 formed over the contact plug 148, the first cap layer 138R, and the mask pattern 108A, and a conductive layer 154 formed over the barrier layer 152. In some embodiments, the barrier layer 152 is formed of titanium (Ti), tantalum (Ta), titanium nitride (TiN), and/or tantalum nitride (TaN). In some embodiments, conductive layer 154 is formed of tungsten (W), aluminum (Al), and/or copper (Cu). In some embodiments, forming the bit line 150 may include a deposition process and a patterning process.
According to some embodiments, a dielectric layer 156 is formed over the bit line 150, as shown in FIG. 16. In some embodiments, the material of dielectric layer 156 is silicon nitride, silicon oxide, and/or silicon oxynitride, and is formed by a chemical vapor deposition process.
In some embodiments, additional features may be formed, for example, to the semiconductor region 107 1 And 107 3 A contact plug, a component of a capacitor, etc., on the semiconductor memory structure 100 to manufacture a semiconductor memory device. In some embodiments, the semiconductor memory device is a Dynamic Random Access Memory (DRAM).
According to an embodiment of the present invention, the semiconductor memory structure 100 includes a plurality of active regions 106 of the semiconductor substrate 102, each of the active regions 106 includes a semiconductor region 107 1 、107 2 、107 3 . The semiconductor memory structure 100 further includes a semiconductor region 107 1 、107 2 、107 3 Word lines 130 are alternately arranged laterally. The semiconductor memory structure 100 further includes a cover semiconductor region 107 1 And 107 3 Is included in the mask pattern 108A. The mask pattern 108A also covers part of the isolation members 104A, 104B, 104C. The semiconductor memory structure 100 further includes a first cap layer 138R beside the mask pattern 108A and extending into the semiconductor substrate 102 to abut the word line 130. The semiconductor memory structure 100 further includes a contact plug 148 buried in the first cap layer 138R and located in the semiconductor region 107 2 And (3) upper part. According to some embodiments, the upper surface of the contact plug 148, the upper surface of the first cap layer 138R, is substantially flush with the upper surface of the mask pattern 108A. The semiconductor memory structure 100 further includes a bit line 150 disposed on the contact plug 148, the first cap layer 138R and the mask pattern 108A and electrically coupled to the semiconductor region 107 of the active region 106 through the contact plug 148 2 . According to some embodiments, the bit line 150 directly contacts the contact plug 148, the first cap layer 138R, and the mask pattern 108A.
According to the above, the embodiment of the invention provides a method for forming a semiconductor memory structure with a self-aligned contact plug. Thus, the problem of overlay shift of the photolithography process is avoided, and the contact plug and other conductive parts (for example, to the semiconductor region 107) formed later are avoided 1 And 107 3 A contact plug) of the contact plug is short-circuited. Therefore, the reliability and the manufacturing yield of the semiconductor memory device are improved.
Although the present invention has been described in terms of the foregoing embodiments, it is not limited thereto. Those skilled in the art will appreciate that many modifications and variations may be made without departing from the spirit and scope of the invention. The scope of the invention is therefore defined by the appended claims.
Claims (11)
1. A method of forming a semiconductor memory structure, comprising:
forming a hard mask layer on a semiconductor substrate;
etching the hard mask layer to form a plurality of first mask patterns and a plurality of second mask patterns;
transferring the first mask pattern and the second mask pattern to the semiconductor substrate to form a plurality of semiconductor blocks;
thinning the second mask pattern, wherein after thinning the second mask pattern, a thickness of the second mask pattern is less than a thickness of the first mask pattern;
forming a first cap layer extending laterally over the first mask pattern and the second mask pattern; and
etching the first cap layer and the second mask pattern to form a plurality of contact openings;
the etching the first cap layer and the second mask pattern to form a plurality of contact openings, comprising:
providing said first cover layer comprising a horizontal extension extending over said first mask pattern and said second mask pattern, said horizontal extension having alternating convex-concave contours; forming a second cap layer extending laterally over the first cap layer, wherein the second cap layer conforms to the first cap layer to have alternating convex-concave profiles, the second cap layer having a plurality of second protrusions corresponding to the first mask pattern, and upper edges of adjacent two of the second protrusions being adjacent to each other to form a void having an upwardly tapered profile, and wherein the step of etching the first cap layer comprises: the second cap layer is etched to form the contact opening.
2. The method of forming a semiconductor memory structure of claim 1, further comprising:
forming a patterning layer on the hard mask layer, wherein the patterning layer comprises a plurality of third mask patterns and a plurality of fourth mask patterns, wherein the thickness of the third mask patterns is greater than that of the fourth mask patterns, and the third mask patterns and the fourth mask patterns are formed of different materials.
3. The method of forming a semiconductor memory structure of claim 2, wherein the step of forming the patterned layer comprises:
forming a semiconductor layer over the hard mask layer;
patterning the semiconductor layer to form the third mask pattern;
forming a compliant layer along the third mask pattern and the hard mask layer;
forming a filling layer on the compliant layer between the third mask patterns;
removing portions of the compliant layer not covered by the fill layer; and
the fill layer is removed, leaving the compliant layer as the fourth mask pattern.
4. The method of forming a semiconductor memory structure of claim 1, further comprising:
a word line is formed in a lower portion of a trench between the semiconductor blocks, wherein the first cap layer is formed to fill an upper portion of the trench.
5. The method of forming a semiconductor memory structure according to claim 1, wherein the horizontal extension of the first cap layer has a plurality of convex portions corresponding to the first mask pattern and a plurality of concave portions corresponding to the second mask pattern.
6. The method of forming a semiconductor memory structure of claim 1, further comprising:
a contact plug is formed in the contact opening.
7. The method of forming a semiconductor memory structure of claim 6, further comprising:
removing a portion of the first cover layer higher than the first mask pattern to expose the first mask pattern; and
a bit line is formed over the first mask pattern and the contact plug.
8. A semiconductor memory structure formed by the method of forming a semiconductor memory structure according to any one of claims 1 to 7, the semiconductor memory structure comprising:
an active region of a semiconductor substrate, comprising a first semiconductor block and a second semiconductor block;
a word line disposed in the semiconductor substrate adjacent to the first semiconductor block;
a mask pattern disposed over the first semiconductor block;
a cap layer disposed beside the mask pattern and in the semiconductor substrate to abut the word line, wherein an upper surface of the cap layer is substantially flush with an upper surface of the mask pattern; and
and a contact plug formed in the contact opening, buried in the cap layer and disposed on the second semiconductor block.
9. The semiconductor memory structure according to claim 8, wherein an upper surface of the mask pattern is substantially flush with an upper surface of the contact plug.
10. The semiconductor memory structure of claim 8, further comprising:
a bit line disposed over the mask pattern, the cap layer and the contact plug.
11. The semiconductor memory structure of claim 8, further comprising:
an isolation member disposed in the semiconductor substrate, wherein a portion of the word line is disposed in the isolation member, wherein the mask pattern covers a portion of the isolation member.
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| KR100771891B1 (en) * | 2006-11-10 | 2007-11-01 | 삼성전자주식회사 | Method of forming fine patterns of semiconductor device using double patterning process |
| TWI684822B (en) * | 2015-09-30 | 2020-02-11 | 日商Ｈｏｙａ股份有限公司 | Blank mask, phase shift mask and method for manufacturing semiconductor element |
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| JP2003100751A (en) * | 2001-09-26 | 2003-04-04 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| CN101026086A (en) * | 2006-02-24 | 2007-08-29 | 海力士半导体有限公司 | Method for forming fine pattern of semiconductor device |
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