CN104576510A - Self-alignment contact hole etching method - Google Patents
Self-alignment contact hole etching method Download PDFInfo
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- CN104576510A CN104576510A CN201310509004.8A CN201310509004A CN104576510A CN 104576510 A CN104576510 A CN 104576510A CN 201310509004 A CN201310509004 A CN 201310509004A CN 104576510 A CN104576510 A CN 104576510A
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Abstract
The invention discloses a self-alignment contact hole etching method which comprises the following steps of providing a silicon substrate provided with a plurality of gate structures, depositing a silicon nitride side wall, depositing first phosphorosilicate glass comprising bud structures by an HDPCVD (High Density Plasma Chemical Vapor Deposition) technology, etching the first phosphorosilicate glass with an etching area defined by a minimum distance between the adjacent bud structures, etching the silicon nitride side wall by taking an etched figure of the first phosphorosilicate glass as a mask, completely removing the first phosphorosilicate glass and forming an L-shaped grid side wall, forming a self-alignment source area and a drain area, removing a hard mask layer and the silicon nitride side wall from a window in a grid contact area, depositing and flattening second phosphorosilicate glass, forming an undoped third silicon dioxide layer, defining a figure of a self-alignment contact hole by a photoetching technology, and etching to form the self-alignment contact hole. The method can reduce the heights of the gate structures, increase grid distances, reduce PSG (Phosphosilicate Glass) filling difficulty among the gate structures, enhance etching power of the self-alignment contact hole and improve etching quality of the self-alignment contact hole.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of self-aligned contact etch method.
Background technology
As shown in Figure 1, be the self-aligned contact hole section of structure that existing self-aligned contact etch method is formed; Existing self-aligned contact etch method comprises following processing step:
Step one, the silicon substrate 101 providing to be formed with multiple grid structure, described grid structure comprises the gate dielectric layer 102, grid polycrystalline silicon 103 and the hard mask layer 106 that are formed at described silicon substrate 101 surface successively, and the figure of described grid structure is defined by described hard mask layer 106; Self aligned lightly doped drain note district 104 is formed in the described silicon substrate 101 of each described grid structure both sides.Wherein gate dielectric layer 102 can be gate oxide, and grid polycrystalline silicon 103 adopts chemical vapor deposition (CVD) technique to be formed.
Hard mask layer 106 adopts low pressure chemical vapor phase deposition (LPN) boiler tube mode to grow formation.Hard mask layer 106 adopts thickness to be approximately usually
silicon nitride, the effect of hard mask layer 106 has: be on the one hand for grid polycrystalline silicon 103 provides protection when grid polycrystalline silicon 103 etches; In addition, the thickness increasing hard mask layer 106 can also increase the height of whole grid structure, can increase the thickness b of the top grid side wall of grid polycrystalline silicon 103 like this; Again, barrier layer is provided when self-aligned contact hole 109 etches for grid polycrystalline silicon 103.
Step 2, deposit the silicon nitride spacer 107 of one deck for the formation of side wall in the upper LPN boiler tube mode of described silicon substrate 101; Described silicon substrate 101 adopts incorgruous dry etching silicon nitride side wall 107, and the silicon nitride spacer 107 be etched on silicon substrate 101 is removed completely.
The thickness of silicon nitride spacer 107 that LPN boiler tube mode deposits herein can be
when carrying out incorgruous dry etching silicon nitride side wall 107, the thickness of the silicon nitride spacer 107 on gate structure sidewall has certain loss, and the bottom thickness a of the silicon nitride spacer 107 after having etched is approximately
top thickness b also can reduce.
Step 3, carry out on described silicon substrate 101 source and drain ion implantation formed source-drain area 105.
Step 4, on described silicon substrate 101, adopt high-density plasma chemical vapor deposition (HDP CVD) mode sedimentary phosphor silex glass (PSG), and carry out cmp (CMP), then at the unadulterated silicon dioxide of surface deposition one deck (USG), then self-aligned contact hole 109 is etched with photoetching and etching technics to above on the grid polycrystalline silicon 103 needing to be connected contact hole and heavily doped region and source-drain area 105.Self-aligned contact hole 109 on source-drain area 105 and the contact area of source-drain area 105 self-defined by two silicon nitride spacer 107 between each adjacent described grid structure; The contact window that self-aligned contact hole 109 on grid polycrystalline silicon 103 and the contact area of grid polycrystalline silicon 103 are formed by grid polycrystalline silicon 103 top etch is self-defined.
When the self-aligned contact hole 109 on source-drain area 105 being formed to etching in existing method, self-aligned contact hole 109 can be connected across certain distance d on silicon nitride spacer 107, can cause certain destruction like this when etching and forming self-aligned contact hole 109 to silicon nitride spacer 107.In addition, when existing method forms grid curb wall, the thickness of the silicon nitride spacer 107 on gate structure sidewall also has certain loss, and the bottom thickness a of silicon nitride spacer 107 can be made to be greater than top thickness b all the time.In order to maintain the top thickness b of silicon nitride spacer 107, existing method is that the thickness by increasing hard mask layer 106 realizes, the increase of the thickness of hard mask layer 106 can make the increase of the thickness of whole grid structure, when gate pitch c is less, the groove structure between grid structure can be made to have larger depth-to-width ratio, not easily fill the groove structure between grid structure when the PSG in subsequent step four can be made like this to deposit, add technology difficulty; In addition, when gate pitch c is less, follow-up self-aligned contact etch window also can be made too little, and contact hole is not easy open completely and form defect.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of self-aligned contact etch method, the height of grid structure can be reduced, increase gate pitch, the etching quality that the PSG that can reduce between grid structure fills difficulty, strengthens the etching power of self-aligned contact hole, improves self-aligned contact hole.
For solving the problems of the technologies described above, self-aligned contact etch method provided by the invention comprises the steps:
Step one, the silicon substrate providing to be formed with multiple grid structure, described grid structure comprises the gate dielectric layer, grid polycrystalline silicon and the hard mask layer that are formed at described surface of silicon successively, and the figure of described grid structure is defined by described hard mask layer; Self aligned lightly doped drain note district is formed in the described silicon substrate of each described grid structure both sides.
Step 2, front deposit silicon nitride side wall at described silicon substrate, described silicon nitride spacer covers the described surface of silicon outside the described hard mask layer top surface of described grid structure, the side of described grid structure and described grid structure.
Step 3, employing high-density plasma chemical vapor deposition technique are at described silicon nitride spacer surface deposition ground floor phosphorosilicate glass, described ground floor phosphorosilicate glass comprises petal shape structure, and petal shape structure described in each corresponds to a described grid structure and surrounded by corresponding described grid structure; Outside the described silicon nitride spacer of the side of each described grid structure, the width being positioned at the described petal shape structure of the side bottom of described grid structure is less than the width of the described petal shape structure of the side top being positioned at described grid structure; The phosphorus solubility of each described petal shape inside configuration is less than the phosphorus solubility of the described phosphorosilicate glass of described petal shape outside.
Step 4, the incorgruous etching technics of first time dry method is adopted to etch described ground floor phosphorosilicate glass, the incorgruous etching technics of described first time dry method utilizes the etch rate of described petal shape inside configuration and outside difference realize the removal of the described ground floor phosphorosilicate glass between each described petal shape structure and exposed on the described silicon nitride spacer surface bottom removed described ground floor phosphorosilicate glass, after the incorgruous etching of described first time dry method, between each described grid structure, the width of removed described ground floor phosphorosilicate glass is self-defined by the minimum spacing between each adjacent described petal shape structure.
Step 5, the incorgruous etching technics of employing second time dry method etch described silicon nitride spacer, the figure that the incorgruous etching technics of described second time dry method utilizes the described ground floor phosphorosilicate glass after the incorgruous etching of described first time dry method to be formed does mask, and the described silicon nitride spacer after incorgruous for first time dry method etching between each described grid structure bottom removed described ground floor phosphorosilicate glass is all removed by the incorgruous etching technics of described second time dry method.
Step 6, after the incorgruous etching technics of described second time dry method completes, all remove described ground floor phosphorosilicate glass also form the L-type grid curb wall be made up of described silicon nitride spacer, the bottom of each described L-type grid curb wall extends a segment distance outside the side of each described grid structure, and the top spacing of two described L-type grid curb walls between each adjacent described grid structure is greater than bottom space.
Step 7, employing source and drain ion implantation technology form self aligned source-drain area in the described silicon substrate of each described grid structure both sides.
Step 8, need in the subregion of each described grid structure formed gate contact, adopt photoetching process define gate contact portion window and the described hard mask layer at the described grid polycrystalline silicon top at window place, described gate contact portion and described silicon nitride spacer all removed.
After step 9, step 8 complete, employing high-density plasma chemical vapor deposition technique is at the front of described silicon substrate deposition second layer phosphorosilicate glass, adopts chemical mechanical milling tech to carry out planarization to described second layer phosphorosilicate glass; Unadulterated third layer silicon dioxide is formed on described second layer phosphorosilicate glass top after planarization.
Step 10, employing photoetching process define self-aligned contacts hole pattern, adopt dry etch process the described third layer silicon dioxide of self-aligned contact hole forming region and described second layer phosphorosilicate glass are removed and form self-aligned contact hole; Described self-aligned contact hole comprises gate contact hole for being connected with described grid polycrystalline silicon and the source-drain area contact hole for being connected with described source-drain area; The described gate polycrystalline silicon face of position, described gate contact portion exposes by described gate contact hole, and the contact area of described gate contact hole and described grid polycrystalline silicon is self-defined by described gate contact portion window; The contact area of described source and drain contact hole and described source-drain area is self-defined by two described L-type grid curb walls between each adjacent described grid structure.
Further improvement is, to be thickness be hard mask layer described in step one
silicon oxynitride; Or to be thickness be described hard mask layer
silicon nitride.
Further improvement is, the thickness of described hard mask layer is the odd-multiple of 1/2 of lithographic wavelength.
Further improvement is, the thickness of silicon nitride spacer described in step 2 is
The etching of grid curb wall of the present invention adopts the graphic structure of the self-defined formation of petal shape structure of HDP CVD technique formation to be mask, this mask can carry out good protection when grid curb wall etches to the silicon nitride spacer on gate structure sidewall, thus the loss to the silicon nitride spacer on gate structure sidewall can be avoided, compared to the method adopting comprehensive etch silicon nitride side wall to form grid curb wall in prior art, because the present invention can avoid the loss to the silicon nitride spacer on gate structure sidewall, thus the present invention can adopt thinner silicon nitride spacer and hard mask layer, the wherein thinning height that can reduce grid structure of hard mask layer, the thinning spacing that can increase grid structure of silicon nitride spacer, this makes it possible to the depth-to-width ratio of the groove structure reduced between grid structure, what the reduction of the groove depth-to-width ratio PSG that can reduce between grid structure filled difficulty and self-aligned contact hole opens difficulty, thus the etching power of self-aligned contact hole can be strengthened, improve the etching quality of self-aligned contact hole.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the self-aligned contact hole section of structure that existing self-aligned contact etch method is formed;
Fig. 2 is embodiment of the present invention method flow diagram;
Fig. 3 A-Fig. 3 G is the self-aligned contact hole section of structure in each step of embodiment of the present invention method.
Embodiment
As shown in Figure 2, be embodiment of the present invention method flow diagram; As shown in Fig. 3 A to Fig. 3 G, it is the self-aligned contact hole section of structure in each step of embodiment of the present invention method.Embodiment of the present invention self-aligned contact etch method comprises the steps:
Step one, as shown in Figure 3A, the silicon substrate 1 that one is formed with multiple grid structure is provided, described grid structure comprises the gate dielectric layer 2, grid polycrystalline silicon 3 and the hard mask layer 4 that are formed at described silicon substrate 1 surface successively, the figure of described grid structure is defined by described hard mask layer 4, namely defines the figure of described grid structure by described hard mask layer 4 and under the protection of described hard mask layer 4, carries out the etching of described grid polycrystalline silicon 3; Self aligned lightly doped drain note district 5 is formed in the described silicon substrate 1 of each described grid structure both sides.
Be preferably, gate dielectric layer 2 is gate oxide.Grid polycrystalline silicon 103 adopts chemical vapor deposition method to be formed.
Described hard mask layer 4 for thickness is
silicon oxynitride; Or described hard mask layer 4 for thickness is
silicon nitride.More preferably the thickness being selected as described hard mask layer 4 is the odd-multiple of 1/2 of lithographic wavelength.Described hard mask layer 4 adopts LPN boiler tube mode to grow.
Step 2, as shown in Figure 3 B, at the front deposit silicon nitride side wall 6 of described silicon substrate 1, described silicon nitride spacer 6 covers described silicon substrate 1 surface outside described hard mask layer 4 top surface of described grid structure, the side of described grid structure and described grid structure.Be preferably, the thickness of described silicon nitride spacer 6 is
Step 3, as shown in Figure 3 C, adopt high-density plasma chemical vapor deposition technique at described silicon nitride spacer 6 surface deposition ground floor phosphorosilicate glass 7, described ground floor phosphorosilicate glass 7 comprises petal shape structure 7a, and the described ground floor phosphorosilicate glass 7 of described petal shape structure 7a outside is labeled as 7b.Petal shape structure 7a is that the sputtering raste due to the ion pair different materials of HDP CVD in the deposition process of HDP CVD is different, thus forms the crustose figure of petal shape and described petal shape structure 7a having on flagpole pattern.So petal shape structure 7a described in each corresponds to a described grid structure and is surrounded by corresponding described grid structure; Outside the described silicon nitride spacer 6 of the side of each described grid structure, the width being positioned at region shown in the described petal shape structure 7a of the side bottom of described grid structure and dotted line money 7c is less than the width in region shown in the described petal shape structure 7a of the side top being positioned at described grid structure and dotted line money 7c; The phosphorus solubility of each described petal shape structure 7a inside is less than the phosphorus solubility of the described phosphorosilicate glass of described petal shape outside.
Step 4, as shown in Figure 3 D, the incorgruous etching technics of first time dry method is adopted to etch described ground floor phosphorosilicate glass 7, the incorgruous etching technics of described first time dry method utilizes described petal shape structure 7a inside and outside etch rate difference realize the removal of the described ground floor phosphorosilicate glass 7 between each described petal shape structure 7a and exposed on described silicon nitride spacer 6 surface bottom removed described ground floor phosphorosilicate glass 7, after the incorgruous etching of described first time dry method between each described grid structure the width of removed described ground floor phosphorosilicate glass 7 and width d1 self-defined by the minimum spacing between each adjacent described petal shape structure 7a.As can be seen from Fig. 3 D, width d1 is less than spacing between adjacent described silicon nitride spacer 6 and width d2.
Step 5, as shown in FIGURE 3 E, the incorgruous etching technics of second time dry method is adopted to etch described silicon nitride spacer 6, the figure that the incorgruous etching technics of described second time dry method utilizes the described ground floor phosphorosilicate glass 7 after the incorgruous etching of described first time dry method to be formed does mask, and the described silicon nitride spacer 6 after incorgruous for first time dry method etching between each described grid structure bottom removed described ground floor phosphorosilicate glass 7 is all removed by the incorgruous etching technics of described second time dry method.
Step 6, as illustrated in Figure 3 F, after the incorgruous etching technics of described second time dry method completes, all remove described ground floor phosphorosilicate glass 7 also form the L-type grid curb wall be made up of described silicon nitride spacer 6, the bottom of each described L-type grid curb wall extends a segment distance outside the side of each described grid structure, and top spacing and the width d2 of two described L-type grid curb walls between each adjacent described grid structure are greater than bottom space and width d1.The bottom width of each described L-type grid curb wall is that width d3 is greater than top width and width d4.Because the incorgruous etching technics of described second time dry method in embodiment of the present invention step 5 does not cause loss to the described silicon nitride spacer 6 of the side being positioned at each described grid structure, therefore the thickness of described silicon nitride spacer 6 when the thickness of the position of each described L-type grid curb wall remains deposit.
Because the thickness of the present invention's described silicon nitride spacer 6 in better situation is
and the original depth of silicon nitride spacer of the prior art 107 is as shown in Figure 1
final thickness after loss is
so the gate pitch that finally formed of the embodiment of the present invention and width d2 more about than the width c in prior art and Fig. 1
In like manner the embodiment of the present invention does not cause loss to the described silicon nitride spacer 6 of the side being positioned at each described grid structure in the incorgruous etching technics of second time dry method, so can not reduce at the width d4 at each described L-type grid curb wall top, width d4 is directly determined by the thickness of described silicon nitride spacer 6 and described hard mask layer 4, unnecessary minimizing in order to compensate width d4 in such embodiment of the present invention and increase the thickness of described hard mask layer 4.The thickness of described hard mask layer 4 is in embodiments of the present invention
, and in prior art as shown in Figure 1, the thickness of hard mask layer 106 is approximately
so the embodiment of the present invention can make the height reduction of grid structure about
Step 7, as illustrated in Figure 3 F, adopts source and drain ion implantation technology to form self aligned source-drain area 8 in the described silicon substrate 1 of each described grid structure both sides.
Step 8, as illustrated in Figure 3 F, need to form gate contact in the subregion of each described grid structure, adopt photoetching process define gate contact portion window and the described hard mask layer 4 at described grid polycrystalline silicon 3 top at window place, described gate contact portion and described silicon nitride spacer 6 all removed.
Step 9, as shown in Figure 3 G, after step 8 completes, employing high-density plasma chemical vapor deposition technique is at the front of described silicon substrate 1 deposition second layer phosphorosilicate glass 9, adopts chemical mechanical milling tech to carry out planarization to described second layer phosphorosilicate glass 9; Unadulterated third layer silica 10 is formed on described second layer phosphorosilicate glass 9 top after planarization.
Step 10, as shown in Figure 3 G, adopt photoetching process to define self-aligned contacts hole pattern, adopt dry etch process the described third layer silica 10 of self-aligned contact hole forming region and described second layer phosphorosilicate glass 9 are removed and form self-aligned contact hole 11; Described self-aligned contact hole 11 comprises gate contact hole for being connected with described grid polycrystalline silicon 3 and the source-drain area contact hole for being connected with described source-drain area 8; Described grid polycrystalline silicon 3 surface of position, described gate contact portion is exposed by described gate contact hole, and the contact area of described gate contact hole and described grid polycrystalline silicon 3 is self-defined by described gate contact portion window; The contact area of described source and drain contact hole and described source-drain area 8 is self-defined by two described L-type grid curb walls between each adjacent described grid structure.Finally need to fill metal in described self-aligned contact hole 11.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a self-aligned contact etch method, is characterized in that, comprises the steps:
Step one, the silicon substrate providing to be formed with multiple grid structure, described grid structure comprises the gate dielectric layer, grid polycrystalline silicon and the hard mask layer that are formed at described surface of silicon successively, and the figure of described grid structure is defined by described hard mask layer; Self aligned lightly doped drain note district is formed in the described silicon substrate of each described grid structure both sides;
Step 2, front deposit silicon nitride side wall at described silicon substrate, described silicon nitride spacer covers the described surface of silicon outside the described hard mask layer top surface of described grid structure, the side of described grid structure and described grid structure;
Step 3, employing high-density plasma chemical vapor deposition technique are at described silicon nitride spacer surface deposition ground floor phosphorosilicate glass, described ground floor phosphorosilicate glass comprises petal shape structure, and petal shape structure described in each corresponds to a described grid structure and surrounded by corresponding described grid structure; Outside the described silicon nitride spacer of the side of each described grid structure, the width being positioned at the described petal shape structure of the side bottom of described grid structure is less than the width of the described petal shape structure of the side top being positioned at described grid structure; The phosphorus solubility of each described petal shape inside configuration is less than the phosphorus solubility of the described phosphorosilicate glass of described petal shape outside;
Step 4, the incorgruous etching technics of first time dry method is adopted to etch described ground floor phosphorosilicate glass, the incorgruous etching technics of described first time dry method utilizes the etch rate of described petal shape inside configuration and outside difference realize the removal of the described ground floor phosphorosilicate glass between each described petal shape structure and exposed on the described silicon nitride spacer surface bottom removed described ground floor phosphorosilicate glass, after the incorgruous etching of described first time dry method, between each described grid structure, the width of removed described ground floor phosphorosilicate glass is self-defined by the minimum spacing between each adjacent described petal shape structure,
Step 5, the incorgruous etching technics of employing second time dry method etch described silicon nitride spacer, the figure that the incorgruous etching technics of described second time dry method utilizes the described ground floor phosphorosilicate glass after the incorgruous etching of described first time dry method to be formed does mask, and the described silicon nitride spacer after incorgruous for first time dry method etching between each described grid structure bottom removed described ground floor phosphorosilicate glass is all removed by the incorgruous etching technics of described second time dry method;
Step 6, after the incorgruous etching technics of described second time dry method completes, all remove described ground floor phosphorosilicate glass also form the L-type grid curb wall be made up of described silicon nitride spacer, the bottom of each described L-type grid curb wall extends a segment distance outside the side of each described grid structure, and the top spacing of two described L-type grid curb walls between each adjacent described grid structure is greater than bottom space;
Step 7, employing source and drain ion implantation technology form self aligned source-drain area in the described silicon substrate of each described grid structure both sides;
Step 8, need in the subregion of each described grid structure formed gate contact, adopt photoetching process define gate contact portion window and the described hard mask layer at the described grid polycrystalline silicon top at window place, described gate contact portion and described silicon nitride spacer all removed;
After step 9, step 8 complete, employing high-density plasma chemical vapor deposition technique is at the front of described silicon substrate deposition second layer phosphorosilicate glass, adopts chemical mechanical milling tech to carry out planarization to described second layer phosphorosilicate glass; Unadulterated third layer silicon dioxide is formed on described second layer phosphorosilicate glass top after planarization;
Step 10, employing photoetching process define self-aligned contacts hole pattern, adopt dry etch process the described third layer silicon dioxide of self-aligned contact hole forming region and described second layer phosphorosilicate glass are removed and form self-aligned contact hole; Described self-aligned contact hole comprises gate contact hole for being connected with described grid polycrystalline silicon and the source-drain area contact hole for being connected with described source-drain area; The described gate polycrystalline silicon face of position, described gate contact portion exposes by described gate contact hole, and the contact area of described gate contact hole and described grid polycrystalline silicon is self-defined by described gate contact portion window; The contact area of described source and drain contact hole and described source-drain area is self-defined by two described L-type grid curb walls between each adjacent described grid structure.
2. self-aligned contact etch method as claimed in claim 1, is characterized in that: to be thickness be hard mask layer described in step one
silicon oxynitride; Or to be thickness be described hard mask layer
silicon nitride.
3. self-aligned contact etch method as claimed in claim 2, is characterized in that: the thickness of described hard mask layer is the odd-multiple of 1/2 of lithographic wavelength.
4. self-aligned contact etch method as claimed in claim 1, is characterized in that: the thickness of silicon nitride spacer described in step 2 is
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| CN112151450A (en) * | 2019-06-26 | 2020-12-29 | 联华电子股份有限公司 | Semiconductor structure and forming method thereof |
| CN113363217A (en) * | 2020-03-04 | 2021-09-07 | 华邦电子股份有限公司 | Semiconductor memory structure and forming method thereof |
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| CN113363217A (en) * | 2020-03-04 | 2021-09-07 | 华邦电子股份有限公司 | Semiconductor memory structure and forming method thereof |
| CN113363217B (en) * | 2020-03-04 | 2024-02-06 | 华邦电子股份有限公司 | Semiconductor memory structure and forming method thereof |
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