CN102543878B - Manufacturing method of storage - Google Patents
Manufacturing method of storage Download PDFInfo
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- CN102543878B CN102543878B CN201010621017.0A CN201010621017A CN102543878B CN 102543878 B CN102543878 B CN 102543878B CN 201010621017 A CN201010621017 A CN 201010621017A CN 102543878 B CN102543878 B CN 102543878B
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Abstract
The invention discloses a manufacturing method of a storage. The manufacturing method comprises the following steps of: providing a substrate comprising a storage unit region and a peripheral region, wherein a plurality of grids with clearance walls are formed on the substrate, and a plurality of openings are formed among the grids of the storage unit region; forming a first material layer in the storage unit region to cover the grids and fill the openings; forming a barrier layer on the substrate to cover the grids of the peripheral region and the first material layer of the storage unit region; forming a second material layer on the substrate of the peripheral region to cover the barrier layer on the grids of the peripheral region; removing the barrier layer covering the first material layer; removing a part of the first material layer to form a plurality of second openings, wherein the second openings are positioned on the tops of the grids of the storage unit region; forming patterns in the second openings; removing the first material layer to form a plurality of contact window openings; and forming a contact window plug in each contact window opening. According to the method, a process can be simplified, and the storage has good properties.
Description
Technical field
The present invention relates to a kind of manufacture method of memory.
Background technology
In general, along with the size of memory is dwindled gradually, in order to overcome more and more little live width and to prevent contact hole generation aligning mistake (misalignment), can adopt self-aligning contact window (self-aligned contact, SAC) technique.
In self-aligning contact window technique, the clearance wall thickness of gate lateral wall can affect the size that is formed at the contact hole between grid.Yet, because memory component comprises memory cell areas and external zones, and the element of memory cell areas and external zones for clearance wall thickness require differently, therefore increased the complexity of technique.In general, can on the gate lateral wall of memory cell areas and external zones, form ground floor clearance wall, then, in order to form source electrode and the drain region of external zones, meeting forms second layer clearance wall on the ground floor clearance wall of the grid of external zones again conventionally simultaneously.Wherein, for simple process, second layer spacer material can be inserted simultaneously to the opening between the grid of memory cell areas, and form source electrode and drain region in the substrate of external zones after, then remove in the lump the second layer spacer material between the second layer clearance wall of external zones and the grid of memory cell areas.
Yet because the opening between the grid of memory cell areas has larger depth-to-width ratio, it is totally very difficult therefore the second layer spacer material between grid will being removed, and may hurt the ground floor clearance wall of memory cell areas in removing process.Thus, cause ground floor clearance wall to provide good being electrically insulated for grid, and the size that affects the formed contact hole of later use ground floor clearance wall.In addition, the not good condition that removes can cause damage to the substrate of external zones, causes element characteristic to be degenerated.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of memory, to simplify step and to make memory there is good element characteristic.
The present invention proposes a kind of manufacture method of memory.First, provide a substrate, substrate comprises a memory cell areas and an external zones, has been formed with a plurality of grids in substrate, and on the sidewall of each grid, has one first clearance wall, wherein between the grid of memory cell areas, has a plurality of the first openings.Then, in the substrate of memory cell areas, form one first material layer, the grid of the first layer of material covers memory cell areas and fill up the first opening.Then, in substrate, form a barrier layer, to cover the grid of external zones and the first material layer of memory cell areas.Then, in the substrate of external zones, form one second material layer, to cover the barrier layer on the grid of external zones.Then, remove the barrier layer that covers the first material layer.Then, remove part the first material layer, to form a plurality of the second openings, each second opening is positioned on the top of each grid of memory cell areas.Then, in each second opening, form one first pattern.Then, remove remaining the first material layer, to form a plurality of contact windows in memory cell areas.Then, form a contact window plug in each contact window, wherein the first pattern arrangement is between contact window plug.
Beneficial effect of the present invention is; based on above-mentioned; the manufacture method of memory of the present invention is protected respectively the element of memory cell areas and external zones with the first material layer and the second material layer; therefore to external zones and memory cell areas, one of them deposit and during the processing such as etching; in external zones and memory cell areas wherein another can not come to harm, the structure that the gap wall energy on gate lateral wall is remained intact.Thus, gap wall energy provides good being electrically insulated for grid, and can between two adjacent clearance walls, form self-aligned contact hole, makes memory have good element characteristic.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 to Fig. 9 is the manufacture method flow process generalized section according to a kind of memory of one embodiment of the invention.
Wherein, description of reference numerals is as follows:
100: substrate
102: memory cell areas
104: external zones
110,120: grid
110a: top
112,122,124: clearance wall
114,132: opening
126: source electrode and drain region
130,150: material layer
134,135: contact window
136,137: contact window plug
140: barrier layer
150a: end face
160: pattern
Embodiment
Fig. 1 to Fig. 9 is the flow process generalized section according to the manufacture method of a kind of memory of one embodiment of the invention.
Please refer to Fig. 1, first, substrate 100 is provided, substrate 100 comprises memory cell areas 102 and external zones 104, a plurality of grids 110,120 in substrate 100, have been formed with, and on the sidewall of grid 110,120, there is the first clearance wall 112,122, wherein between the grid 110 of memory cell areas 102, there are a plurality of the first openings 114.Substrate 100 is for example semiconductor base, as the silicon base of N-type or P type, San Wu family semiconductor base etc.The material of grid 110,120 is for example doped polycrystalline silicon, and the material of the first clearance wall 112,122 is for example silicon nitride.
Please refer to Fig. 2, then, in substrate 100, form the first material layer 130, the first material layers 130 and cover memory cell areas 102 and external zones 104, and the first material layer 130 fills up opening 114.The first material layer 130 is for example polysilicon layer, and its formation method is for example chemical vapour deposition technique.In the present embodiment, this step also comprises the first material layer 130 is carried out such as flatening process such as chemical mechanical milling techs (chemical mechanical polishing, CMP).
Please refer to Fig. 3, then, remove the first material layer 130 that covers external zones 104, to expose external zones 104.The method that removes the first material layer 130 is for example reactive ion-etching (reactive ion etch, RIE).
Please refer to Fig. 4, then, on the first clearance wall 122 of the grid 120 of external zones 104, form the second clearance wall 124.The formation method of the second clearance wall 124 is such as be the first spacer material layer (not shown) that form with methods such as chemical vapour deposition techniques in substrate 100, carry out again afterwards anisotropic etching process and remove part spacer material layer, to form clearance wall structure on the first clearance wall 122.Wherein, the material of the second clearance wall 124 is for example silicon nitride, and removing part spacer material layer is for example reactive ion-etching to form the method for the second clearance wall 124.
Then, be for example that to take the second clearance wall 124 be mask, carry out an implantation technique, so that 104 grid 120 both sides form source electrode and drain regions 126 in external zones.Special one carries, and after grid 120 both sides of external zones 104 form source electrodes and drain region 126, can remove or not remove the second clearance wall 124, is that not remove the second clearance wall 124 be example in the present embodiment.In other words, the step that removes the second clearance wall 124 is actually optional step.
Special one carry be, compared to known technology, when forming the second clearance wall, can spacer material be inserted to the opening between the grid of memory cell areas simultaneously, or together with time shift, remove the spacer material layer in opening when removing the second clearance wall, in the present embodiment, grid 110 and the first clearance wall 112 due to the first material layer 130 meeting covering protection memory cell areas 102, therefore the formation of the second clearance wall 124 or remove technique (comprising the techniques such as deposition or etching) and can not damage the grid 110 of memory cell areas 102 or the first clearance wall 112, the structure that the first clearance wall 112 of memory cell areas 102 can be remained intact.In other words, the first material layer 130 is applicable to protect the destruction that any treatment process that memory cell areas 102 avoids being subject to carrying out external zones 104 may cause.
Please refer to Fig. 5, then, in substrate 100, form a barrier layer 140, to cover the first material layer 130 of memory cell areas 102 and the grid 120 of external zones 104.In the present embodiment, barrier layer 140 is for example the surface of grid 120, the first clearance wall 122 and the second clearance wall 124 and the first material layer 130 of memory cell areas 102 that covers external zones 104.
Then, in the substrate 100 of external zones 104, form one second material layer 150, to cover the barrier layer 140 on the grid 120 of external zones 104.In the present embodiment, the second material layer 150 is for example to comprise boric acid silex glass or silica, and its formation method is for example chemical vapour deposition technique.In the present embodiment, this step is for example prior to form one second material layer that covers external zones 104 and memory cell areas 102 on substrate 100 comprehensively, the barrier layer 140 of then usining on the first material layer 130 is as etch stop layer, the second material layer is carried out to flatening process, make the end face 150a of the second material layer 150 and the end face of barrier layer 140 rough equate and essence at grade upper.Wherein, flatening process is for example to comprise a chemical mechanical milling tech.
In general, if do not form barrier layer 140 on the first material layer 130 of memory cell areas 102, when the second material layer 150 is carried out to flatening process, can using the top of the first material layer 130 as etch stop layer.Thus, may there is overetched problem in the second material layer 150, and may cause the first material layer 130 to have surface dimple phenomenon.Yet, in the present embodiment, on the first material layer 130 due to memory cell areas 102, be coated with barrier layer 140, therefore when the second material layer 150 is carried out to flatening process, the barrier layer 140 that can using on the first material layer 130 is as etch stop layer, and because barrier layer 140 has higher density conventionally, therefore can avoid the second material layer 150 and the first material layer 130 that the problems referred to above occur.
Please refer to Fig. 6, then, remove the barrier layer 140 of the first material layer 130 that covers memory cell areas 102.The method that removes part barrier layer 140 is for example dry etch process.
Then, remove part the first material layer 130, to form a plurality of the second openings 132.In the present embodiment, the method that removes part the first material layer 130 comprises reactive ion-etching.Special one carry be; in the present embodiment; in forming the step of the second opening 132; because the region of external zones 104 is entirely by the second material layer 150 covering protections; therefore selecting in order to remove on the etching condition of part the first material layer 130 whether can hurt external zones 104 without taking into account; and can remove part the first material layer 130 with etching condition preferably, with obtain thering is vertically profiling second opening 132 of (vertical profile).For instance, in the selection of etchant, need not consider whether used etchant has high selection etching ratio for the first material layer 130 and grid 120, and can only with regard to obtaining the viewpoint of the opening with preferred profile, select.
Please refer to Fig. 7, then, in each second opening 132, form one first pattern 160.The material of the first pattern 160 is for example to comprise boron-phosphorosilicate glass or silica, with and forming method thereof be for example chemical vapor deposition method.
Please refer to Fig. 8, then, remove remaining the first material layer 130, to form a plurality of contact windows 134 in memory cell areas 102.The method that removes the first material layer 130 is for example dry etching method or wet etching.Then, remove a part for the second material layer 150 that is positioned at external zones 104, with the 104 formation contact windows 135 in external zones, wherein contact window 135 exposes source electrode and drain regions 126.The method that removes the second material layer 150 is for example dry etching method or wet etching.
Please refer to Fig. 9, then, in contact window 134,135, insert conductor material layer, to form contact window plug 136 between adjacent two first clearance walls 112, and 104 form contact window plugs 137 in external zones.The material of contact window plug 136,137 is for example tungsten, copper, aluminium or other suitable metals.
In the present embodiment; first with the first material layer 130 protection memory cell areas 102; be beneficial to external zones 104 to process (such as forming and removing the second clearance wall 124); the barrier layer 140 of usining again on the first material layer 130 is as the etch stop layer that forms the second material layer 150, to avoid the second material layer 150 to have overetched problem and the first material layer 130 to have the phenomenon of surface depression.Then, removing the first material layer 130 to form in the technique of the first pattern 160, because the second material layer 150 can be protected external zones 104, make the first pattern 160 there is preferably vertically profiling.In addition, because the first clearance wall 112 of memory cell areas 102 can be by the first material layer 130 coverings, therefore the first clearance wall 112 can not be subject to external zones 104 treatment process (such as the formation of the second clearance wall with remove) impact, and can provide good being electrically insulated for grid 110, and can between the first intact clearance wall 112 structures, form contact window plug 136.
In sum; in the manufacture method of memory of the present invention; with the first material layer and the second material layer, protect respectively the element of memory cell areas and external zones; therefore to external zones and memory cell areas, one of them deposit and during the processing such as etching; in external zones and memory cell areas wherein another can not come to harm, the structure that the gap wall energy on gate lateral wall is remained intact.In addition; when forming the second material layer; owing to being formed with barrier layer on the first material layer, therefore can protect the first material layer the problems such as depression can not occur because of the flatening process of the second material layer, be conducive to the follow-up pattern that defines contact window plug that forms in the first material layer.Particularly; forming in order to define in the step of pattern of contact window plug; because the grid of external zones is protected by the second layer of material covers; therefore without taking into account whether can hurt under the grid of external zones and the condition of clearance wall, select preferably etching mode, to obtain the pattern with preferred profile.Thus, the clearance wall of memory cell areas and external zones all has complete structure, therefore can between two adjacent clearance walls, form self-aligned contact hole, makes memory have good element characteristic.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention, any affiliated technical field technical staff, without departing from the spirit and scope of the present invention; when doing a little change and retouching, thus protection scope of the present invention when depending on the claim person of defining be as the criterion.
Claims (8)
1. the manufacture method of a memory, comprise step: provide a substrate, this substrate comprises a memory cell areas and an external zones, a plurality of grids in this substrate, have been formed with, and respectively on the sidewall of this grid, there is one first clearance wall, wherein between described a plurality of grids of this memory cell areas, there are a plurality of the first openings;
In this substrate of this memory cell areas, form one first material layer, described a plurality of grids of this this memory cell areas of the first layer of material covers and fill up described a plurality of the first opening; It is characterized in that, the manufacture method of described memory also comprises step:
In this substrate, form a barrier layer, to cover described a plurality of grids of this external zones and this first material layer of this memory cell areas;
In this substrate of this external zones, form one second material layer, to cover this barrier layer on described a plurality of grids of this external zones;
Remove this barrier layer that covers this first material layer;
Remove this first material layer of part, to form a plurality of the second openings, respectively this second opening is positioned on the top of respectively this grid of this memory cell areas;
In respectively forming one first pattern in this second opening;
Remove remaining this first material layer, to form a plurality of contact windows in this memory cell areas; And
In respectively forming a contact window plug in this contact window, wherein said a plurality of the first pattern arrangement are between described a plurality of contact window plugs.
2. the manufacture method of memory as claimed in claim 1, is characterized in that, this manufacture method also comprises step:
On this first clearance wall of respectively this grid of this external zones, form one second clearance wall; And
Described a plurality of the second clearance wall of take is mask, in respectively these grid both sides of this external zones, forms one source pole and drain region.
3. the manufacture method of memory as claimed in claim 2, is characterized in that, this barrier layer more covers described a plurality of the second clearance wall.
4. the manufacture method of memory as claimed in claim 1, is characterized in that, the material of this barrier layer comprises silicon nitride.
5. the manufacture method of memory as claimed in claim 1, is characterized in that, the step that forms this second material layer comprises:
In this substrate, form one second material layer comprehensively covering; And
This barrier layer of take on this first material layer is an etch stop layer, and this second material layer is carried out to a flatening process.
6. the manufacture method of memory as claimed in claim 1, is characterized in that, the material of this second material layer comprises boric acid silex glass or silica.
7. the manufacture method of memory as claimed in claim 1, is characterized in that, this first material layer comprises polysilicon.
8. the manufacture method of memory as claimed in claim 1, is characterized in that, the material of described the first pattern comprises boron-phosphorosilicate glass or silica.
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| CN201010621017.0A CN102543878B (en) | 2010-12-24 | 2010-12-24 | Manufacturing method of storage |
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| CN201010621017.0A CN102543878B (en) | 2010-12-24 | 2010-12-24 | Manufacturing method of storage |
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| CN102543878B true CN102543878B (en) | 2014-02-12 |
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| CN104716084B (en) * | 2013-12-12 | 2017-10-27 | 华邦电子股份有限公司 | The manufacture method of semiconductor element |
| DE102017120886B4 (en) * | 2017-08-01 | 2022-03-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated chip comprising gate structures with sidewall spacers and manufacturing method |
| US10263004B2 (en) | 2017-08-01 | 2019-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6455362B1 (en) * | 2000-08-22 | 2002-09-24 | Micron Technology, Inc. | Double LDD devices for improved dram refresh |
| TW511249B (en) * | 2000-09-18 | 2002-11-21 | Samsung Electronics Co Ltd | Semiconductor memory device and method for manufacturing the same |
| CN1855433A (en) * | 2005-04-21 | 2006-11-01 | 旺宏电子股份有限公司 | Production of memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100479604B1 (en) * | 2003-03-21 | 2005-03-31 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6455362B1 (en) * | 2000-08-22 | 2002-09-24 | Micron Technology, Inc. | Double LDD devices for improved dram refresh |
| TW511249B (en) * | 2000-09-18 | 2002-11-21 | Samsung Electronics Co Ltd | Semiconductor memory device and method for manufacturing the same |
| CN1855433A (en) * | 2005-04-21 | 2006-11-01 | 旺宏电子股份有限公司 | Production of memory |
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