TW200633006A - Methods for forming isolation films - Google Patents

Methods for forming isolation films

Info

Publication number
TW200633006A
TW200633006A TW094120981A TW94120981A TW200633006A TW 200633006 A TW200633006 A TW 200633006A TW 094120981 A TW094120981 A TW 094120981A TW 94120981 A TW94120981 A TW 94120981A TW 200633006 A TW200633006 A TW 200633006A
Authority
TW
Taiwan
Prior art keywords
film
forming
trench
entire surface
semiconductor substrate
Prior art date
Application number
TW094120981A
Other languages
Chinese (zh)
Other versions
TWI303079B (en
Inventor
Pil-Geun Song
Young-Jun Kim
Sang-Wook Park
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200633006A publication Critical patent/TW200633006A/en
Application granted granted Critical
Publication of TWI303079B publication Critical patent/TWI303079B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Abstract

A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a liner film on the entire surface including the trench, forming an insulating film for trench burial only within the trench, stripping the remaining liner film formed except for the inside of the trench and the patterned pad film formed below the liner film, forming a sacrificial film on the entire surface, and performing a polishing process on the entire surface in which the sacrificial film is formed until the semiconductor substrate of the active region is exposed, thereby forming the isolation film having no topology difference with the semiconductor substrate of the active region.
TW094120981A 2005-03-09 2005-06-23 Methods for forming isolation films TWI303079B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050019636A KR100590383B1 (en) 2005-03-09 2005-03-09 Method of forming a field oxide layer in semiconductor device

Publications (2)

Publication Number Publication Date
TW200633006A true TW200633006A (en) 2006-09-16
TWI303079B TWI303079B (en) 2008-11-11

Family

ID=36971565

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094120981A TWI303079B (en) 2005-03-09 2005-06-23 Methods for forming isolation films

Country Status (5)

Country Link
US (3) US7429520B2 (en)
JP (1) JP2006253624A (en)
KR (1) KR100590383B1 (en)
CN (1) CN1832124A (en)
TW (1) TWI303079B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4756926B2 (en) * 2005-06-17 2011-08-24 Ｏｋｉセミコンダクタ株式会社 Method for manufacturing element isolation structure
KR100700284B1 (en) * 2005-12-28 2007-03-26 동부일렉트로닉스 주식회사 Method of fabricating the trench isolation layer in semiconductor device
US8012846B2 (en) * 2006-08-04 2011-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structures and methods of fabricating isolation structures
DE102007008530B4 (en) * 2007-02-21 2015-11-12 Infineon Technologies Ag A method of manufacturing a nonvolatile memory device, a nonvolatile memory device, a memory card having a nonvolatile memory device, and an electrical device having a memory card
CN102814727B (en) * 2012-08-13 2015-05-06 无锡华润上华科技有限公司 Method for chemically and mechanically grinding shallow trench isolation structure
CN103855072B (en) * 2012-12-06 2016-08-17 中国科学院微电子研究所 Deng flat field oxidation isolation structure and forming method thereof
US9502499B2 (en) * 2015-02-13 2016-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure having multi-layered isolation trench structures
KR20180068229A (en) * 2016-12-13 2018-06-21 삼성전자주식회사 Semiconductor device and method for fabricating the same
CN110943033B (en) * 2018-09-25 2022-04-26 长鑫存储技术有限公司 Preparation method of shallow trench isolation structure liner

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Publication number Priority date Publication date Assignee Title
US5273915A (en) * 1992-10-05 1993-12-28 Motorola, Inc. Method for fabricating bipolar junction and MOS transistors on SOI
JPH1187490A (en) * 1997-07-14 1999-03-30 Sony Corp Semiconductor device and its manufacture
US7235856B1 (en) * 1997-12-18 2007-06-26 Micron Technology, Inc. Trench isolation for semiconductor devices
KR100280107B1 (en) * 1998-05-07 2001-03-02 윤종용 How to form trench isolation
KR100322531B1 (en) * 1999-01-11 2002-03-18 윤종용 Method for Trench Isolation using a Dent free layer &Semiconductor Device thereof
JP3443358B2 (en) * 1999-03-24 2003-09-02 シャープ株式会社 Method for manufacturing semiconductor device
US6255194B1 (en) * 1999-06-03 2001-07-03 Samsung Electronics Co., Ltd. Trench isolation method
US6413828B1 (en) * 2000-03-08 2002-07-02 International Business Machines Corporation Process using poly-buffered STI
KR100386946B1 (en) * 2000-08-01 2003-06-09 삼성전자주식회사 Shallow trench isolation type semiconductor devices and method of forming it
US6348380B1 (en) * 2000-08-25 2002-02-19 Micron Technology, Inc. Use of dilute steam ambient for improvement of flash devices
JP2002270824A (en) * 2001-03-07 2002-09-20 Hitachi Ltd Method of manufacturing semiconductor integrated circuit device
US20020197823A1 (en) * 2001-05-18 2002-12-26 Yoo Jae-Yoon Isolation method for semiconductor device
KR100861290B1 (en) * 2002-07-08 2008-10-01 주식회사 하이닉스반도체 Method for forming isolation layer of semiconductor device
US6833322B2 (en) * 2002-10-17 2004-12-21 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film
JP2004179301A (en) * 2002-11-26 2004-06-24 Renesas Technology Corp Manufacturing method of semiconductor integrated circuit device
JP2004288965A (en) 2003-03-24 2004-10-14 Texas Instruments Inc Method to improve sti nano gap fill and moat nitride pull back
KR20050012652A (en) * 2003-07-26 2005-02-02 매그나칩 반도체 유한회사 Method for forming element isolation layer of semiconductor device

Also Published As

Publication number Publication date
US20080242046A1 (en) 2008-10-02
CN1832124A (en) 2006-09-13
TWI303079B (en) 2008-11-11
JP2006253624A (en) 2006-09-21
US20060205173A1 (en) 2006-09-14
US7429520B2 (en) 2008-09-30
US20080206955A1 (en) 2008-08-28
KR100590383B1 (en) 2006-06-19

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees