JPH0555102A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the influence of the proximity effect and form a fine precise resist pattern. CONSTITUTION:This method for manufacture consists of the following four processes: (1) Process to heap the first resist 2 on a substrate 1, (2) process to expose and develop the first resist 2 to form the first resist pattern 2a, (3) process to heap either resist of type, positive or negative, opposed to that of the first resist 2 or negative resist on the substrate 1 as the second resist 3, and (4) process to expose and develop the second resist 3 to form the second resist pattern 3a and then form a resist pattern 4a, the synthetic of the first resist pattern 2a and the second 3a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
In particular, it relates to a method of forming a resist pattern that reduces the proximity effect.

With the miniaturization of semiconductor devices, and also for the manufacture of devices utilizing the quantum effect, fine patterns are required, and so-called deep submicron patterning is required.

However, when the resist is exposed to light, if the pattern becomes fine, the influence of the proximity effect becomes large, so that it becomes difficult to form a fine resist pattern precisely.
Therefore, there is a demand for a method of forming a resist pattern having a precise shape with less proximity effect.

[0004]

2. Description of the Related Art Conventionally, in order to form a resist pattern, the resist deposited on the substrate was patterned by one exposure.

In such a method, interference between close patterns, that is, a so-called proximity effect occurs. The occurrence of the proximity effect in the conventional example will be described below. 7A and 7B are explanatory views of a conventional example, FIG. 7A is a diagram for explaining the occurrence of a proximity effect, FIG. 7B is a plan view of a resist pattern showing the effect of a proximity pattern, and FIG. It is a top view of a resist pattern showing a modification of a large-area pattern.

Referring to FIG. 7 (b), two resist patterns P which are to be provided separately from each other by a distance d _{0.
When 1 and} P ₂ are placed close to each other, refer to FIG.
The portion below the threshold value, which is the critical exposure amount for exposing the resist between two patterns, originally has the width d _{0 ,}
Since the fog areas that are inevitably exposed when the adjacent patterns are exposed overlap, the width d becomes smaller.

Therefore, as shown in FIG. 7B, the patterns are close to each other and the patterns are deformed. Further, in the pattern P _{3 having} a large area, referring to FIG. 7C, the resist near the periphery is exposed during the exposure of the inside of the pattern, and the deformed pattern P is generated.

In order to avoid such a proximity effect, a method of correcting the exposure amount and its distribution by a pattern, or a method of reducing the proximity effect by exposing only a thin layer with a multilayered resist has been devised.

However, the former method requires a large amount of complicated calculation and correction data based on experimental facts in charged beam exposure. Also, it is difficult to apply it to light and X-ray exposure, which are batch exposure.

Furthermore, the latter method has to go through complicated lithographic steps.

[0011]

As described above, the conventional resist pattern formation has a drawback that the pattern is deformed by the proximity effect.

A method for reducing the proximity effect is as follows.
It requires complicated procedures and many steps. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which avoids the influence of the proximity effect and forms a fine resist pattern in a precise shape.

[0013]

FIG. 1 is a process diagram of a first embodiment of the present invention, in which a resist pattern forming process is performed as shown in FIG.
1A to 1D are sectional views, and FIG. 1E is a plan view.

FIG. 3 is a process chart of the fourth embodiment of the present invention.
The plane and cross section of the resist pattern are shown. A first configuration of the present invention is directed to a semiconductor device including a step of developing a resist film exposed by light, X-rays or a charged beam to form a resist pattern 4a with reference to FIGS. In the manufacturing method, a step of depositing a first resist 2 on a substrate 1, a step of exposing the first resist 2 and then developing it to form a first resist pattern 2a, and then a positive type and a negative type A step of depositing one of a negative type resist and a negative type resist of the first resist 2 on the substrate 1 as a second resist 3, and then the second resist 3 is exposed and then developed to form a second resist pattern 3a, and the resist pattern 4a consisting of the first resist pattern 2a and the second resist pattern 3a is formed. And a second configuration, in the method of manufacturing a semiconductor device having the first configuration, the step of forming the first resist pattern 2a and the step of depositing the second resist 3. And a plurality of resist pattern forming steps including resist deposition, exposure and development.

[0015]

The operation of the structure of the present invention will be described with reference to FIGS. In the first configuration, first, for example, a negative first resist pattern 2a is formed through exposure and development.

During the development, the fog region 12 which is formed outside the exposure region 11 where the pattern is to be formed and causes the proximity effect is removed during the development. Then, a second resist is deposited, exposed and developed to form a second resist pattern.

Therefore, for example, when the negative second resist is exposed, since there is no fog region caused by the exposure of the first resist pattern, it overlaps with the fog region 12 caused by the exposure of the second resist pattern. Therefore, the fog region of these two exposures is not exposed twice.

Therefore, the proximity effect does not occur. Another function of the first configuration relates to prevention of deformation of a large area pattern. In this embodiment, first, only the outer periphery of the pattern is formed by the negative type first resist pattern 2a. After that, the second resist pattern 3a is formed by, for example, a negative resist so as to fill the inside of the pattern and not to extend outside the first resist pattern.

In the double exposure, the proximity effect due to the first exposure and the second exposure is not generated as in the previous example. In this example, the first resist pattern can be precisely patterned because the proximity effect can be avoided by making the first resist pattern a thin pattern that defines the outer periphery. On the other hand, the deformation due to the proximity effect due to the size of the area of the second resist pattern can usually be accommodated within the first resist pattern.

As a result, the resist pattern 4a, which is a combination of the first and second resist patterns, has the features of both the precise outer periphery of the first resist pattern and the large area of the second resist pattern. ..

Therefore, it is possible to form a precise resist pattern for a large area pattern while avoiding the proximity effect. In the above two examples, the first resist is a negative type and the second resist is a positive type, but the same effect can be obtained even if the second resist is a negative type. In this case, the first resist is doubly exposed, but since it is a negative type, overexposure does not affect the pattern shape at all.

When the first resist is a positive type, the second resist is a negative type. In this case, since there is a fog region in the positive resist pattern, if the second resist is too close to the second resist, the fog will be doubled when the second resist is exposed.

However, since the first resist pattern is usually post-baked, the sensitivity is lowered, and this effect rarely poses a problem. In addition, it is not preferable to make both the first and second resists positive because the first resist pattern is surely overexposed.

In the second structure of the present invention, two or more exposed and developed resist patterns are formed by using the same method as in the first structure, and these resist patterns are synthesized to form a desired resist pattern. It is a thing.

According to this structure, a complicated pattern, for example, a pattern in which three or more thin lines intersect, is formed as a precise pattern without proximity effect by forming resist patterns for each thin line separately. You can

[0026]

EXAMPLES Details of the present invention will be described with reference to examples. 1 to 3 are process charts of an embodiment of the present invention.
Fig. 3 shows a pattern consisting of two parallel thin lines (Fig. 1 (e)
It is the same pattern as. ) Is shown by a cross section.

In the first embodiment, referring to FIG.
First, a negative resist 2 for electron beam exposure is applied on the substrate 1 to a thickness of 600 nm and prebaked, and then a width of 0.6 μm is applied.
An EB exposure (electron beam exposure) device is used to perform drawing and exposure with an electron beam on a rectangular exposure region 11 having a length of m and a length of 10 μm.

Then, referring to FIG. 1B, the first resist pattern 2a is left in the exposed area 11 by ordinary development to remove the others, and post-baking is performed at 120 to 170.degree. By such post-baking, when a resist is applied over it, it is possible to prevent the previously formed resist pattern from being deformed or mixed.

Next, referring to FIG. 1C, a second resist 3 is applied and pre-baked, and then a rectangle having a width of 0.6 μm and a length of 10 μm is arranged in parallel with the first resist pattern at a distance of 0.3 μm. The exposure area 11 is exposed in the same manner as the first resist pattern.

Next, referring to FIG. 1D, the resist pattern 4a is completed through development and post-baking similar to the first resist pattern. The second embodiment is shown in FIG.
The same pattern as in (e) is formed by using the first resist as a negative type and the second resist as a positive type.

Referring to FIG. 2A, the first resist pattern 2a is formed on the substrate 1 in the same manner as in the first embodiment. Next, referring to FIG. 2B, a positive type second resist 3 is applied and pre-baked, and then an unexposed region 11b where the second resist pattern 3a is to be formed is left on the entire outer surface thereof. EB exposure.

Next, development and post-baking are performed to form a second resist pattern 3a, and a resist pattern 4a is formed.
To complete. In this example, the fog region 12 is generated in the second resist pattern 3a, but since it is not exposed and developed after that, it does not cause any trouble.

In this embodiment, particularly, the first resist pattern is exposed by drawing and the second resist pattern is collectively exposed.
For example, the effect of facilitating mask formation is achieved when light exposure is performed.

In the third embodiment, a pattern similar to that shown in FIG. 1E is formed by using the first resist as a positive type and the second resist as a negative type. First, referring to FIG.
After the positive type resist 2 is applied on the substrate 1 and prebaked, the other is exposed except the unexposed region 11b where the second resist pattern 3a is to be formed.

Next, referring to FIG. 3B, after development,
Post baking is performed to gradually raise the temperature to 170 to 230. This post-baking can prevent deformation and mixing during the next resist coating.

Next, referring to FIG. 3C, a negative type second resist 3 is applied and prebaked, and then the exposed region 1 is exposed.
1 is EB exposed. Next, the resist pattern 4a is completed through development and post baking.

4 to 5 are process charts of an embodiment of the present invention, in which the pattern forming process is shown by a plane and its CD cross section. In the fourth embodiment of the present invention, referring to FIG. 4 (a), a negative resist having a thickness of 600 nm applied on a substrate is EB-exposed into a rectangular frame having an outer shape of 20 × 30 μm and a width of 2 μm. The first resist pattern 2a is formed through development and post baking.

Next, referring to FIG. 4B, a negative type second resist 3 is applied, and subsequently, a rectangular exposure region having an outer edge in the first resist pattern is exposed. Next, referring to FIG. 4C, the second resist is developed and post-baked to form a second resist pattern, and the desired resist pattern is completed together with the first resist.

In this example, when the pattern area is small, EB
There is an advantage that the exposure drawing time is short. Further, as a modification of this example, the second resist can be a positive type. At this time, the exposed area and the non-exposed area of the second resist are reversed and exposed. In this modified example, when the ratio of the pattern area to the area of the substrate 1 is large, it is possible to reduce the drawing time of the EB exposure.

The fifth embodiment is formation of a pattern for forming a contact hole. First, referring to FIG. 5A, a rectangular frame-shaped first resist pattern having a width of 0.3 μm is formed along the outer edge of a contact hole having a size of 0.3 μm × 0.4 μm, for example.

Next, referring to FIG. 5B, a positive type second resist 3 is applied, and then a rectangular exposure region 11 having an outer edge in the first resist pattern is exposed. Then, the second resist is developed and post-baked to form a resist pattern 4a having an opening at a portion corresponding to the contact hole.

In this example, since the exposure area is limited to the opening and the peripheral edge thereof, there is an effect that the drawing for the exposure may be small. In the sixth embodiment, referring to FIG. 6 (a), a negative type first negative electrode having a pattern in which a circle having a diameter of 0.3 μm and a line having a width of 0.1 are provided on the substrate 1 is formed. The resist pattern 2a is formed by, for example, ion beam exposure.

Next, referring to FIG. 6B, a negative type second resist is applied, and then an exposure region having a diameter of 0.15 μm which is concentric with the circle is exposed by, for example, an ion beam.

Next, the second resist is developed and post-baked to form a small circular second resist pattern 3a which is concentric with the circle opened in the first resist pattern 2a.
Such a resist pattern can be applied, for example, to the manufacture of a device utilizing the quantum effect.

In the present example, since the contours of the outer circle and the inner circle are formed by separate exposures without interference, the width of the pattern on the opened circular ring should be narrower than the beam diameter at the time of exposure. You can That is, it is possible to form a resist pattern in which a fine line is opened beyond the original resolution of the exposure apparatus.

The effect is the same for all combinations of the types described above, regardless of the type of the resist. The present invention can be applied not only to ion beam and EB exposure, but also to light and X-ray exposure, or a combination thereof.

[0047]

According to the present invention, it is possible to avoid the influence of the proximity effect due to the fog during exposure, so that a fine resist pattern can be formed in a precise shape. Can contribute to improving the performance of semiconductor devices.

[Brief description of drawings]

FIG. 1 is a process chart of a first embodiment of the present invention.

FIG. 2 is a process chart of a second embodiment of the present invention.

FIG. 3 is a process chart of a third embodiment of the present invention.

FIG. 4 is a process chart of a fourth embodiment of the present invention.

FIG. 5 is a process chart of the fifth embodiment of the present invention.

FIG. 6 is a process chart of the sixth embodiment of the present invention.

FIG. 7 is an explanatory view of a conventional example.

[Explanation of reference numerals] 1 substrate 2 first resist 2a first resist pattern 3 second resist 3a second resist pattern 4a resist pattern 11 exposed region 11b non-exposed region 12 fog region P deformed pattern P ₁ , P ₂ pattern

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor device, which comprises the step of developing a resist film exposed by any of light, X-rays and charged beams to form a resist pattern (4a), the method comprising: A step of depositing a first resist (2), a step of exposing the first resist (2) and then developing it to form a first resist pattern (2a), and then a positive type and a negative type A step of depositing one of a resist opposite to the first resist (2) and a negative resist as the second resist (3) on the substrate (1); The second resist (3) is exposed and then developed to form a second resist pattern (3a), and the resist pattern (consisting of the first resist pattern (2a) and the second resist pattern (3a) ( Four The method of manufacturing a semiconductor device characterized by comprising the step of forming a). 2. The method of manufacturing a semiconductor device according to claim 1, wherein a resist layer is formed between the step of forming the first resist pattern (2a) and the step of depositing the second resist (3). A method of manufacturing a semiconductor device, comprising a plurality of resist pattern forming steps including deposition, exposure and development.