JPS6154629A - Forming process of photoresist pattern - Google Patents
Forming process of photoresist patternInfo
- Publication number
- JPS6154629A JPS6154629A JP59176202A JP17620284A JPS6154629A JP S6154629 A JPS6154629 A JP S6154629A JP 59176202 A JP59176202 A JP 59176202A JP 17620284 A JP17620284 A JP 17620284A JP S6154629 A JPS6154629 A JP S6154629A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- sio2
- film
- thick
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半導体装置の製造のためのフォト・リソグラフ
ィ一工程において厚いポジ型フォト・レジスト膜に対す
る微細なパターンの形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming a fine pattern on a thick positive photoresist film in a photolithography process for manufacturing semiconductor devices.
(従来の技術)
従来、半導体基板の表面に大きな段差がある場合や技工
、チング物とレジストとのエツチング速度があまり違わ
ないような工、チングを長時間にわたって施す必要のあ
る場合には厚いレジスト膜の形成が必要とされる。しか
しながら、フォト・リソグラフィ□−技術においてレジ
ストが厚くなるに従い形成可能なパターンの寸法が大き
くなり、微細なパターンが形成できないという欠点があ
った。つまシ、レジスト膜厚程度までしか解像力がない
と考えられていた。(Conventional technology) Conventionally, thick resists have been used when there is a large step on the surface of a semiconductor substrate, when the etching rate is not much different between the etching material and the resist, or when etching needs to be performed for a long time. Formation of a film is required. However, in the photolithography technique, as the resist becomes thicker, the size of the pattern that can be formed becomes larger, and there is a drawback that fine patterns cannot be formed. It was thought that the resolution was only up to the thickness of the resist film.
(発明が解決しようとする問題点)
本発明の目的は、厚いレジスト膜を用いながらも、膜厚
に比して微細なパターンを形成することができるポジ型
フォト・レジストパターンの形成方法を得ることにある
。(Problems to be Solved by the Invention) An object of the present invention is to provide a method for forming a positive photoresist pattern that can form a fine pattern compared to the film thickness even though a thick resist film is used. There is a particular thing.
(問題点を解決するための手段)
本発明によれば、まず半導体基板上に厚いポジ型フォト
・レジスト膜を形成した後、短時間の露光、現像を行い
、膜厚に比して小さな段差を形成する。しかる後、レジ
ストのドライエッチに対するマスク材の層をレジスト上
に形成するが、この際、マスク材の厚さを充分にとれば
1表面はフラットに形成される。次にレジストの上部が
露出する程度Kまでマスク材をエツチングし、最後にレ
ジスト凹部に残ったマスク材を利用して0!ガスによる
リアクティブイオンエツチング(RIE)によるドライ
エツチングを行う。この時実際のバターニングはレジス
トの薄い層に対して行われるので従来に比して解像力が
良いという特徴がある。(Means for Solving the Problems) According to the present invention, a thick positive photoresist film is first formed on a semiconductor substrate, and then exposed to light for a short time and developed, the step difference is small compared to the film thickness. form. Thereafter, a layer of mask material for dry etching of the resist is formed on the resist. At this time, if the mask material is sufficiently thick, one surface will be formed flat. Next, the mask material is etched to a degree K that exposes the upper part of the resist, and finally, the mask material remaining in the resist recesses is used to remove the 0! Dry etching is performed using reactive ion etching (RIE) using gas. At this time, the actual patterning is performed on a thin layer of resist, so it is characterized by better resolution than conventional methods.
(実施例) 次に1図面を用いて本発明全よフ詳細に説明する。(Example) Next, the present invention will be explained in detail with reference to one drawing.
第1図は半導体基板1上にフォト・レジスト2を厚く塗
布したものである。これ金レジスト2の下部が感光しな
い程度のわずかな光量で露光し。FIG. 1 shows a photoresist 2 coated thickly on a semiconductor substrate 1. In FIG. The gold resist 2 is exposed to such a small amount of light that the lower part thereof is not exposed.
現像すると第2図のようにレジスト2の上部のみがバタ
ーニングされる。これは入射した光はレジスト2の上部
で吸収されポリマーの切+−i’t−行うが。When developed, only the upper part of the resist 2 is patterned as shown in FIG. This is because the incident light is absorbed by the upper part of the resist 2 and cuts the polymer.
下部においては充分な光が到達せず、切断が不充分なた
めである。このようにしてレジスト2の上部に小さな段
差でパターン金形成した後、第3図のようにレジスト2
上にスピン塗布によってマスク材たとえば酸化膜3を形
成する。このとき酸化膜3の厚さ金大きくすれば流体的
な性質によって上部はフラットに形成される。さらにレ
ジスト2が焼き付きを起こさない程度に熱処理を行った
後。This is because sufficient light does not reach the lower part and the cutting is insufficient. After forming the gold pattern with small steps on the upper part of the resist 2 in this way, the resist 2
A mask material such as an oxide film 3 is formed thereon by spin coating. At this time, if the thickness of the oxide film 3 is increased, the upper part will be formed flat due to its fluid properties. After the resist 2 is further heat-treated to the extent that it does not cause burn-in.
第4図に示すように塗布酸化膜3をレジスト2の上端が
露出する程度までエツチングを行う。この際のエツチン
グはドライであっても、ウェットであってもかまわない
。この結果レジスト2の凹部のみに酸化膜3が残る。こ
の酸化膜3全マスクにして02ガスによるRIEドライ
エッチングによって、レジスト全エラテンブレ、第5図
の様な厚いレジスト膜に対するパターンを形成すること
ができる。As shown in FIG. 4, the applied oxide film 3 is etched to the extent that the upper end of the resist 2 is exposed. The etching at this time may be dry or wet. As a result, the oxide film 3 remains only in the recessed portions of the resist 2. By performing RIE dry etching with O2 gas using the entire oxide film 3 as a mask, it is possible to form a pattern for a thick resist film, such as a resist entire etching pattern, as shown in FIG.
(発明の効果)
このように1本発明によれば、厚いレジスト膜にも微細
なパターンが形成できる。(Effects of the Invention) As described above, according to the present invention, a fine pattern can be formed even in a thick resist film.
第1図乃至第5図は本発明の各工程に於ける断面図で、
第1図は半導体基板上に厚いポジ型フォト・レジスト膜
全形成した工程、第2図はレジストの上部のみをバター
ニングした工程、第3図は上部レジスト全バターニング
した後の基板上に塗布酸化膜を形成した工程、第4図は
塗布酸化膜のエツチングを行った工程、第5図は残った
酸化膜をマスクにしてレジストのドライエッチング全行
った工程を示したものである。
1・・・・・・半導体基板、2・・・・・・ポジ型フォ
ト・レジスト、3・・・・・・塗布酸化膜。
芽 1 国
東I 側Figures 1 to 5 are cross-sectional views at each step of the present invention.
Figure 1 shows the process in which a thick positive photoresist film is completely formed on the semiconductor substrate, Figure 2 shows the process in which only the upper part of the resist is buttered, and Figure 3 shows the process in which the upper resist is completely buttered and then coated on the substrate. FIG. 4 shows the step of forming an oxide film, the step of etching the applied oxide film, and FIG. 5 shows the step of completely dry etching the resist using the remaining oxide film as a mask. 1...Semiconductor substrate, 2...Positive photoresist, 3...Coated oxide film. Bud 1 Kunisaki I side
Claims (1)
トの厚さの一部を露光、現像してレジスト表面に小さな
段差を形成する工程と、該レジスト上に、ドライエッチ
に対するマスク材の層を形成する工程と、該マスク材の
層をレジスト段差の上部が露出するまでエッチングする
工程と、さらに残ったマスク材の層を利用して、レジス
トをドライエッチングによってエッチングする工程とを
含むことを特徴とするフォト・レジストパターンの形成
方法。A process of forming a thick positive photoresist, exposing and developing a portion of the thickness of the photoresist to form a small step on the resist surface, and forming a layer of masking material for dry etching on the resist. a step of etching the mask material layer until the upper part of the resist step is exposed; and a step of etching the resist by dry etching using the remaining mask material layer. A method for forming a photoresist pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59176202A JPS6154629A (en) | 1984-08-24 | 1984-08-24 | Forming process of photoresist pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59176202A JPS6154629A (en) | 1984-08-24 | 1984-08-24 | Forming process of photoresist pattern |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6154629A true JPS6154629A (en) | 1986-03-18 |
Family
ID=16009406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59176202A Pending JPS6154629A (en) | 1984-08-24 | 1984-08-24 | Forming process of photoresist pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6154629A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0304077A2 (en) * | 1987-08-20 | 1989-02-22 | Kabushiki Kaisha Toshiba | Method of forming a fine pattern |
-
1984
- 1984-08-24 JP JP59176202A patent/JPS6154629A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0304077A2 (en) * | 1987-08-20 | 1989-02-22 | Kabushiki Kaisha Toshiba | Method of forming a fine pattern |
JPS6450425A (en) * | 1987-08-20 | 1989-02-27 | Toshiba Corp | Formation of fine pattern |
US5032491A (en) * | 1987-08-20 | 1991-07-16 | Kabushiki Kaisha Toshiba | Method of forming a fine pattern |
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