JPS61107747A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a fine contact hole precisely by shaping the contact hole at the crossing section of an etching section in a first insulating film and a second etching section. CONSTITUTION:A resist pattern with an opening section along the longitudinal direction of a diffusion layer 23 is formed onto an oxide film 24. The insulating film 24 is removed selectively through etching while using the resist pattern as a mask, and the resist pattern is peeled. An insulating film 27 is shaped onto the whole surface. A resist pattern with an opening section in the direction orthogonal to the longitudinal direction of the diffusion layer 23 is formed onto the insulating film 27. The oxide films 24, 27 are removed through etching while employing the resist pattern as a mask to shape an approximately square contact hole 30. An Al layer is deposited onto the whole surface, and patterned to form an Al layer 31.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which formation of contact holes is improved.

[Technical background of the invention]

Conventionally, semiconductor devices have been manufactured as shown in FIGS. 13(a) to 13(C), for example.

That is, first, as shown in <a> of the same figure, a photoresist layer 4 is formed on a P-type semiconductor substrate 2 having an N'' type diffusion layer 1 on the surface with an insulating film 3 interposed therebetween.Subsequently, Photoetching (PEP) using a mask with openings of desired size
An opening 5 is formed in the photoresist layer 4 by a method (
(b) Illustrated in the same figure. Next, using the photoresist layer 4 as a mask, the insulating film 3 is etched to form a contact hole 6 (as shown in FIG. 3C).

[Problems with background technology]

However, according to the prior art, the contact hole 6
The photoresist layer 4 has an area equal to or several times larger than that of the photoresist layer 4.
It is difficult to form ultrafine contact holes because the light needed to open them is not available. That is, during exposure, light is irradiated from above the mask 7 as shown in FIG. 14, and the resist pattern 4 is obtained by development.
As shown in the figure, a portion of the corner of the opening 5 of the resist pattern 4 is rounded. Therefore, in the case of a resist pattern 4' having a small opening 5' as shown in FIG.
The opening 5' of the resist pattern 4' and thus a part of the corner of the contact hole are rounded, making it difficult to accurately form a fine contact hole.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can form fine contact holes with high accuracy.

[Summary of the invention]

The first invention of the present application includes a step of forming a first insulating film on a semiconductor substrate, a step of selectively etching and removing this insulating film, a step of forming a second insulating film on the entire surface, and a step of forming a second insulating film on the entire surface. The second insulating film is selectively etched away, and a contact hole is formed at the intersection of the etched part of the first insulating film and the second etched part. the amount of light that enters the entire pattern,
1. :The main idea is to compensate for the lack of light, especially in some corners, and to form fine contact holes.

The second invention of the present application includes a step of forming an insulating film on a semiconductor substrate, a step of forming a mask material other than a resist on the insulating film, a step of patterning the mask material, and a resist pattern having an opening. forming such that the intersection of the opening of the resist pattern and the opening of the mask material serves as a mask for forming a contact hole, and etching the insulating film using the mask material and the resist pattern as a mask. and a step of opening a contact hole, thereby achieving the same effect as the first invention of the present application.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Example 1 (1) First, an element isolation region 22 is formed on a P-type silicon substrate 21 using a selective oxidation method, and then arsenic is ion-implanted into the substrate 21, annealed at 1000° C. for 20 minutes, and N
A + type diffusion layer 23 was formed (as shown in FIGS. 1(a) and 1(b)). Here, FIG. 5(b) is a sectional view taken along the line BB in FIG. 1(a), and the same will be considered hereinafter. Subsequently, a first CVD silicon oxide film 24 having a thickness of 7,000 layers is formed on the entire surface (as shown in FIGS. 2(a) and 2(b)). Next, on this oxide film 24, a layer is formed in the longitudinal direction of the diffusion layer 24.

A first resist pattern 26 having an opening 25 along (arrow X) was formed (as shown in FIGS. 3(a) and 9(b) and FIG. 9). Here, cross-sectional views taken along lines AA and 8-B in FIG. 9 are shown in FIGS. 3(a) and 3(b), respectively. In FIG. 9, the @ area surrounded by the dotted line is the opening 25, and the dotted area is the area where the contact hole is to be formed. Thereafter, using the resist pattern 26 as a mask, the oxide film 24 is subjected to reactive ion etching (RiE).
After selectively etching and removing the resist pattern 26, the resist pattern 26 was peeled off (as shown in FIGS. 4(a) and 4(b)). Furthermore, a second CVD silicon oxide film 27 having a thickness of 7,000 wafers was formed over the entire surface (as shown in FIGS. 5(a) and 5(b)).

(21, Next, on the oxide film 27, a second resist pattern 29 having an opening 28 in a direction perpendicular to the longitudinal direction of the diffusion layer 23 (arrow X) is formed. (
a), (b) and FIG. 10).

Here, cross-sectional views taken along line AA and line BB in FIG. 10 are shown in FIGS. 6(a) and 6(b), respectively. In addition, in FIG. 10, the area within the dotted line is the opening 8. Next, using the two resist patterns as a mask, the oxidation process 11!
24 and 27 were etched away by RIE to form a substantially square contact hole 30. At this time, the etching time was set to an over-etching time of the time during which the diffusion layer 23 was exposed in the longitudinal direction of the diffusion layer 23 +20%. In addition,
The diffusion layer 23 perpendicular to the longitudinal direction of the diffusion layer 23 is also exposed. After that, the resist pattern 29 was peeled off (7th
Figures (a) and (b) shown). Next, after depositing, for example, an A2 layer on the entire surface, it is patterned to form an A2 wiring 31 connected to the diffusion layer 23 via the contact hole 3Q,
I want to manufacture a semiconductor device.
(Illustrated in Figure 1).

Here, cross-sectional views taken along line AA and line BB in FIG. 11 correspond to FIGS. 8(a) and 8(b), respectively.

In addition, in FIG. 11, the area within the dashed dot line is the A2 wiring 31.

Thus, according to the first embodiment, fine contact holes 30 can be formed. This will be explained with reference to FIG. That is, after selectively etching and removing the oxide film 24 using the first resist pattern 26 having an opening 25 along the longitudinal direction of the diffusion layer 23 as a mask, openings are formed in a direction perpendicular to the longitudinal direction of the diffusion layer 23. In order to selectively remove the oxide film 24, 27 by etching using the second resist pattern 29 having the pattern 28 as a mask, a contact hole 30 is formed.
Some of the corners are not rounded as in the conventional case.

Therefore, fine contact holes 30 can be formed.

Example 2 (1) First, as in Example 1, a P-type silicon substrate 2 is prepared.
An element isolation region 22 and an N+ type diffusion layer 23 are formed on the entire surface (as shown in FIGS.
A large first CVD silicon oxide film 24 was formed (as shown in FIGS. 18(a) and 18(b)). Next, the thickness is 7 on the entire surface.
I want to form two layers 41 for 000 people.
b) As shown).

Next, a first resist pattern 43 having an opening/portion 42 along the longitudinal direction (arrow X) of the diffusion layer 23 is formed on this second layer 41 as shown in FIGS. 20(a) and 20(b). and shown in Figure 26). Here, the lines AA and B- in FIG.
The cross-sectional views taken along line B are shown in FIGS. 20(a) and 20(b), respectively. In FIG. 26, the area surrounded by the dotted line is the opening 42, and the dotted area is the area where the contact hole is to be formed. Thereafter, using the resist pattern 43 as a mask, the AR1i41 was selectively etched away by RIE, and the resist pattern 43 was peeled off (as shown in FIGS. 21(a) and 21(b)).

(2) Next, a second layer 41 having an opening 4.4 perpendicular to the longitudinal direction (arrow X) of the diffusion layer 23 is placed on the second layer 41.
A resist pattern 45 was formed (FIG. 22(a),
(b) and illustrated in Figure 27). Here, A-A in FIG.
22(a) and 22(a), respectively.
b). Note that the intersections between the openings 44 of the resist pattern 45 and the openings of the Aλ layer 41 serve as masks for forming contact holes, which will be described later. Further, in FIG. 27, the area within the dotted line is the opening 44. Next, using the second layer 41 and the resist pattern 45 as a mask, the oxide film 24 is selectively etched away by RIE to form a substantially square contact hole 46.
Figures 3 (a) and (b) shown). Next, the A2 layer 41 and the resist pattern 45 were removed using a mixed solution of sulfuric acid and hydrogen peroxide (as shown in FIGS. 24(a) and 24(b)). Thereafter, an An layer was deposited on the entire surface and patterned to form an A° C. wiring 47 connected to the diffusion layer 23 through a contact hole 46 (see FIGS. 25(a) and 28(b)).
(Illustrated) Here, cross-sectional views taken along line AA and line BB in FIG. 28 are shown in FIGS. 25(a) and 25(b), respectively. Second
In FIG. 7, the one-dot chain line A° C. wiring 47 is shown.

According to the second embodiment, the contact hole 46 is located at the intersection of the opening of the Aλ layer 41 and the opening 44 of the resist pattern 45 as shown in FIG. 46 can be formed. In addition, in the first embodiment, the oxide film is etched away by RIE using the first and second resist patterns as masks, which causes damage to the diffusion layer and thinning of the element isolation region, whereas in the second embodiment, the oxide film is etched away by RIE. , mask (A°C, resist)
Since contact holes are formed by etching the oxide film through the etching process, damage to the diffusion layer and reduction in film thickness in the element isolation region can be reduced compared to the first embodiment.

In the above embodiment, the contact hole is formed at a position corresponding to the diffusion layer on the surface of the root. Alternatively, a contact hole may be provided at a position corresponding to the wiring layer.

In the above embodiment, the case where the contact hole has a substantially square shape has been described, but the present invention is not limited to this, and can be similarly applied to a case where the contact hole is rectangular, for example. However, in this case, in order to avoid disconnection of the An layer formed in the contact hole, the etching that determines the long side of the contact hole is performed using the second C
It is preferable to etch the VD silicon oxide film.

In the above Example 2, AJ2 layers were used as the mask material, but the mask material is not limited to this, and may be, for example, a molybdenum layer, a tungsten layer, or the like.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device in which fine contact holes can be formed with high precision and the degree of integration can be improved thereby.

[Brief explanation of the drawing]

1 to 8 are cross-sectional views showing the manufacturing method of a semiconductor device according to Example 1 of the present invention in order of steps, FIG. 9 is a plan view of FIG. 3, FIG. 1o is a plan view of FIG. 6, 11 is a plan view of FIG. 8, FIG. 12 is a plan view for explaining the effects of Example 1, and FIGS. 13(a) to (C) show a conventional semiconductor device manufacturing method in order of steps. A cross-sectional view, FIG. 14 is a diagram for explaining the principle of exposure, FIGS. 15 and 16 are diagrams for explaining the drawbacks of the prior art, respectively, and FIGS. 17 to 25 are diagrams for Embodiment 2. A cross-section (
26 is a plan view of FIG. 20, FIG. 27 is a plan view of FIG. 22, FIG. 28 is a plan view of FIG. 25, and FIG. 29 is a plan view for explaining the effect of the second embodiment. It is a diagram. 21...P-type silicon substrate, 22...Element valve I@
area, 23...N+ type diffusion layer, 24.27...CV
D silicon oxide film, 25.28.42.44... opening, 26.29.43.45... resist pattern,
30.46...Contact hole, 31.41.47
...A2 layer.

Claims (4)

[Claims] (1) A step of forming a first insulating film on a semiconductor substrate, a step of selectively etching away this insulating film, a step of forming a second insulating film on the entire surface, and a step of forming a second insulating film on the entire surface. A method for manufacturing a semiconductor device, comprising the step of selectively etching away a film and forming a contact hole at an intersection of an etched portion of the first insulating film and a second etched portion. (2) Manufacturing a semiconductor device according to claim 1, wherein the contact hole has a rectangular shape, and the etching to determine the long side of the contact hole is performed by etching the second insulating film. Method. (3) The semiconductor device according to claim 1, wherein the etching of the side of the contact hole parallel to the length direction of the wiring above the contact hole is performed by etching the second insulating film. Production method. (4) a step of forming an insulating film on the semiconductor substrate; a step of forming a mask material other than resist on the insulating film;
a step of patterning this mask material; a step of forming a resist pattern having an opening so that the intersection of the opening of the resist pattern and the opening of the mask material serves as a mask for forming a contact hole; A method for manufacturing a semiconductor device, comprising the step of etching the insulating film using the mask material and the resist pattern as a mask to open a contact hole.