JPS5815934B2 - How to use hand tools - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a fine pattern such as a super high frequency transistor.

Semiconductor devices such as transistors and integrated circuit ICs are manufactured by selective diffusion, that is, by forming openings at predetermined positions in the silicon oxide film, since the silicon oxide film has the effect of preventing impurities from diffusing into the silicon semiconductor substrate. It was common to manufacture semiconductor devices by diffusing specific impurities into the semiconductor substrate through the openings.

The diffusion is performed multiple times to form, for example, a base region and an emitter region, and an opening of a different size must be formed in the silicon oxide film each time. Since the positions of the two are also different, an alignment operation must be performed to form the opening.

Furthermore, since a silicon oxide film is formed on the semiconductor substrate by performing the diffusion process, openings for providing electrodes must also be formed.

Normally, to form an opening in a silicon oxide film, a photoresist is applied, a desired pattern is exposed, and then the silicon oxide film is etched using a photoresist mask.

In this case, the positioning of the opening is performed by relative alignment between the exposure mask and the semiconductor substrate, and high precision is required.

In particular, when a transistor has a fine pattern such as an ultra-high frequency transistor, even higher accuracy is required in the positioning operation, making the operation extremely difficult.

If an opening with poor alignment is formed, a fatal defect will occur in the function of the semiconductor device.

The present invention is a novel invention that improves the above-mentioned conventional drawbacks, and its purpose is to facilitate the mask alignment operation, form fine pattern openings without being limited to the mask pattern, and An object of the present invention is to provide a method for manufacturing a semiconductor device with improved high frequency characteristics.

In order to achieve the object, the method for manufacturing a semiconductor device of the present invention includes a step of forming a second diffusion layer in a first diffusion layer of a semiconductor substrate, in which an opening formed in the first diffusion layer is formed. forming first and second diffusion prevention coatings made of different materials in a pattern longer than the width of the opening for forming the second diffusion layer and wider than the width of the opening for forming the second diffusion layer; A highly conductive layer is formed by high-concentration diffusion from the first diffusion layer forming opening part of which is partially covered with a second layer diffusion prevention coating, and then the second diffusion prevention coating is used as a mask to form a highly conductive layer. The first layer diffusion prevention coating is etched from the side to leave the width of the second diffusion layer formation opening, and the first diffusion layer formation opening other than the remaining first layer diffusion prevention coating is etched. The method is characterized in that it includes a step of forming a diffusion prevention coating on the first layer, and then removing the diffusion prevention coating of the first and second layers to form a second diffusion layer forming opening. An example will be explained in detail.

FIG. 1a is an explanatory diagram of the manufacturing process of an embodiment of the present invention, and FIG. This figure shows what was formed by.

Specific impurities are diffused through this opening 3 to form a base region 4.

As a result of this diffusion process, a thin silicon oxide film is formed in the opening 3 as well, so it is removed using, for example, an etching solution containing hydrofluoric acid so that the opening 3 is exposed.

Figure 1 shows this state.

Next, a silicon nitride film 5 and a silicon oxide film 6 are formed over the entire surface of the semiconductor substrate 1 by a vapor phase growth method or the like.

FIG. 1C shows this state, in which the silicon nitride film 5 serves as the first layer of the diffusion barrier coating, and the silicon oxide film 6 serves as the second layer of the diffusion barrier coating.

Next, a silicon oxide film 6 is formed according to the pattern of the photomask.
Using the remaining silicon oxide film 6 as a mask, the silicon nitride film 5 is etched with, for example, an etching solution containing phosphoric acid to form openings 7 and 8.

FIG. 1d shows this state.

Impurities are diffused from these openings 7 and 8 in order to form highly conductive films 9 and 1o.

This impurity is of the same conductivity type as the base region 4, and in the case of an NPN transistor, a P-type impurity such as boron is diffused to form high conductivity layers 9 and 10.

FIG. 1e shows this state.

Next, the silicon nitride film 5 is etched from the sides using phosphoric acid using the silicon oxide film 6 as a mask.

In this case, the overetching layer is a highly conductive layer 9°10
Although it is determined by the diffusion depth of the first stage and the emitter diffusion depth of the subsequent stage, it is about 1 μm when the emitter junction is formed at a shallow place from the surface as in a super high frequency transistor.

Furthermore, since the opening is formed by removing the remaining silicon nitride film 5, the opening in that case is 1.
If a width of less than μ is required, etching is performed from the sides of the silicon nitride film 5 to control the width of the remaining silicon nitride film 50 to a desired opening dimension of less than 1 μ.

For example, hydrofluoric acid has a high etching rate for silicon oxide films, and phosphoric acid has a high etching rate for silicon nitride films, so the above-mentioned etching can be performed by combining the respective etching solutions.
The ratio of each etching speed is 10=1 to 100:1
It is also possible to

FIG. 1f shows the state at the end of the above-mentioned process.

Next, a silicon oxide film 11 is formed on the surface of the semiconductor substrate 1 in an oxidizing atmosphere.

This process is generally called drive-in process.
Simultaneously with the growth of the silicon oxide film, diffusion of the base region 4 progresses, and an impurity redistribution layer 12 in the base region is formed.

FIG. 1g shows this state.

Next, the silicon oxide film 6 is removed by etching, and the silicon nitride film 5 is then removed by phosphoric acid, thereby forming an opening 13 for emitter diffusion as shown in Figure 1.

Emitter diffusion is performed through this opening 13 to form an emitter region 14.

A silicon oxide film 15 is formed by this diffusion process.

FIG. 1i shows this state.

Next, this silicon oxide film 15 is removed by etching to form an opening 13 again, and openings 16 and 17 are formed in the highly conductive layer 9.100 by photoetching.

FIG. 1j shows this state.

Next, when electrode metal is provided by vapor deposition or the like and predetermined patterning is performed, the electrodes 18, 19,
20 is formed, electrode 19 is an emitter electrode, electrode 18 .
20 is a base electrode.

In general, ultra-high frequency transistors are required to have the base high-conductivity layer and emitter junction close to each other in order to improve their characteristics, but conventional methods lack precision in alignment operations. Due to this, the degree of proximity was limited.

However, according to the method of the present invention as described above, there is an advantage that no positioning operation is required for photoetching the emitter diffusion opening, and furthermore, the amount of overetching between the base high conductivity layer and the emitter junction is reduced. Accordingly, they can be formed very closely together.

In addition, the photomask pattern, especially the fine pattern for forming the emitter opening of ultra-high frequency transistors, is
If the width is less than μ, it is difficult to make it with high precision due to limitations in photomask production, but as mentioned above, the etching mask can be used to prevent diffusion of the second layer using a photomask pattern that can be made. There is an advantage that openings of 1 μm or smaller can be formed with high accuracy by forming the first layer of diffusion-preventing film from the sides using the etching mask.

Further, in ultra-high frequency transistors, an emitter diffusion opening 21 is usually formed inside a base diffusion opening 20, as shown in FIG.

Note that 22 indicates an opening for the base electrode.

In this way, the length of the emitter diffusion opening 21 is shorter than the length of the base diffusion opening 20, and the degree of this shortness depends on the accuracy of the alignment operation in the photoetching process, and generally The distance from the edge of the base diffusion opening 20 to the edge of the emitter diffusion opening 21 is about 3 μm.

Therefore, although it is believed that making the shaded area as small as possible for high-frequency transistors will improve the high-frequency characteristics, in the conventional method, it is made sufficiently small due to the limitation due to the accuracy of the alignment operation. I couldn't.

Therefore, the present invention improves the characteristics by using the above-mentioned process and reducing the shaded area in FIG. 2 to almost zero.

The process will be explained below.

In the step shown in FIG. 1d, when alignment is performed using a photomask, a striped pattern 24 is formed across the base diffusion opening 23 as shown in FIG. 3g.
using a photomask.

Therefore, the positioning operation only needs to be performed on the left and right sides in FIG. 3g.

Further, as described above, this pattern 24 is used to form an opening for emitter diffusion, and the width of the pan 724 is made larger than the width of the opening to be formed by the amount of etching from the side. Therefore, the production of a photomask becomes easy even though a fine pattern is formed on a semiconductor substrate.

Figures 3g, 4g, and 5g are top views, and A
- The direction parallel to the A line is the width, and the direction parallel to the B-B line is the length.

As shown in FIG. 3, which is a cross-sectional view taken along the line A--A in FIG. A pattern consisting of a silicon oxide film 27 and a silicon oxide film 27 is formed.

FIG. 3C is a cross-sectional view taken along line BB in FIG. 3G, and the pattern is formed longer than the length of the opening 23. FIG.

Next, as shown in Figure 1 eK, a high conductivity layer is formed, and then a first
As shown in FIG. f, the first layer silicon nitride film is etched from the sides.

That is, Figure 4g. As shown in b and c, silicon oxide film 2
Over-etching is performed by etching the silicon nitride film 26 from the sides using 7 as a mask so that the width of the remaining silicon nitride film 26 becomes the width of the desired emitter diffusion opening.

Next, as shown in FIG. 1g, a drive-in process is performed to form a silicon oxide film in the base diffusion opening 23, and then the silicon oxide film 27 and the silicon nitride film 26 are removed.

As a result, an emitter diffusion opening 28 is formed as shown in FIG. 5g, and its length is equal to that of the base diffusion opening 28.
It has a full length in the direction parallel to the 0B-B line.

When impurities are diffused through this emitter diffusion opening 28 and the silicon oxide film formed at that time is removed,
The configuration shown in FIG. 5c is obtained.

The lines A-A and B in Figure 5g are shown in Figure 5.
This corresponds to a cross section taken along line -B, where b is a semiconductor substrate, 29 is a base region, and 30 is an emitter region.

Next, as shown in FIG. 1j, a base electrode opening is formed. In FIG. 6, if the region 31 is the base diffusion opening, 32 is the emitter electrode opening, and 33 is the base This becomes the electrode opening.

Next, as explained with respect to FIG. 1k, the opening 32.3
3 is provided with an electrode.

As explained above, the semiconductor device, especially the ultra-high frequency transistor, manufactured by the manufacturing method of the present invention has an emitter width of 1
μ or less, the emitter junction and the base high conductivity layer can be formed in close proximity, and the emitter region can be formed to have approximately the same length as the base region, so that high frequency Not only can the noise figure in the high frequency range be improved, but also the power gain in the high frequency range can be significantly improved.

Furthermore, in the case of high frequency, high output transistors, it is possible to significantly improve power gain and output power.

In addition, in the manufacturing process, there is no need for alignment operations to form openings in fine patterns of 1μ or less, and there is no need to prepare photomasks for the fine patterns, making manufacturing easier. There are some advantages.

In addition, in the step before forming the openings of the fine pattern, the alignment operation for patterning the second layer diffusion prevention coating is a stripe-like pattern, so the alignment operation in the longitudinal direction is performed. Since accuracy is not required for the lateral positioning operation, only accuracy is required for the horizontal alignment operation.
The alignment operation is easier than in the conventional example.

The striped pattern allows the emitter diffusion opening to be formed to cover the entire length of the base diffusion opening, so the area of the base region required for arranging the emitter can be reduced compared to the conventional example. , the characteristics can be improved as described above.

The reduction rate of the area is, for example, up to 1/1 compared to the conventional example.
I was able to make it to 3.

It should be noted that the first layer of silicon nitride film and the second layer of silicon oxide film may be other diffusion blocking films having different etching rates, or may be used for ultra-high frequency silicon planar transistors as in the embodiment. Of course, the present invention can be applied not only to the manufacture of semiconductor devices having other fine patterns, but also to the manufacture of semiconductor devices having other fine patterns.

[Brief explanation of drawings]

Fig. 1a- is an explanatory diagram of the manufacturing process of the embodiment of the present invention;
The figure is an explanatory diagram of the aperture of a conventional ultra-high frequency transistor.
Figure 3 a, b, c, Figure 4 a, b. C1 Figures 5a, b, and c are explanatory diagrams of the manufacturing process of the embodiment of the present invention, and each figure and c are cross-sectional views taken along the line A-A and line B-B of each figure a, and Figure 6 2 is an explanatory diagram of an opening in an embodiment of the present invention corresponding to FIG. 2; FIG. 1.25 is a silicon diffusion layer, 2 is a silicon oxide film, 4 is a base diffusion layer, 5 and 26 are silicon nitride films, 6 and 27 are silicon oxide films, 9 and 10 are high conductivity layers, and 11 is formed by drive-in processing. Formed silicon oxide film, 13.28
is an opening for emitter diffusion, and 14.30 is an emitter region.

Claims (1)

[Claims] 1. In a method of forming an opposite conductivity type region in a semiconductor substrate having one conductivity type and further forming a one conductivity type region within the opposite conductivity type region, the opposite conductivity type region is formed in the semiconductor substrate having one conductivity type. Next, a first insulating film is formed on the opposite conductivity type region, and a second insulating film is formed on the first insulating film and is etched at a different rate with the same etching solution than the first insulating film. forming a double insulating film that is longer than the length of the opening for forming the opposite conductivity type region and wider than the width of the opening for forming the - conductivity type region; using as a mask, introducing an impurity of the same conductivity type as the opposite conductivity type region into the opposite conductivity type region, then side etching the first insulating film to narrow its width, and then removing the first insulating film. Forming a third insulating film on the surface of the semiconductor substrate as a mask and redistributing impurities forming the opposite conductivity type region, then removing the first insulating film to select the surface of the opposite conductivity type region. 1. A method for manufacturing a semiconductor device, comprising a step of exposing the semiconductor device to the outside.