JPS62273773A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62273773A JPS62273773A JP11467786A JP11467786A JPS62273773A JP S62273773 A JPS62273773 A JP S62273773A JP 11467786 A JP11467786 A JP 11467786A JP 11467786 A JP11467786 A JP 11467786A JP S62273773 A JPS62273773 A JP S62273773A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- polycrystalline silicon
- deposited
- resist pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 239000010410 layer Substances 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000001459 lithography Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔発明の目的〕
（産業上の利用分野）
本発明は、半導体装置の製造方法、特に微細かつ高性能
な絶縁ゲート型電界効果トランジスタを含む半導体装置
の製造方法に関する。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, including a fine and high-performance insulated gate field effect transistor. The present invention relates to a method for manufacturing a semiconductor device.
（従来の技術）
近年、半導体装置の小形化及び高集積化がはかられ、い
わゆる集積回路（■ｅ）’ｓ大規模集積回路（ＬＳＩ）
、車には超ＬＳＩが市場に登場している。しかしながら
リソグラフィーの制限の為に微細化に限界を生じる。(Prior art) In recent years, semiconductor devices have become smaller and more highly integrated, and so-called integrated circuits (■e)'s large-scale integrated circuits (LSI) have been developed.
, super LSIs have appeared on the market for cars. However, there are limits to miniaturization due to lithography limitations.
（発明が解決しようとする問題点）
本発明は、このような事情に鑑みなされたもので、絶縁
ゲート型電界効果（ＭＯＳ）トランジスタの製造におい
てリソグラフィー技術の制限を受けずに微細化できる半
導体装置の製造方法を提供することを目的とする。(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and provides a semiconductor device that can be miniaturized without being subject to the limitations of lithography technology in the production of insulated gate field effect (MOS) transistors. The purpose is to provide a manufacturing method for.
（問題点を解決するための手段）
本発明は、半導体基板表面に第１の絶縁膜および多結晶
シリコン膜を堆積させ、レジストパターンをマスクに前
記多結晶シリコン膜および第１の絶縁膜をエツチングし
、レジストを除去した後、全面に第２の絶縁膜を形成す
る。次に前記第２の絶縁膜を異方性エツチングすること
により、素子形成領域の側壁に第２の絶縁膜を残存する
ことにより、マスク寸法より微細なチャネル幅を有する
素子を実現できることを特徴とするものである。(Means for Solving the Problems) The present invention deposits a first insulating film and a polycrystalline silicon film on the surface of a semiconductor substrate, and etches the polycrystalline silicon film and first insulating film using a resist pattern as a mask. After removing the resist, a second insulating film is formed over the entire surface. Next, by anisotropically etching the second insulating film, the second insulating film remains on the sidewalls of the element formation region, thereby making it possible to realize an element having a channel width smaller than the mask dimension. It is something to do.
（作 用）
本発明によれば、リソグラフィー技術の限界からくるマ
スク最小寸法よりも微細な素子の形成を行うことができ
る。又、シールド板を備なえることにより外部ノイズを
チャネルに伝えにくいものができる。(Function) According to the present invention, it is possible to form elements that are finer than the minimum dimension of the mask due to the limitations of lithography technology. Furthermore, by providing a shield plate, it is possible to make it difficult for external noise to be transmitted to the channel.
（実施例）
第２図（ａ）、（ｅ）は１本発明の一実施例によるＭＯ
３型トランジスタの製造工程を示す断面図である。(Embodiment) FIGS. 2(a) and (e) show an MO according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of a type 3 transistor.
先ず、第２図（ａ）に示す如く、シリコン基板１に第１
の絶縁膜２を形成し、 更にＬＰＣＶＤ法により多結晶
シリコン膜３を堆積し、レジストパターン４を形成する
。次に第２図（ｂ）に示す如くレジストパターン４をマ
スクに、周知のりアクティブイオンエツチング法を用い
る多結晶シリコン膜３と第１の絶縁膜２をエツチングし
、レジストパターン４を除去する。次に第２図（Ｑ）に
示す如く、周知のＣＶＤ法でＣＶＤシリコン酸化膜５を
堆積させる。First, as shown in FIG. 2(a), a first
An insulating film 2 is formed, a polycrystalline silicon film 3 is further deposited by LPCVD, and a resist pattern 4 is formed. Next, as shown in FIG. 2(b), using the resist pattern 4 as a mask, the polycrystalline silicon film 3 and first insulating film 2 are etched using the well-known active ion etching method, and the resist pattern 4 is removed. Next, as shown in FIG. 2(Q), a CVD silicon oxide film 5 is deposited by a well-known CVD method.
そして、リアクティブエツチング法を用いて異方性エツ
チングすることにより、第２図（ｄ）に示す様に、素子
形成領域の側壁にシリコン酸化膜５を残存させる。（こ
の時、素子分離領域の第１の絶縁膜２は、多結晶シリコ
ン膜３がストッパーとなりエツチングはされない。）更
に、ゲート絶縁膜６を形成すると同時に、層間絶縁膜７
を形成する。Then, by performing anisotropic etching using a reactive etching method, the silicon oxide film 5 is left on the side walls of the element formation region, as shown in FIG. 2(d). (At this time, the first insulating film 2 in the element isolation region is not etched because the polycrystalline silicon film 3 serves as a stopper.) Furthermore, at the same time as the gate insulating film 6 is formed, the interlayer insulating film 7 is etched.
form.
そして、ゲート電極８を形成し、この後にイオン注入法
により拡散層９を形成した。続いて、周知の気相成長技
術を用いて第３の絶縁膜１０を形成した後（第２図（ｅ
））、ゲート電極８、及び拡散層９にコンタクトホール
を開孔し、導電膜１１を被着し、この導電膜１１をパタ
ーニングすることにより、ＭＯＳ トランジスタが完成
する（第１図）。尚、第２図は第１図のＡ−Ａ断面図で
あり、第３図は同Ｂ−Ｂ断面図である。Then, a gate electrode 8 was formed, and then a diffusion layer 9 was formed by ion implantation. Subsequently, after forming the third insulating film 10 using a well-known vapor phase growth technique (see FIG. 2(e)
)), a contact hole is opened in the gate electrode 8 and the diffusion layer 9, a conductive film 11 is deposited, and the conductive film 11 is patterned to complete a MOS transistor (FIG. 1). 2 is a sectional view taken along line AA in FIG. 1, and FIG. 3 is a sectional view taken along line BB in FIG.
こうしてこの実施例によれば、リソグラフィーの限界か
らくるマスク最小寸法よりも微細な素子の形成を行なう
ことができる。又、多結晶シリコン膜３がシールド板と
なり外部ノイズをチャネルに伝えにくい構造になってい
る。尚、本発明は上述した実施例に限定されるものでは
ない。Thus, according to this embodiment, it is possible to form elements that are finer than the minimum dimension of the mask due to the limitations of lithography. Furthermore, the polycrystalline silicon film 3 acts as a shield plate, making it difficult for external noise to be transmitted to the channel. Note that the present invention is not limited to the embodiments described above.
例えば、多結晶シリコン膜３と絶縁膜２をエツチングし
た後の側壁に残存させるものはＣｖＤシリコン酸化ｗＩ
５に限るものではな（Ｐｏ１ｙｓｉ＊その他の絶縁膜で
代替できる０以上、本発明はその要旨を逸脱しない範囲
で、種々変形して実施することができる。For example, what remains on the sidewalls after etching the polycrystalline silicon film 3 and the insulating film 2 is CvD silicon oxide wI.
The present invention is not limited to 5 (0 or more can be substituted with Polysi* or other insulating films), and the present invention can be implemented with various modifications without departing from the gist thereof.
本発明によれば微細な半導体装置が得られる。 According to the present invention, a fine semiconductor device can be obtained.
第１図は本発明の一実施例に係わるＭＯｓトラン、工
ジスタ製造工程を示す平面図、第２図は同実施例の各製
造工程を示す断面図、第３図は第１図のＢ−Ｂの断面図
である。
図において
１・・・シリコン基板、
２・・・第１の絶縁膜、
３・・・多結晶シリコン膜、
４・・・レジストパターン、
５・・・シリコン酸化膜（第２の絶縁膜）、６・・・ゲ
ート酸化膜、
７・・・層間絶縁膜、
８・・・ゲート電極、
９・・・拡散層、
１０・・・第３の絶縁膜、
１１・・・導電膜。
代理人 弁理士 則 近 憲 右
同 竹 花 喜久男
Ｂ
第１図
第２図（１）
第２図（コ）
第３図FIG. 1 is a plan view showing the manufacturing process of an MOs transformer and a resistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing each manufacturing process of the same embodiment, and FIG. FIG. In the figure, 1... silicon substrate, 2... first insulating film, 3... polycrystalline silicon film, 4... resist pattern, 5... silicon oxide film (second insulating film), 6... Gate oxide film, 7... Interlayer insulating film, 8... Gate electrode, 9... Diffusion layer, 10... Third insulating film, 11... Conductive film. Agent Patent Attorney Ken Nori Chika Kikuo Takehana B Figure 1 Figure 2 (1) Figure 2 (C) Figure 3
Claims (1)
膜を形成する工程と、該多結晶シリコン膜上にソース・
ドレインおよびチャネルとなるべき領域以外の部分をレ
ジストパターンで覆い露出した部分の前記多結晶シリコ
ン膜および第１の絶縁膜エッチングする工程と、前記レ
ジストを除去した後に全面に第２の絶縁膜を形成し更に
、該第２の絶縁膜を異方性エッチングすることにより前
記レジストパターンで定義された領域の周辺部側壁に該
第２の絶縁膜を残存させる工程と、熱酸化によりゲート
絶縁膜を形成すると同時に前記多結晶シリコン膜表面に
絶縁膜を形成する工程とを備えた絶縁ゲート型電界効果
トランジスタを含む半導体装置の製造方法。A step of forming a first insulating film and a polycrystalline silicon film on the surface of the semiconductor substrate, and a step of forming a source film on the polycrystalline silicon film.
A step of covering a portion other than the region to become a drain and a channel with a resist pattern and etching the exposed portion of the polycrystalline silicon film and the first insulating film, and forming a second insulating film on the entire surface after removing the resist. Furthermore, a step of anisotropically etching the second insulating film to leave the second insulating film on the peripheral sidewall of the region defined by the resist pattern, and forming a gate insulating film by thermal oxidation. and simultaneously forming an insulating film on the surface of the polycrystalline silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11467786A JPS62273773A (en) | 1986-05-21 | 1986-05-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11467786A JPS62273773A (en) | 1986-05-21 | 1986-05-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62273773A true JPS62273773A (en) | 1987-11-27 |
Family
ID=14643863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11467786A Pending JPS62273773A (en) | 1986-05-21 | 1986-05-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62273773A (en) |
-
1986
- 1986-05-21 JP JP11467786A patent/JPS62273773A/en active Pending
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