JPS62150885A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacity that hinders the microminiaturization of elements by forming a gate electrode, source, drain contact and source.drain electrodes with one mask pattern by self-aligning technique to eliminate the necessity of positioning margin between the patterns. CONSTITUTION:When a polycrystalline silicon film 5 is isotropically etched with a resist pattern 6 as a mask, the film 5 is sidewisely etched, and a region 7 becomes later source.drain contact. When an aluminum film 8 is removed together with the pattern 6 after the entire surface is further covered with the aluminum film 8, an aluminum film 8' remains only on a gate electrode. Then, with the films 5 and 8' as masks a nitride film 4 is etched, and source.drain 9 are formed by an ion implanting method or a thermal diffusing method. Further, a gate insulating film 3 of a source.drain contact 7 is removed by etching, and a tungsten film 10 is selectively deposited by a CVD method only on the contact 7 and the film 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including a fine and high-performance insulated gate field effect transistor.

[Technical background of the invention and its problems]

In recent years, semiconductor devices have become smaller and more highly integrated, so-called integrated circuits (ICs), large-scale integrated circuits (LSIs),
Furthermore, super LSIs are appearing on the market. However, in the conventional MO8 structure, the alignment of the gate electrode, source/drain contact hole, source/drain electrode, etc. is limited by alignment in the lithography process, so it is necessary to have alignment margin for each pattern. Therefore, there is a limit to miniaturization, and further problems arise, such as an increase in parasitic capacitance that impedes high-speed operation. In order to reduce these problems with miniaturization, self-line technology is essential.

[Purpose of the invention]

The present invention has been made in view of the shortcomings of the conventional methods described above, and is based on a novel self-line technology that enables miniaturization without being limited by lithography technology in the production of insulated gate field effect (MOS) transistors. The purpose is to provide a method for manufacturing the device.

[Summary of the invention]

In the present invention, after forming an insulating film for element isolation and a gate insulating film on the surface of a semiconductor substrate, a first insulating film and a polycrystalline silicon film are deposited, and the polycrystalline silicon film is isotropically deposited using a resist pattern as a mask. After etching, a first conductive film is formed on the entire surface by sputter deposition or the like, and the resist pattern is further removed, leaving the first conductive film only in the area where the gate electrode is to be formed. Next, using the polycrystalline silicon film and the first conductor m1FJ as a mask, the first insulating film and the gate insulating film in the contact hole forming part are anisotropically etched, and then impurities are introduced into the contact hole forming part, and the source - After forming a drain and removing the first conductive film, a high melting point metal is selectively deposited on the contact hole forming portion and the polycrystalline silicon film. next,
The high melting point metal is thermally reacted with the polycrystalline silicon film and the substrate silicon to form a silicide, and then a thermal oxide film is formed on the silicide surface layer using the first insulating film as a mask. Furthermore, after etching and removing the first insulating film that will become the gate region, a second conductive film made of polycrystalline silicon, aluminum, etc. is deposited and patterned to form the gate electrode. shall be.

〔Effect of the invention〕

According to the present invention, gate electrodes, source/drain contacts, and source/drain electrodes can be formed from a single mask pattern using self-line technology, so there is no need for alignment margins between patterns, and element miniaturization is facilitated. It is also possible to increase the speed of the device.

[Embodiments of the invention]

FIGS. 1(a) to 1(e) show an MO according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of an 8-type transistor.

First, as shown in FIG. 1(a), a silicon substrate 1 is subjected to an element isolation method to form an insulator If! for isolation between elements. 12 is formed, and then a nitride film 4 and a polycrystalline silicon film 5 are deposited by the zero-order LPCVD method to form a gate insulating film 3, and a resist pattern 6 is formed. Next, as shown in FIG. 1(b), the polycrystalline silicon film 5 is isotropically etched using the resist pattern 6 as a mask.

Here, side etching is performed on the polycrystalline silicon film 5, and this region 7 will later become a source/drain contact portion. Furthermore, AQm 8 is applied to the entire surface. At this time, the AQ film 8 is not deposited on the side etched portion 7. Next, as shown in FIG. 1(C), the resist pattern 6 is removed and at the same time the AQ film 8 deposited on the resist pattern is removed.
is removed, leaving Ajll[8' only on the gate electrode. Next, using the polycrystalline silicon film 5 and the AQ film 8' as masks, the nitride film 4 is etched using a well-known active ion method, and the source/drain 9 is formed by a well-known ion implantation method or thermal diffusion method. ΔQ
The film 8' is removed and tungsten 111 is deposited using the well-known CVD method.
10 is selectively deposited only on the source/drain tact portion 7° and the polycrystalline silicon film 5.

Then, as shown in FIG. 1(d), the tungsten film 10, the polycrystalline silicon film 5, and the silicon substrate 1 are thermally reacted to form a silicide film 11. Next, using the nitride film 4 as a mask, the surface layer of the silicide film 11 is thermally oxidized to form an interlayer insulating film 12. Further, as shown in FIG. 1(e), the nitride film 4', which will become the gate region, is etched using hot phosphoric acid or the like.

By forming the gate electrode 13, a MOS transistor is formed.

Thus, according to the above-described embodiment, since the goo electrode, the source/drain contact, and the source/drain electrode can be formed from one mask pattern using the self-line technology, there is no need for alignment margin between the patterns, and the device It is possible to significantly reduce the parasitic capacitance that has hindered miniaturization. still.

The invention is not limited to the embodiments described above. For example, the first conductive film is not limited to AN, but may also be Zn,
It can be replaced with a conductive film such as Pb or Sn. Also.

It is not limited to tungsten selectively deposited on source/drain contact areas and polycrystalline silicon films, but also on Mo.
, Tx + Nb HTa and other high melting point metals can be used instead. The present invention can be implemented with various modifications without departing from the spirit thereof.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) show an MO according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of an S transistor. In the figure, 1... silicon substrate, 2... insulating film for element isolation, 3... gate insulating film. 4.4'...Nitride film (first insulating film), 5...Polycrystalline silicon film, 6...Resist pattern. 7... Source/drain contact part, 8.8'...
・A2 film (first conductive film), 9... Source/drain, 10... Tungsten film (high melting point metal 1t!, 11
...Silicide film. 12-... Interlayer insulation IIkrIA, 13... Gate electrode. Agent Patent Attorney Noriyuki Chika Yudo Kikuo Takehana

Claims (1)

[Claims] A step of forming an insulating film for element isolation and a gate insulating film on a surface portion of the semiconductor substrate, and a step of depositing a first insulating film and a polycrystalline silicon film on the insulating film for element isolation and the gate insulating film. , forming a resist pattern on the polycrystalline silicon film, isotropically etching the polycrystalline silicon film, forming a first conductive film on the entire surface, and further removing the resist pattern to form a gate. a step of leaving the first conductive film only in the area where the electrode shape is to be formed, etching the first insulating film using the first conductive film and the polycrystalline silicon film as a mask, and then etching the gate insulating film. a step of forming a contact hole through the contact hole, a step of introducing an impurity into the substrate through the contact hole to form a source/drain, and then a step of forming the first
a step of selectively depositing a high melting point metal film on the contact hole forming portion and the polycrystalline silicon film; A step of thermally oxidizing the surface layer of the formed silicide, a step of etching the first insulating film existing in the gate region, and then depositing a second conductive film. A method for manufacturing a semiconductor device including an insulated gate field effect transistor, comprising a step of forming a gate electrode by patterning.