JP2000332130A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce resistances of the gate electrode, source, and drain of an MISFET(metal insulator semiconductor field-effect transistor) and, at the same time, to provide a manufacturing process by which various lines of products can be made easily. SOLUTION: Silicide layers 9 are formed on the surfaces of sources and drains (N+-type semiconductor areas 14 and p+-type semiconductor areas 15) while the top faces of gate electrodes 7 are covered with solicon oxide films and, after the silicon oxide films are removed, silicon nitride films 17 and silicon oxide films 18 are successively formed on the gate electrodes 7. Then contact holes 20 and 21 are formed on the sources and drains (n+-type semiconductor areas 14 and p+-type semiconductor areas 15) and, at the same time, contact holes 22 are formed on the gate electrodes 7 by using the self-alignment contact(SAC) technology.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a MISFET (Metal Insula
The present invention relates to a technology effective when applied to high integration of a semiconductor integrated circuit device having a tor semiconductor field effect transistor).

[0002]

2. Description of the Related Art MI formed by fine design rules
As a method of electrically connecting the source / drain of the SFET and the metal wiring, a silicon nitride film is formed on the upper surface and side surfaces of the gate electrode, and the silicon nitride film and an insulating film (silicon oxide film) formed thereon are formed. A self-aligned contact (Self Align contact) that forms a contact hole by dry etching using the difference in etching speed
Contact; SAC) technology is used (for example, Japanese Patent Application Laid-Open No. 9-252098).

In order to reduce the gate electrode resistance of a MISFET or to reduce the contact resistance between a source / drain and a metal wiring, a gate electrode, a source,
A salicide technique for forming a refractory metal silicide layer on the surface of the drain is used.

[0004]

In order to realize the above-mentioned self-aligned contact (SAC), it is necessary to cover the upper surfaces of the gate electrode, source and drain with a silicon nitride film. In this case, a refractory metal silicide layer cannot be formed on the surface of the gate electrode. Therefore, in order to reduce the gate electrode resistance or the contact resistance between the source / drain and the metal wiring, the gate electrode material is required. Need to be a laminated structure (polymetal) of polycrystalline silicon and a refractory metal, and a refractory metal silicide layer needs to be formed only on the source and drain surfaces.

However, the CVD method (particularly, plasma CVD)
The silicon nitride film formed by the method 1) is 1 × 10 ²² cm in the film.
^{Since a} silicon nitride film is formed on the upper surface of the gate electrode because it contains about ^-3 hydrogen, hydrogen in the silicon nitride film is released by heat treatment when forming a high melting point metal silicide layer on the source and drain surfaces. Then, it diffuses to the gate oxide film. Therefore, a part of the Si—O bond forming the gate oxide film is cut by hydrogen, and the trap density in the film increases, resulting in a variation in the threshold voltage (Vth) (N
egative Bias Temperature Instability (NBTI) occurs.

Therefore, the occurrence of the above-mentioned NBTI is prevented,
In addition, in order to realize SAC, a silicon oxide film must be interposed between the gate electrode and the silicon nitride film on the gate electrode so as to prevent direct contact therebetween. However, in this case, the upper surfaces of the source and drain are covered with the silicon nitride film, while the upper surface of the gate electrode is covered with the silicon oxide film and the silicon nitride film. This makes it impossible to form the contact hole above the gate electrode at the same time. That is, the contact hole above the source and the drain and the contact hole above the gate electrode have to be formed in separate steps using two photomasks, which causes a problem that the manufacturing cost increases.

An object of the present invention is to provide a technique for reducing the resistance of a gate electrode, a source, and a drain of a MISFET.

Another object of the present invention is to provide a technique for simplifying a manufacturing process of a semiconductor integrated circuit device constituted by MISFETs.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) A first conductive film is formed on a main surface of a semiconductor substrate, a first silicon oxide film is formed on the first conductive film, and then the first silicon oxide film and the first silicon oxide film are formed. Forming a gate electrode whose upper surface is covered with the first silicon oxide film by patterning a conductive film; (b) forming a source and a drain on the semiconductor substrate on both sides of the gate electrode, Forming a refractory metal film on the substrate, and then heat-treating the semiconductor substrate to form a refractory metal silicide layer on the source and drain surfaces; (c) forming the first refractory metal silicide layer on the gate electrode; Removing the silicon oxide film, forming a silicon nitride film on the semiconductor substrate, and then forming a second silicon oxide film on the silicon nitride film; A first contact hole is formed in a self-aligned manner with respect to the gate electrode above the source and the drain by dry etching using an etching rate difference between the silicon oxide film and the silicon nitride film. Forming a second contact hole;

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) A first conductive film is formed on a main surface of a semiconductor substrate, and then a first silicon oxide film is formed on the first conductive film, and then the first silicon oxide film and the first silicon oxide film are formed. Forming a gate electrode whose upper surface is covered with the first silicon oxide film by patterning a conductive film; (b) forming a source and a drain on the semiconductor substrate on both sides of the gate electrode, Forming a high melting point metal film on the substrate and then heat treating the semiconductor substrate to form a high melting point metal silicide layer on the source and drain surfaces; (c) forming a silicon nitride film on the semiconductor substrate Removing the silicon nitride film in a region where a second contact hole is to be formed in a later step after the formation; (d) a second silicon oxide film on the silicon nitride film After the formation, a first contact hole is formed above the source and drain by self-alignment with respect to the gate electrode by dry etching using an etching rate difference between the second silicon oxide film and the silicon nitride film. Forming the second contact hole on the gate electrode.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIGS. 1 to 10 show a method of manufacturing a CMOS gate array according to Embodiment 1 of the present invention.
Will be described in the order of the steps.

First, as shown in FIG. 1, an element isolation groove 2 is formed in a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of, for example, p-type single crystal silicon. In order to form the element isolation groove 2, the substrate 1 in the element isolation region is etched to form a groove, and then a silicon oxide film 3 is deposited on the substrate 1 including the inside of the groove by a CVD method. The surface is flattened by chemically and mechanically polishing the upper silicon oxide film 3.

Next, a p-type impurity (boron) and an n-type impurity (for example, phosphorus) are ion-implanted into the substrate 1 to form a p-type well 4 and an n-type well 5, and then the substrate 1 is subjected to steam oxidation. As a result, a gate oxide film 6 is formed on the surfaces of the p-type well 4 and the n-type well 5.

Next, as shown in FIG.
A gate electrode 7 is formed on the upper surface of the substrate. In order to form the gate electrode 7, for example, a low-resistance polycrystalline silicon film doped with phosphorus (P) is deposited on the gate oxide film 6 by a CVD method, and then a WN film and a W film are formed thereon by a sputtering method. Are deposited, and a silicon oxide film 8 is further deposited thereon by a CVD method, and then these films are patterned by dry etching using a photoresist film (not shown) as a mask. By forming the gate electrode 7 to have a laminated structure of a polycrystalline silicon film and a W film (polymetal), the sheet resistance can be reduced to about half as compared with the laminated structure of the polycrystalline silicon film and the W silicide film (polycide). Can be.

Next, an n-type impurity (phosphorous or arsenic) is ion-implanted into the p-type well 4 on both sides of the gate electrode 7 to thereby form the n ^- type semiconductor region 11 having a low impurity concentration.
Is formed, and a p-type impurity (boron) is ion-implanted into the n-type well 5 to form a p ^- type semiconductor region 12 having a low impurity concentration.

Next, as shown in FIG.
After depositing the silicon oxide film by the method D, the silicon oxide film is anisotropically etched to form a sidewall spacer 13 made of the silicon oxide film on the side wall of the gate electrode 7.

Next, an n ⁺ -type semiconductor region 14 (source, drain) having a high impurity concentration is formed by ion-implanting an n-type impurity (phosphorous or arsenic) into the p-type well 4. A p ⁺ type semiconductor region 15 (source, drain) having a high impurity concentration is formed by ion implantation of a type impurity (boron).

Next, after the surface of the substrate 1 has been cleaned, as shown in FIG.
After the substrate 1 and the Ti film 10 are reacted by heat treatment, as shown in FIG.
By removing 0 by wet etching, a silicide layer 9 made of Ti silicide is formed on the surfaces of the n ⁺ type semiconductor region 14 (source and drain) and the p ⁺ type semiconductor region 15 (source and drain). Through the steps so far, an n-channel MISFET Qn and a p-channel MISFET Qp having a gate electrode 7 having a polymetal structure in which a W film is laminated on a polycrystalline silicon film, and a source and a drain having a silicide structure are completed.

As described above, in this embodiment, the upper surface of the gate electrode 7 is covered with the silicon oxide film 8, and the source and drain ( Since the silicide layer 9 is formed on the surface of the n ⁺ -type semiconductor region 14 and the p ⁺ -type semiconductor region 15), the NBTI phenomenon does not occur due to the heat treatment for forming the silicide layer 9.
Further, since the W film constituting a part of the gate electrode 7 does not directly contact the Ti film 10 deposited on the W film, the W film and the Ti film 10 are heat-treated when the silicide layer 9 is formed.
The reaction with the film 10 does not occur, and an undesired high-resistance alloy is not generated at the interface between them. In addition, as the high melting point metal material for forming the silicide layer 9, in addition to the above-described Ti film 10, C
An o film or the like can also be used.

Next, as shown in FIG. 6, the gate electrode 7 is formed by dry etching using the photoresist film 16 as a mask.
7, the silicon nitride film 17 and the silicon oxide film 18 are deposited on the n-channel MISFET Qn and the p-channel MISFET Qp by the CVD method, as shown in FIG. The surface of the silicon oxide film 18 is flattened by using a mechanical polishing method or the like.

In the manufacturing process of the gate array, a large number of wafers for which the processes up to this point have been completed are prepared, and thereafter,
The MISFETs are connected in the following manner according to the type.

First, as shown in FIG. 8, the silicon oxide film 18 on the gate electrode 7, the n ⁺ type semiconductor region 14 and the p ⁺ type semiconductor region 15 is dry-etched using the photoresist film 19 as a mask. This etching is performed using a gas (for example, C ₄ F ₈ + Ar) that etches the silicon oxide film 18 with a high selectivity in order to prevent the silicon nitride film 17 under the silicon oxide film 18 from being shaved.

Next, as shown in FIG. 9, a contact hole 20 is formed on the n ⁺ type semiconductor region 14 by dry-etching the silicon nitride film 17 using the photoresist film 19 as a mask. ^A contact hole 21 is formed above the ⁺ type semiconductor region 15, and a contact hole 22 is formed above the gate electrode 7. This etching is a gas (for example, CF ₄ + CH) that etches the silicon nitride film 17 with a high selectivity in order to minimize the amount of the silicon oxide film 3 in the substrate 1 and the element isolation trench 2 that is shaved.
F ₃ + Ar). As a result, contact holes 20 and 21 having a diameter smaller than the space between the adjacent gate electrodes 7 and 7 are formed in a self-aligned manner (self-alignment) with the gate electrode 7.

Next, as shown in FIG. 10, after forming plugs 23 in the contact holes 20 to 22, wirings 24 to 29 are formed on the silicon oxide film 18. The plug 23 is formed, for example, by depositing a W film on the silicon oxide film 18 including the inside of the contact holes 20 to 22 by sputtering, and then polishing the W film on the silicon oxide film 18 by CMP. . The wirings 24 to 29 are formed, for example, by depositing a W film (or an Al alloy film) on the silicon oxide film 18 by a sputtering method and then performing dry etching using a photoresist film (not shown) as a mask. (Or an Al alloy film) by patterning.

(1) According to the present embodiment, the gate electrode 7, the source and the drain (the n ⁺ type semiconductor region 14) of the n-channel MISFET Qn and the gate electrode 7 and the source of the p-channel MISFET Qp constituting the gate array , The drain (p ⁺ -type semiconductor region 15) can be reduced in resistance, so that the operating speed of the n-channel MISFET Qn and the p-channel MISFET Qp is improved.

(2) According to the present embodiment, a self-aligned contact (SAC) can be realized, so that an n-channel MISFET Qn and a p-channel MISFE
The miniaturization of TQp can be promoted.

(3) According to the present embodiment, the n-channel MISFET Qn and the p-channel MISFET Q
The contact holes 20 to 21 for connecting p can be formed with one photomask.

(4) According to the above (1) to (3), a high-speed and large-scale CMOS gate array can be manufactured at low cost.

(Embodiment 2) FIGS. 11 to 1 show a method of manufacturing a CMOS gate array according to Embodiment 2 of the present invention.
6 will be described in the order of steps.

First, as shown in FIG. 11, a gate electrode 7 having a polymetal structure and a source and a drain having a silicide layer 9 formed on the surface are formed in the same manner as in the first embodiment (FIGS. 1 to 5). -Channel MISFET Qn
And a p-channel type MISFET Qp is formed.

Next, as shown in FIG. 12, the n-channel MISFET Qn and the p-channel MISFET Qp
After depositing a silicon nitride film 17 on top of
As shown in FIG. 13, the silicon nitride film 17 in a region where the contact hole 22 is to be formed (above the gate electrode 7) in a later step is removed by dry etching using the photoresist film 31 as a mask.

Next, after removing the photoresist film 31, as shown in FIG. 14, an n-channel MISFET is formed.
CV is provided on the top of the Qn and p channel type MISFETs Qp.
A silicon oxide film 18 is deposited by the method D, and subsequently the silicon oxide film 18 on the gate electrode 7, the n ⁺ type semiconductor region 14 and the p ⁺ type semiconductor region 15 is dry-etched using the photoresist film 32 as a mask. This etching is performed using a gas that etches the silicon oxide film 18 with a high selectivity in order to prevent the silicon nitride film 17 under the silicon oxide film 18 from being shaved. When the silicon oxide film 18 on the gate electrode 7 is etched, the W film constituting a part of the gate electrode 7 serves as an etching stopper.

Next, as shown in FIG. 15, the silicon nitride film 17 is dry-etched using the photoresist film 32 as a mask, thereby forming a contact hole 20 above the n ⁺ type semiconductor region 14 and ^A contact hole 21 is formed above the ⁺ type semiconductor region 15, and a contact hole 22 is formed above the gate electrode 7. This etching is performed in order to minimize the amount of the silicon oxide film 3 in the substrate 1 and the element isolation trench 2 that is shaved.
Using a gas that etches with a high selectivity. As a result, contact holes 20 and 21 having a diameter smaller than the space between the adjacent gate electrodes 7 and 7 are formed in a self-aligned manner (self-alignment) with the gate electrode 7.

Next, as shown in FIG. 16, plugs 23 are formed inside the contact holes 20 to 22, and then wirings 24 to 29 are formed above the silicon oxide film 18.
The plug 23 and the wirings 24 to 29 are the same as those of the first embodiment.
It is formed by the same method as described above. As described above, according to the present embodiment, the same effects as in the first embodiment can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In the above embodiment, the case where the present invention is applied to a CMOS-gate array has been described. However, the present invention is not limited to this and can be widely applied to MOS-LSIs manufactured according to fine design rules.

[0042]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the speed of a semiconductor integrated circuit device having a MISFET can be promoted.

According to the present invention, high integration of a semiconductor integrated circuit device having a MISFET can be promoted.

According to the present invention, the manufacturing cost of a semiconductor integrated circuit device having a MISFET can be reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a fragmentary plan view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 11 is a plan view of a main portion of a substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 14 is a plan view of a main part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation groove 3 silicon oxide film 4 p-type well 5 n-type well 6 gate oxide film 7 gate electrode 8 silicon oxide film 9 silicide layer 10 Ti film 11 n ^- type semiconductor region 12 p ^- type semiconductor region 13 side Wall spacer 14 n ⁺ type semiconductor region (source, drain) 15 p ⁺ type semiconductor region (source, drain) 16 photoresist film 17 silicon nitride film 18 silicon oxide film 19 photoresist film 20 to 22 contact hole 23 plug 24 to 29 Wiring 31, 32 Photoresist film Qn N-channel MISFET Qp P-channel MISFET

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masafumi Miyamoto 3-16, Shinmachi, Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Yusuke Nonaka 6--16, Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center (72) Inventor Tomohiro Saito 6-16, Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center F-term (reference) 4M104 AA01 BB01 BB02 BB18 BB20 BB25 CC01 CC05 DD02 DD04 DD08 DD16 DD26 DD37 DD43 DD78 DD84 EE09 EE14 GG10 GG14 HH16 5F038 CA04 CD18 CD19 EZ15 EZ17 EZ18 5F048 AA00 AA09 AB02 AC03 BA01 BB06 BB09 BB13 BC06 BE03 BF06 BF15 BF16 BG14 DA25 DA30

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a first conductive film on a main surface of a semiconductor substrate and then forming a first conductive film on the first conductive film; Forming a gate electrode having an upper surface covered with the first silicon oxide film by patterning the first silicon oxide film and the first conductor film after forming the first silicon oxide film; (b)
After forming a source and a drain on the semiconductor substrate on both sides of the gate electrode, a refractory metal film is formed on the semiconductor substrate, and then the semiconductor substrate is subjected to a heat treatment to form a high melting point on the surfaces of the source and the drain. Forming a metal silicide layer; (c) forming a silicon nitride film on the semiconductor substrate after removing the first silicon oxide film on the gate electrode; and then forming a second silicon nitride film on the silicon nitride film. Forming a silicon oxide film; and (d) self-aligning the gate electrode over the source and drain by dry etching using an etching rate difference between the second silicon oxide film and the silicon nitride film. Forming a first contact hole and forming a second contact hole above the gate electrode; 2. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a first conductive film on a main surface of a semiconductor substrate, and then forming a first conductive film on the first conductive film; Forming a gate electrode having an upper surface covered with the first silicon oxide film by patterning the first silicon oxide film and the first conductor film after forming the first silicon oxide film; (b)
After forming a source and a drain on the semiconductor substrate on both sides of the gate electrode, a refractory metal film is formed on the semiconductor substrate, and then the semiconductor substrate is subjected to a heat treatment to form a high melting point on the surfaces of the source and the drain. Forming a metal silicide layer, (c) forming a silicon nitride film on the semiconductor substrate, and removing the silicon nitride film in a region where a second contact hole is to be formed in a later process, (d). After a second silicon oxide film is formed on the silicon nitride film, the gate electrode is formed on the source and the drain by dry etching using an etching rate difference between the second silicon oxide film and the silicon nitride film. Forming a first contact hole by self-alignment, and forming the second contact hole above the gate electrode. Degree. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first conductor film has a top portion made of a refractory metal film. Production method. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein after forming said gate electrode, prior to a step of forming said refractory metal silicide layer on said source and drain surfaces. Forming a sidewall spacer made of a silicon oxide film on a side wall of the gate electrode. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising, after the step (d), a step of forming a wiring on the second silicon oxide film. A method for manufacturing a semiconductor integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is a gate array. .