JP4241288B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a gate electrode having a silicide film and a manufacturing method thereof.

  Conventionally, in the field of LSI (Large Scale Integrated Circuit), miniaturization, high density, high speed and low power consumption of elements have been advanced.

  When miniaturizing an element, it is necessary to reduce the resistance of a gate electrode and a source / drain region of a MOS transistor and wiring in order to suppress an increase in resistance when the element is miniaturized. One method of reducing the resistance of the gate electrode and the source / drain region and the wiring is to form a silicide film on the polysilicon layer constituting the gate electrode and the wiring and on the source / drain region of the silicon substrate. Are known. Since this silicide is a compound of silicon and metal and has a lower resistance value than silicon, the resistance of the gate electrode and wiring made of polysilicon and the source / drain region made of a silicon substrate can be reduced. .

Conventionally, as a method for forming a silicide film, a salicide (Self-Aligned Silicide) film is formed on a polysilicon layer constituting a gate electrode and a source / drain region located on the surface of a silicon substrate in a self-aligning manner. ) Processes have been developed (see, for example, Patent Document 1). In this salicide process, the gate electrode and the source / drain regions can be silicided in the same process, so that the number of manufacturing steps and manufacturing cost can be reduced. For this reason, it is widely adopted in the manufacturing process of MOS transistors.
JP 2000-22150 A

  In the structure including the MOS transistor formed by using the above-described conventional salicide process, the resistance can be reduced by the silicide film, so that an increase in resistance can be suppressed even when the structure is miniaturized. However, when miniaturization is performed, the distance between the gate electrode of the MOS transistor and the wiring adjacent to the gate electrode is reduced, which causes a problem that the capacitance between the gate electrode and the wiring is increased. Here, when the distance between the centers of the gate electrode and the wiring is the same, the distance between the side surface of the gate electrode and the side surface of the wiring becomes larger when the line width of the gate electrode and the wiring is reduced. The capacity between the wiring and the wiring can be reduced. However, if the line width of the gate electrode or the wiring is made too small, the width of the silicide film becomes too small, so that there is a problem that the resistance rapidly increases due to the fine line effect of the silicide film.

The present invention has been made to solve the above problems,
One object of the present invention is to provide a semiconductor device capable of suppressing an increase in capacitance while suppressing a thin line effect of a silicide film.

  Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing an increase in capacitance while suppressing a thin line effect of a silicide film.

Means for Solving the Problems and Effects of the Invention

  In order to achieve the above object, a semiconductor device according to a first aspect of the present invention is formed on a semiconductor substrate via a gate insulating film, and has an upper and lower width larger than that of the central portion, and a gate. A first silicon layer functioning as an electrode and a first silicide film formed on the first silicon layer and functioning as a gate electrode are provided.

  In the semiconductor device according to the first aspect, as described above, the width of the upper and lower portions is larger than that of the central portion, and the first silicon layer that functions as the gate electrode is formed, thereby reducing the width of the central portion. Since the distance between the central portion of the gate electrode and the adjacent wiring is increased by the portion, the capacitance between the gate electrode and the wiring can be reduced correspondingly. Further, by reducing the width of the central portion from the upper portion, even when the width of the central portion is reduced in order to reduce the capacity, the width of the upper portion (upper surface) is prevented from being reduced. As a result, the width of the first silicide film formed on the first silicon layer can be prevented from being reduced, and the thin line effect of the silicide film can be reduced. As a result, it is possible to suppress an increase in capacitance while suppressing the fine line effect of the silicide film. Further, by forming the gate electrode in a shape where the width of the upper and lower portions is larger than that of the central portion, the upper and lower portions of the first silicon layer become mask portions when ion implantation is performed using the gate electrode as a mask. Compared with the case where only the upper part of one silicon layer serves as a mask, it is possible to further suppress the ion implantation of impurities into the region below the gate electrode of the semiconductor substrate. Thereby, the controllability of the ion implantation profile can be improved.

  In the semiconductor device according to the first aspect, the first silicon layer functioning as a gate electrode preferably includes an upper part having an inverted mesa shape and a lower part having a forward mesa shape. Since the shape having the upper part of the reverse mesa shape and the lower part of the forward mesa shape can be easily formed by etching, a gate electrode whose upper and lower widths are larger than the central part can be easily formed. can do.

  In the above configuration, preferably, the second silicon layer is formed with a predetermined distance from the gate electrode, and the upper and lower widths are larger than the central portion, and the second silicon layer functions as a wiring. And a second silicide film formed on the silicon layer and functioning as a wiring. If comprised in this way, the wiring containing the 2nd silicon layer which has a shape where the width | variety of an upper part and a lower part is larger than a center part, and the above-mentioned 1st silicon layer which has a shape whose width | variety of an upper part and a lower part is larger than a center part Since the distance between the central portion of the wiring and the central portion of the gate electrode can be further increased by the gate electrode including, the capacitance between the wiring and the gate electrode can be further reduced.

  In the semiconductor device according to the first aspect, preferably, a second electrode that is formed at a predetermined interval from the gate electrode, has a shape in which the width of the upper and lower portions is larger than that of the central portion, and functions as the gate electrode. The semiconductor device further includes a silicon layer and a second silicide film formed on the second silicon layer and functioning as a gate electrode. If comprised in this way, one gate electrode containing the 2nd silicon layer which has the shape where the width | variety of an upper part and a lower part is larger than a center part, and the above-mentioned 1st shape which has a shape whose width | variety of an upper part and a lower part is larger than a center part. Since the distance between the center portions of the two gate electrodes can be increased by the other gate electrode including one silicon layer, the capacitance between the two gate electrodes can be further reduced.

  In the above case, preferably, the first silicon layer and the second silicon layer are made of the same silicon layer. With this configuration, the first silicon layer and the second silicon layer can be etched in the same etching step, so that the upper and lower widths function as gate electrodes having a shape larger than that of the central portion. One silicon layer and a second silicon layer functioning as a wiring or gate electrode can be formed simultaneously. As a result, the manufacturing process can be simplified.

  A semiconductor device according to a second aspect of the present invention is formed on a semiconductor substrate and a gate insulating film on the semiconductor substrate, and has a shape in which the upper and lower widths are larger than the central portion, and a single metal layer A gate electrode.

  In the semiconductor device according to the second aspect, as described above, the width of the upper portion and the lower portion is larger than that of the central portion, and the gate electrode made of a single metal layer is formed, thereby reducing the width of the central portion. Since the distance between the central portion of the gate electrode and the adjacent wiring is increased by the portion, the capacitance between the gate electrode and the wiring can be reduced correspondingly. Further, by forming the gate electrode in a shape where the width of the upper and lower portions is larger than that of the central portion, the upper and lower portions of the first silicon layer become mask portions when ion implantation is performed using the gate electrode as a mask. Compared with the case where only the upper part of one silicon layer serves as a mask, it is possible to further suppress the ion implantation of impurities into the region below the gate electrode of the semiconductor substrate. Thereby, the controllability of the ion implantation profile can be improved.

  A semiconductor device according to a third aspect of the present invention is formed on a semiconductor substrate, and has a first conductive layer having a shape in which the widths of the upper and lower portions are larger than the central portion, the first conductive layer on the semiconductor substrate, and a predetermined width And a second conductive layer having a shape in which the width of the upper part and the lower part is larger than that of the central part.

  In the semiconductor device according to the third aspect, as described above, by forming the first conductive layer and the second conductive layer having a shape in which the width of the upper part and the lower part is larger than that of the central part with a predetermined interval therebetween, Since the distance between the central portion of the first conductive layer and the central portion of the second conductive layer adjacent to the central portion having the small width increases, the capacitance between the first conductive layer and the second conductive layer is increased accordingly. Can be reduced.

  In this case, preferably, the first conductive layer and the second conductive layer include a silicon layer having a shape in which the upper and lower widths are larger than the central portion, and a silicide film formed on the silicon layer. With this configuration, the width of the upper part (upper surface) is prevented from being reduced even when the width of the central part is reduced in order to reduce the capacity by making the central part smaller than the upper part. The As a result, the width of the silicide film formed on the silicon layer can be prevented from being reduced, and the thin line effect of the silicide film can be reduced. As a result, it is possible to suppress an increase in capacitance while suppressing the fine line effect of the silicide film.

  A method of manufacturing a semiconductor device according to a fourth aspect of the present invention includes a step of forming a first silicon layer on a semiconductor layer via a gate insulating film, a step of forming an etching mask on the first silicon layer, Etching the first silicon layer using the etching mask as a mask to form a first silicon layer that functions as a gate electrode having a shape in which the width of the upper and lower portions is larger than that of the central portion; and And a step of forming a first silicide film functioning as a gate electrode.

  As described above, the method for manufacturing a semiconductor device according to the fourth aspect is characterized in that the first silicon layer functions as a gate electrode having an upper and lower width larger than the central portion by etching the first silicon layer. By forming the layer, the distance between the central portion of the gate electrode and the adjacent wiring is increased by the central portion having a small width, and accordingly, the capacitance between the gate electrode and the wiring can be reduced. . Further, by reducing the width of the central portion from the upper portion, even when the width of the central portion is reduced in order to reduce the capacity, the width of the upper portion (upper surface) is prevented from being reduced. As a result, the width of the first silicide film formed on the first silicon layer can be prevented from being reduced, and the thin line effect of the silicide film can be reduced. As a result, it is possible to suppress an increase in capacitance while suppressing the fine line effect of the silicide film. In addition, by forming the gate electrode in a shape in which the width of the upper and lower portions is larger than that of the central portion, in the subsequent process, when ion implantation is performed using the gate electrode as a mask, the upper and lower portions of the first silicon layer are mask portions. Therefore, compared to the case where only the upper part of the first silicon layer is used as a mask, it is possible to further suppress the ion implantation of impurities into the region below the gate electrode of the semiconductor substrate. Thereby, the controllability of the ion implantation profile can be improved.

In the fourth aspect, preferably, the step of forming the gate electrode includes a first etching step of dry-etching the first silicon layer into a reverse mesa shape using an etching gas containing Cl ₂ , O _2, and HBr; After the first etching step, a second etching step of dry-etching the first silicon layer into a normal mesa shape using an etching gas containing O ₂ and HBr is included. If comprised in this way, the 1st silicon layer which has the upper part of a reverse mesa shape and the lower part of a forward mesa shape can be formed easily.

  In the method for manufacturing a semiconductor device according to the fourth aspect, preferably, a step of forming a second silicon layer on the semiconductor layer with a predetermined distance from the gate electrode, and an etching mask on the second silicon layer are formed. Forming a second silicon layer that functions as a wiring or gate electrode having a shape in which the width of the upper and lower portions is larger than that of the central portion by etching the second silicon layer using the etching mask as a mask; Forming a second silicide film functioning as a wiring or a gate electrode on the second silicon layer. If comprised in this way, the wiring or gate electrode containing the 2nd silicon layer which has a shape where the width | variety of an upper part and a lower part is larger than a center part, and the above-mentioned 1st shape which has a shape where the width | variety of an upper part and a lower part is larger than a center part. Since the distance between the central portion of the wiring or the gate electrode and the central portion of the gate electrode can be further increased by the gate electrode including one silicon layer, the capacitance between the wiring and the gate electrode, or two gates The capacity between the electrodes can be reduced.

  In this case, the first silicon layer and the second silicon layer are formed by patterning the same silicon layer. If comprised in this way, since it can pattern by etching a 1st silicon layer and a 2nd silicon layer by the same etching process, the width | variety of an upper part and a lower part has a shape larger than a center part. The silicon layer and the second silicon layer can be formed simultaneously. As a result, the manufacturing process can be simplified.

  In addition, in the above aspect, the following configuration is also conceivable. For example, in the semiconductor device according to the first aspect, preferably, the first silicon layer includes a lower layer made of a polysilicon layer and an upper layer made of an amorphous silicon layer. If comprised in this way, since the surface exposed by the etching of the amorphous material has a good surface roughness, the amorphous silicon layer can be etched to a surface having a good surface roughness. For this reason, if the polysilicon layer is etched subsequent to the amorphous silicon layer, the surface exposed by the etching of the polysilicon layer can also have good surface roughness. Thereby, the accuracy of the line width of the gate electrode can be improved.

  In the semiconductor device according to the first aspect, the lower width of the first silicon layer may be smaller than the upper width of the first silicon layer.

  In the semiconductor device having the second silicon layer, the second silicon layer preferably includes a lower layer made of a polysilicon layer and an upper layer made of an amorphous silicon layer. If comprised in this way, since the surface exposed by the etching of the amorphous material has a good surface roughness, the amorphous silicon layer can be etched to a surface having a good surface roughness. For this reason, if the polysilicon layer is etched subsequent to the amorphous silicon layer, the surface exposed by the etching of the polysilicon layer can also have good surface roughness. Thereby, the accuracy of the line width of the wiring can be improved.

  In the semiconductor device having the second silicon layer, the lower width of the second silicon layer may be smaller than the upper width of the second silicon layer.

  In the method for manufacturing a semiconductor device including the step of forming the second silicon layer, the second silicon layer preferably includes a lower layer made of a polysilicon layer and an upper layer made of an amorphous silicon layer. If comprised in this way, since the surface exposed by the etching of the amorphous material has a good surface roughness, the amorphous silicon layer can be etched to a surface having a good surface roughness. For this reason, if the polysilicon layer is etched subsequent to the amorphous silicon layer, the surface exposed by the etching of the polysilicon layer can also have good surface roughness. Thereby, the accuracy of the line width of the wiring or the gate electrode can be improved.

  In the method for manufacturing a semiconductor device including the step of forming the second silicon layer, the lower width of the second silicon layer may be smaller than the upper width of the second silicon layer.

    Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

In the semiconductor device according to the present embodiment, as shown in FIG. 1, an STI (Shallow Trench Isolation) structure for separating adjacent element formation regions (active regions) into a predetermined region on the main surface of the silicon substrate 1 is provided. The element isolation 2 is formed. The silicon substrate 1 is an example of the “semiconductor substrate” in the present invention. The upper surface of the element isolation 2 is formed to be stepped higher than the upper surface of the silicon substrate 1. In the active region surrounded by the element isolation 2 of the silicon substrate 1, a pair of n-type source / drain regions 3 are formed so as to sandwich the channel region. The source / drain region 3 has an LDD (Lightly Doped Drain) structure composed of a low concentration region 3a and a high concentration region 3b. A gate insulating film 4 made of SiO ₂ having a thickness of about 2 nm is formed on the channel region between the source / drain regions 3. A silicide film 5 c made of CoSi ₂ is formed on the high concentration region 3 b of the source / drain region 3.

Further, on the upper surface of the gate insulating film 4, a polysilicon layer 7a doped with phosphorus having a thickness of about 100 nm is formed. On the polysilicon layer 7a, an amorphous silicon layer 8a doped with phosphorus having a thickness of about 100 nm is formed. A silicide film 5a made of CoSi ₂ is formed on the upper surface of the amorphous silicon layer 8a. The gate electrode 6 is constituted by the polysilicon layer 7a, the amorphous silicon layer 8a, and the silicide film 5a. The pair of source / drain regions 3, gate insulating film 4, and gate electrode 6 constitute an n-channel MOS transistor. The polysilicon layer 7a and the amorphous silicon layer 8a are examples of the “first silicon layer” in the present invention, and the silicide film 5a is an example of the “first silicide film” in the present invention.

  Here, in the present embodiment, the gate electrode 6 has a forward mesa-shaped lower part 6a and a reverse mesa-shaped upper part 6b, and a constriction having a width W3 smaller than the width W1 of the lower part 6a and the width W2 of the upper part 6b. Part 6c is included. The constricted portion 6c is an example of the “central portion” in the present invention. Further, the narrowest part 6c is formed at a position of about 70 nm downward from the upper surface of the polysilicon layer 7a. Therefore, the width W1 of the lower portion 6a of the gate electrode 6 is formed to be smaller than the width W2 of the upper portion 6b.

Further, a phosphorus-doped polysilicon layer 7b having a thickness of about 100 nm is formed on the upper surface of the element isolation 2. An amorphous silicon layer 8b doped with phosphorus having a thickness of about 100 nm is formed on the polysilicon layer 7b. A silicide film 5b made of CoSi ₂ is formed on the upper surface of the amorphous silicon layer 8b. A wiring 9 is constituted by the polysilicon layer 7b, the amorphous silicon layer 8b, and the silicide film 5b. The polysilicon layer 7b and the amorphous silicon layer 8b are examples of the “second silicon layer” in the present invention, and the silicide film 5b is an example of the “second silicide film” in the present invention.

  In the present embodiment, the wiring 9 has a forward mesa-shaped lower portion 9a and an inverted mesa-shaped upper portion 9b, and a constricted portion 9c having a width W1 smaller than the width W1 of the lower portion 9a and the width W2 of the upper portion 9b. including. The constricted portion 9c is an example of the “central portion” in the present invention. Further, the narrowest part 9c is formed at a position of about 70 nm downward from the upper surface of the polysilicon layer 7b. For this reason, the width W1 of the lower part 9a of the wiring 9 is formed to be smaller than the width W2 of the upper part 9b.

  In the present embodiment, the polysilicon layer 7a constituting the gate electrode 6 and the polysilicon layer 7b constituting the wiring 9 are formed from the same polysilicon layer. The amorphous silicon layer 8a constituting the gate electrode 6 and the amorphous silicon layer 8b constituting the wiring 9 are formed from the same amorphous silicon layer.

Then, on both side surfaces of the gate electrode 6 and the wiring 9, first sidewall films 10a and 10b made of SiO ₂ are formed so as to fill the constricted portions 6c and 9c of the gate electrode 6 and the wiring 9, respectively. Yes. On both side surfaces of the first sidewall films 10a and 10b, second sidewall films 11a and 11b made of Si ₃ N ₄ having a thickness of about 30 nm are formed.

  In the present embodiment, as described above, the constricted portion 6c having the lower portion 6a having the forward mesa shape and the upper portion 6b having the reverse mesa shape and having the width W3 smaller than the width W1 of the lower portion 6a and the width W2 of the upper portion 6b. By forming the included gate electrode 6, the distance between the gate electrode 6 and the adjacent wiring 9 is increased by the constricted portion 6c having a small width W3. The capacity can be reduced. Even when the constricted portion 6c having a small width W3 is formed in order to reduce the capacitance by making the width W2 of the upper portion 6b of the gate electrode 6 larger than the width W1 of the lower portion 6a, the upper portion of the gate electrode 6 can be reduced. Since it is possible to prevent the width of the silicide film 5a constituting 6b from being reduced, the fine line effect of the silicide film 5a can be reduced. As a result, an increase in capacitance can be suppressed while suppressing the fine line effect of the silicide film 5a. Further, when ions are implanted using the polysilicon layer 7a and the amorphous silicon layer 8a constituting the gate electrode 6 as a mask, even if phosphorus is ion-implanted from an oblique direction, the forward mesa-shaped lower portion 6a and the inverted mesa-shaped upper portion Since 6b serves as a mask portion, it is possible to further suppress phosphorus from being ion-implanted into a region below the gate electrode 6 of the silicon substrate 1 as compared with a case where only the inverted mesa-shaped upper portion 6b serves as a mask. . Thereby, the controllability of the ion implantation profile can be improved. Further, since it is possible to suppress an increase in the distance (channel length) between the source / drain regions 3, the operation speed is increased accordingly.

  In this embodiment, as described above, the gate electrode 6 and the wiring 9 are formed by forming the wiring 9 including the constricted portion 9c having the width W3 smaller than the width W1 of the lower portion 9a and the width W2 of the upper portion 9b. Therefore, the capacitance between the gate electrode 6 and the wiring 9 can be further reduced. Even when the constricted portion 9c having a small width W3 is formed in order to reduce the capacitance by making the width W2 of the upper portion 9b of the wiring 9 larger than the width W1 of the lower portion 9a, the upper portion 9b of the wiring 9 is reduced. Since the width of the silicide film 5b to be formed can be prevented from being reduced, the fine line effect of the silicide film 5b can be reduced.

  In the present embodiment, as described above, the polysilicon layer 7a constituting the gate electrode 6 and the polysilicon layer 7b constituting the wiring 9 are formed from the same polysilicon layer, and the gate electrode 6 is constituted. By forming the amorphous silicon layer 8a and the amorphous silicon layer 8b constituting the wiring 9 from the same amorphous silicon layer, the polysilicon layer 7a and the amorphous silicon layer 8a constituting the gate electrode 6 and the polysilicon constituting the wiring 9 are formed. The silicon layer 7b and the amorphous silicon layer 8b can be etched in the same etching process. Thereby, since the gate electrode 6 and the wiring 9 can be formed simultaneously, the manufacturing process can be simplified.

  In the present embodiment, as described above, the gate electrode 6 has a structure including the polysilicon layer 7a and the amorphous silicon layer 8a, so that the surface exposed by etching of the amorphous material has good surface roughness. Therefore, the amorphous silicon layer 8a can be etched so as to have a surface having good surface roughness. Therefore, if the polysilicon layer 7a is etched subsequent to the amorphous silicon layer 8a, the surface exposed by the etching of the polysilicon layer 7a can also have good surface roughness. Thereby, the accuracy of the line width of the gate electrode 6 can be improved. Further, since the wiring 9 also has a structure including the polysilicon layer 7b and the amorphous silicon layer 8b, the line width accuracy can be improved as in the case of the gate electrode 6.

  2 to 9 are cross-sectional views for explaining a semiconductor device manufacturing process according to an embodiment of the present invention. Next, the manufacturing process of the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, as shown in FIG. 2, after forming an element isolation groove in a predetermined region on the main surface of the silicon substrate 1, the surface of the element isolation groove is oxidized. Then, an element isolation 2 having an STI structure for isolating the active region is formed by embedding an insulator in the element isolation trench. Further, by oxidizing the surface of the silicon substrate 1, a gate insulating film 4 made of SiO ₂ having a thickness of about 2 nm is formed. The element isolation 2 and the gate insulating film 4 have a thickness of about 100 nm, a polysilicon layer 7 doped with phosphorus by ion implantation, and a thickness of about 100 nm. A doped amorphous silicon layer 8 is formed sequentially. The polysilicon layer 7 and the amorphous silicon layer 8 are examples of the “silicon layer” in the present invention. Thereafter, rapid thermal annealing is performed under a temperature condition of about 1000 ° C. using RTA (Rapid Thermal Annealing) technology to activate the phosphorus ions doped in the polysilicon layer 7 and the amorphous silicon layer 8.

  Next, as shown in FIG. 3, an etching mask 12 made of a sulfonium-based resist is formed on a predetermined region of the amorphous silicon layer 8 by using a lithography technique.

Next, using the etching mask 12 as a mask, the etching depth from the upper surface of the amorphous silicon layer 8 is about 170 nm (about 70 nm from the upper surface of the polysilicon layer 7), and the polycrystal is formed from the upper surface of the amorphous silicon layer 8. Etching is performed so that the shape of the silicon layer 7 up to the middle becomes an inverted mesa shape. Etching conditions in this case are as follows: in an inductively coupled plasma etching apparatus, pressure: about 1.33 Pa, upper electrode: about 300 W, lower electrode: about 40 W, substrate temperature: about 65 ° C., aperture ratio: about 50% to about 60 %, Etching gas: Cl ₂ (about 20 sccm), O ₂ (about 1 sccm) and HBr (about 180 sccm). By etching under such conditions, amorphous silicon layers 8a and 8b having a reverse mesa shape as a whole are formed as shown in FIG. 4, and the shape up to the middle of the polysilicon layer 7 is changed to a reverse mesa shape. Become. This etching step is an example of the “first etching step” in the present invention.

Then, after changing the etching conditions, the etching is continued so that the shape from the middle of the polysilicon layer 7 becomes a forward mesa shape. The etching conditions in this case are as follows: in an inductively coupled plasma etching apparatus, pressure: about 1.995 Pa, upper electrode: about 250 W, lower electrode: about 12 W, substrate temperature: about 65 ° C., aperture ratio: about 50% to about 60 %, Etching gas: O ₂ (about ₂ sccm) and HBr (about 180 sccm). By etching under such conditions, it is possible to easily perform etching so that the shape of the polysilicon layer 7 from the middle becomes a reverse mesa shape. Thereafter, the etching mask 12 is removed. This etching step is an example of the “second etching step” in the present invention.

  As a result, a polysilicon layer 7a and an amorphous silicon layer 8a constituting the gate electrode 6 are formed on a predetermined region of the gate insulating film 4 as shown in FIG. Further, on the upper surface of the element isolation 2, a polysilicon layer 7 b and an amorphous silicon layer 8 b constituting the wiring 9 having the reverse mesa shape and the forward mesa shape similar to the gate electrode 6 are formed. Further, since the etching is performed so that the shape of the polysilicon layers 7a and 7b from the middle becomes an inverted mesa shape, the width W1 below the polysilicon layers 7a and 7b is smaller than the width W2 of the amorphous silicon layers 8a and 8b. Become.

  Next, in this embodiment, as shown in FIG. 6, the low concentration region 3a is formed by ion-implanting phosphorus into the silicon substrate 1 using the polysilicon layer 7a and the amorphous silicon layer 8a as a mask. At this time, even if phosphorus is ion-implanted from an oblique direction, the lower portion of the forward mesa-shaped polysilicon layer 7a prevents phosphorus from being ion-implanted into a region below the polysilicon layer 7a of the silicon substrate 1. be able to.

Next, after depositing a SiO ₂ film (not shown) having a thickness of about 200 nm on the entire surface, the SiO ₂ film is anisotropically etched to form both sides of the polysilicon layers 7a and 7b. First sidewall films 10a and 10b made of SiO ₂ are formed on both side surfaces of the amorphous silicon layers 8a and 8b, respectively. Thereafter, a silicon nitride film (Si ₃ N ₄ film) (not shown) having a film thickness of about 150 nm is formed on the entire surface, and then the Si ₃ N ₄ film is anisotropically etched to form FIG. As shown in FIG. 5, second sidewall films 11a and 11b made of Si ₃ N ₄ having a thickness of about 30 nm are formed on both side surfaces of the first sidewall films 10a and 10b.

  Next, as shown in FIG. 8, phosphorus is ion-implanted into the silicon substrate 1 using the amorphous silicon layer 8a and the second sidewall film 11a as a mask, thereby forming the high concentration region 3b. As a result, an n-type source / drain region 3 having an LDD structure composed of the low concentration region 3a and the high concentration region 3b is formed.

Next, a salicide process is performed. That is, as shown in FIG. 9, about the upper surface of the silicon substrate 1, the upper surfaces of the amorphous silicon layers 8a and 8b, and the both side surfaces of the second sidewall films 11a and 11b by using a sputtering method. A Co film 13 having a thickness of 30 nm is formed. Then, by performing rapid thermal processing under a temperature condition of about 650 ° C. using the RTA technique, Si and Co located on the upper surfaces of the amorphous silicon layers 8a and 8b are reacted with each other, and are positioned on the upper surface of the silicon substrate 1. Si and Co are reacted. Thus, on the amorphous silicon layer 8a and 8b, respectively, together with silicide films 5a and 5b made of CoSi ₂ is formed in a self-aligned manner, on the high concentration region 3b of the source / drain region 3, composed of CoSi ₂ Silicide film 5c is formed in a self-aligning manner. Thereafter, the unreacted Co film 13 is selectively removed. In this manner, the gate electrode 6 having the constricted portion 6c including the forward mesa-shaped lower portion 6a and the reverse mesa-shaped upper portion 6b as shown in FIG. 1 is formed on the upper surface of the gate insulating film 4. On the upper surface of the element isolation 2, a wiring 9 having a constricted portion 9 c including a forward mesa-shaped lower part 9 a and a reverse mesa-shaped upper part 9 b is formed. Thereby, the semiconductor device including the n-channel MOS transistor according to the present embodiment is formed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

For example, in the above embodiment, the silicide films 5a, 5b and 5c made of CoSi ₂ are formed. However, the present invention is not limited to this, and a silicide film made of TiSi ₂ , NiSi, WSi, PtSi ₂ or the like is formed. You may make it do.

In the above embodiment, the second sidewall films 11a and 11b made of Si ₃ N ₄ are formed. However, the present invention is not limited to this, and satisfies the general composition formula Si _X N _Y. A second sidewall film made of a silicon nitride film having a composition other than Si ₃ N ₄ may be formed. Further, as the second sidewall film, a sidewall film made of SiO ₂ or another insulating material may be formed. Alternatively, only the second sidewall films 11a and 11b may be formed without forming the first sidewall films 10a and 10b made of SiO ₂ .

  In the above embodiment, the amorphous silicon layer 8 and the polysilicon layer 7 are etched using the inductively coupled plasma etching apparatus. However, the present invention is not limited to this, and the electron cyclotron resonance type and the capacitive coupling type are used. You may make it etch using other plasma dry etching apparatuses, such as a 2 frequency plasma type and a surface wave plasma type.

  In the above embodiment, the gate electrode 6 having the constricted portion 6c including the forward mesa-shaped lower portion 6a and the reverse mesa-shaped upper portion 6b is formed on the upper surface of the gate insulating film 4, and the gate insulating film 4 Although an example in which the wiring 9 having the constricted portion 9c including the forward mesa-shaped lower portion 9a and the reverse mesa-shaped upper portion 9b is formed on the upper surface of the element isolation 2 arranged with a spacing of However, the present invention is not limited thereto, and the gate electrode 6 may be formed instead of the wiring 9. Specifically, as in the first modification shown in FIG. 10, the gate insulating film 4 is formed on the active region at a predetermined interval, and on the two gate insulating films 4, respectively. A gate electrode 6 having a constricted portion 6c including a forward mesa-shaped lower portion 6a and an inverted mesa-shaped upper portion 6b may be formed. In this case, a common n-type source / drain region 3 having an LDD structure composed of the low concentration region 3a and the high concentration region 3b is formed between the two gate electrodes 6. The two polysilicon layers 7a constituting the two gate electrodes 6 are made of the same layer, and the two amorphous silicon layers 8a constituting the two gate electrodes 6 are made of the same layer.

  In the above embodiment, the gate electrode 6 having the constricted portion 6c including the forward mesa-shaped lower portion 6a and the reverse mesa-shaped upper portion 6b is formed on the upper surface of the gate insulating film 4, and the gate insulating film 4 Although an example in which the wiring 9 having the constricted portion 9c including the forward mesa-shaped lower portion 9a and the reverse mesa-shaped upper portion 9b is formed on the upper surface of the element isolation 2 arranged with a spacing of Not only this but wiring 9 may be formed instead of gate electrode 6. Specifically, as in the second modification shown in FIG. 11, the element isolation 2 is formed on the active region at a predetermined interval, and the forward mesa is respectively formed on the two element isolations 2. You may make it form the wiring 9 which has the constriction part 9c containing the shape lower part 9a and the reverse mesa-shaped upper part 9b. In this case, the two polysilicon layers 7b constituting the two wirings 9 are made of the same layer, and the two amorphous silicon layers 8b constituting the two wirings 9 are made of the same layer.

  In the above embodiment, the gate electrode 6 including the polysilicon layer 7a, the amorphous silicon layer 8a, and the silicide film 5a is formed on the upper surface of the gate insulating film 4, and is spaced from the gate insulating film 4 by a predetermined distance. Although an example in which the wiring 9 composed of the polysilicon layer 7b, the amorphous silicon layer 8b, and the silicide film 5b is formed on the upper surface of the element isolation 2 that has been arranged is shown, the present invention is not limited to this, and the gate electrode 6 and the wiring 9 may be changed to a metal gate electrode 16 and a metal wiring 19 made of a single metal layer having the same constricted shape as in the third modification shown in FIG. As a single metal layer constituting the metal gate electrode 16 and the metal wiring 19, a metal layer made of aluminum (Al), titanium (Ti), tungsten (W), copper (Cu), or an oxide or nitride thereof. Can be considered. Also in this case, the distance between the metal gate electrode 16 and the metal wiring 19 can be further increased by the metal gate electrode 16 and the metal wiring 19 including the constricted portion. The capacity between can be further reduced.

It is sectional drawing which showed the semiconductor device by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by one Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by one Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by one Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by one Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by one Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by one Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by one Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by one Embodiment of this invention shown in FIG. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by the 1st modification of one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by the 2nd modification of one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by the 3rd modification of one Embodiment of this invention.

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
4 Gate insulating film 5a Silicide film (first silicide film)
5b Silicide film (second silicide film)
6 Gate electrode 6a, 9a Lower part 6b, 9b Upper part 6c, 9c Constriction part (central part)
7 Polysilicon layer (silicon layer)
7a Polysilicon layer (first silicon layer)
7b Polysilicon layer (second silicon layer)
8 Amorphous silicon layer (silicon layer)
8a Amorphous silicon layer (first silicon layer)
8b Amorphous silicon layer (second silicon layer)
9 Wiring 12 Etching mask

Claims (9)

A first silicon layer formed on a semiconductor substrate via a gate insulating film, having an upper and lower width larger than the central portion, and functioning as a gate electrode;
A first silicide film formed on the first silicon layer and functioning as the gate electrode;
A second silicon layer formed on the semiconductor substrate at a predetermined interval from the gate electrode and having a shape in which the widths of the upper and lower portions are larger than the central portion, and function as a wiring or a gate electrode;
A second silicide film formed on the second silicon layer and functioning as the wiring or gate electrode,
Each of the first silicon layer and the second silicon layer has a forward mesa shape portion and an inverted mesa shape portion on the forward mesa shape portion, and a lower portion of the first silicon layer and a lower portion of the second silicon layer. A semiconductor device, wherein an interval is formed larger than an interval between an upper portion of the first silicon layer and an upper portion of the second silicon layer. The semiconductor device according to claim 1 , wherein the first silicon layer and the second silicon layer are made of the same silicon layer. A semiconductor substrate;
A gate electrode formed on the semiconductor substrate via a gate insulating film, having a shape in which the width of the upper and lower portions is larger than that of the central portion, and a single metal layer;
The gate electrode is formed on the semiconductor substrate at a predetermined interval and has a shape in which the width of the upper and lower portions is larger than that of the central portion, and includes a wiring made of a single metal layer,
Each of the gate electrode and the wiring has a forward mesa-shaped portion and an inverted mesa-shaped portion above the forward mesa-shaped portion, and an interval between the lower portion of the gate electrode and the lower portion of the wiring is set between the upper portion of the gate electrode and the upper portion of the gate electrode. A semiconductor device formed larger than the distance from the upper part of the wiring. A first conductive layer formed on a semiconductor substrate and having a shape in which upper and lower widths are larger than a central portion;
A second conductive layer formed on the semiconductor substrate at a predetermined interval from the first conductive layer, having an upper and lower width larger than that of the central portion , and made of the same material as the first conductive layer. Layers,
With
Each of the first conductive layer and the second conductive layer has a forward mesa-shaped portion and an inverted mesa-shaped portion thereon, and a lower portion of the first conductive layer and a lower portion of the second conductive layer. A semiconductor device, wherein an interval is formed larger than an interval between an upper portion of the first conductive layer and an upper portion of the second conductive layer. The first conductive layer and the second conductive layer are:
A silicon layer having a shape in which the width of the upper part and the lower part is larger than the central part;
The semiconductor device according to claim 4 , further comprising a silicide film formed on the silicon layer. A first step of forming a first silicon layer on the semiconductor layer via a gate insulating film;
A second step of forming an etching mask on the first silicon layer;
Etching the first silicon layer using the etching mask as a mask has a forward mesa-shaped portion and a reverse mesa-shaped portion above it, and the upper and lower widths are larger than the central portion. A third step of forming a first silicon layer functioning as a first gate electrode;
A fourth step of forming a first silicide film functioning as the first gate electrode on the first silicon layer;
A fifth step of forming a second silicon layer on the semiconductor layer at a predetermined interval from the first gate electrode;
A sixth step of forming an etching mask on the second silicon layer;
Etching the second silicon layer using the etching mask as a mask has a forward mesa-shaped portion and an inverted mesa-shaped portion thereon, and the upper and lower widths are larger than the central portion. A seventh step of forming a second silicon layer functioning as a wiring or a second gate electrode;
On the second silicon layer, Bei example an eighth step of forming a second silicide film functioning as the wiring or the second gate electrode,
According to the third step and the seventh step, an interval between the lower portion of the first silicon layer and the lower portion of the second silicon layer is greater than an interval between the upper portion of the first silicon layer and the upper portion of the second silicon layer. A method for manufacturing a semiconductor device, which is also greatly formed . The third step includes
A first etching step of dry-etching the first silicon layer into an inverted mesa shape using an etching gas containing Cl ₂ , O ₂ and HBr;
The semiconductor device manufacturing method according to claim 6 , further comprising a second etching step of dry etching the first silicon layer into a forward mesa shape using an etching gas containing O ₂ and HBr after the first etching step. Method. 8. The method of manufacturing a semiconductor device according to claim 6 , wherein the first silicon layer in the third step and the second silicon layer in the seventh step are formed by patterning the same silicon layer. A first step of forming a silicon layer on the semiconductor layer via a gate insulating film;
A second step of forming an etching mask on the silicon layer;
By etching the silicon layer using the etching mask as a mask, a first mesa-shaped portion and a reverse mesa-shaped portion above the first mesa-shaped portion are formed. A first silicon layer functioning as a gate electrode, a forward mesa-shaped portion and a reverse mesa-shaped portion above the first silicon layer at a predetermined distance from each other. A third step of forming a wiring having a shape larger than the central portion or a second silicon layer functioning as a second gate electrode;
A first silicide film functioning as the first gate electrode is formed on the first silicon layer, and a second silicide film functioning as the wiring or the second gate electrode is formed on the second silicon layer. A fourth step of forming,
In the third step, the gap between the lower portion of the first silicon layer and the lower portion of the second silicon layer is formed larger than the gap between the upper portion of the first silicon layer and the upper portion of the second silicon layer. A method for manufacturing a semiconductor device.

Images