KR20030042153A - MOS Transistor With T-Shaped Gate Electrode And Method Of Fabricating The Same - Google Patents

Abstract

PURPOSE: A method for fabricating a metal oxide semiconductor(MOS) transistor with a T-shaped gate electrode is provided to reduce capacitance, make a channel length short, increase a cross section of a gate and decrease source/drain resistance by forming an intermediate density impurity region between a high density impurity region and a low density impurity region while using an L-shaped gate spacer formed on the side surface of the T-shaped gate electrode. CONSTITUTION: The T-shaped gate electrode is formed on a semiconductor substrate(100). A low density ion implantation process is performed by using the gate electrode as an ion implantation mask so that the low density impurity region(160) is formed in the semiconductor substrate at both sides of the gate electrode. An L-shaped lower spacer(175), an L-shaped intermediate spacer and an upper spacer are sequentially stacked on the low density impurity region at the side surface of the gate electrode. The upper and intermediate spacers are eliminated to expose the lower spacer. A high density ion implantation process is performed on the semiconductor substrate to which the lower spacer is exposed so that the high density impurity region(200) and the intermediate density impurity region(205) are formed.

Description

MOS transistor with T-shape gate electrode and manufacturing method thereof MOS Transistor With T-Shaped Gate Electrode And Method Of Fabricating The Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a MOS transistor having a T-shaped gate electrode and a manufacturing method thereof.

With the development of the electronics industry, semiconductor devices are further required to have high integration and high speed characteristics. In order to satisfy these requirements, MOS transistors having various structures are used in semiconductor devices. However, semiconductor devices including MOS transistors according to the prior art have a problem that does not satisfy all of the above conditions.

1 is a process sectional view showing a general MOS transistor.

Referring to FIG. 1, the gate oxide film 12 and the gate pattern 14 are sequentially disposed on the semiconductor substrate 10. Gate spacers 16 are disposed on both sidewalls of the gate pattern 14. A high concentration impurity region 20 is disposed in the semiconductor substrate 10 next to the gate spacer 16.

However, due to the miniaturization of the gate pattern 14 due to the high integration of the semiconductor device, the gap between the high concentration impurity regions 20, that is, the gap between the source and the drain, is further reduced. The resulting short channel effect is a major cause of deterioration of the characteristics of the semiconductor device.

In order to minimize the short channel phenomenon, a method of forming a low concentration impurity region 18 in the semiconductor substrate 10 under the gate spacer 16 is generally used. The structure of the high concentration impurity region 20 and the low concentration impurity region 18 thus constructed is generally referred to as a structure of lightly doped drain (LDD).

However, although the short channel phenomenon due to the miniaturization of the gate pattern 14 is minimized by the LDD structure, forming the gate pattern 14 more minutely has difficulties due to technical limitations and at the same time, It causes other problems that worsen the properties. That is, the miniaturization of the gate pattern 14 increases the resistance of the gate line, and increases the capacitance between the gate pattern 14 and the high concentration impurity region 20. Therefore, miniaturization of the gate pattern 14 becomes a cause of making it difficult to speed up the semiconductor device.

FIG. 2 is a cross-sectional view illustrating another example of a MOS transistor according to the related art, which is a MOS transistor having a T-shaped gate electrode. An example of such a MOS transistor having a T-shaped gate electrode is disclosed in a paper published by T. Ghani et al. ("100 nm gate length high performance / low power CMOS transistor structure", IEDM Technical Digest, 1999, pp. 415-). 418)

Referring to FIG. 2, the gate oxide layer 32 and the gate pattern 34 are sequentially disposed on the semiconductor substrate 30. The gate pattern 34 is characterized in that the T-shape having an undercut region. Gate spacers 36 may be disposed on both sidewalls of the gate pattern 34 to fill the undercut regions. A high concentration impurity region 40 is disposed in the semiconductor substrate 30 next to the gate spacer 36, and a low concentration impurity region 38 is formed in the semiconductor substrate 40 under the gate spacer 36 and the undercut region. do.

In the MOS transistor including the gate pattern 34, the distance between the heavily doped impurity region 40 and the gate pattern 34 is further separated by the width of the undercut region, compared to the structure of the transistor described in FIG. 1. do. Therefore, the capacitance between the gate pattern 34 and the heavily doped impurity region 40 can be reduced. In addition, the width of the channel of the semiconductor device may be reduced by the width of the undercut region.

However, the width of the low concentration impurity region 38 increases by the width of the undercut region, thereby increasing the source / drain resistance R _{sd of the} transistor.

An object of the present invention is to provide a method of manufacturing a MOS transistor having a T-shaped gate electrode that can reduce the source / drain resistance.

Another object of the present invention is to provide a MOS transistor including a heavily doped impurity region capable of reducing source / drain resistance.

1 and 2 are cross-sectional views illustrating MOS transistors according to the related art.

3 to 8 are cross-sectional views illustrating a method of manufacturing a MOS transistor having a T-shaped gate electrode according to an exemplary embodiment of the present invention.

9 is a perspective view illustrating a MOS transistor having a T-shaped gate electrode according to a preferred embodiment of the present invention.

In order to achieve the above technical problem, the present invention provides a method of manufacturing a MOS transistor comprising the step of forming a heavily doped impurity region using an L-shaped spacer. The method includes forming a gate electrode in a T-shape on a semiconductor substrate and then forming a low concentration impurity region in the semiconductor substrate on both sides of the gate electrode. It is disposed on the side of the gate electrode, to form an L-shaped lower spacer having a horizontal protrusion extending over the low concentration impurity region. The L-shaped lower spacer and the gate pattern are used as an ion implantation mask to form a high concentration impurity region and a medium concentration impurity region.

Forming the T-shaped gate electrode may include forming a lower conductive layer pattern and an upper conductive layer pattern sequentially stacked on the semiconductor substrate, and then selectively etching the lower conductive layer pattern. . Accordingly, the lower conductive layer pattern and the upper conductive layer pattern may be material layers having etching selectivity with each other. For example, the lower conductive layer pattern may be formed of silicon germanium or titanium nitride, and the upper conductive layer pattern may be formed of polycrystalline silicon or tungsten. In addition, the step of selectively etching the lower conductive layer pattern is preferably performed by an isotropic etching method. Accordingly, an undercut region is formed under the edge of the upper conductive film pattern.

The forming of the L-shaped lower spacer may sequentially form lower, middle, and upper insulating films on the entire surface of the semiconductor substrate including the T-shaped gate electrode, and sequentially etch these insulating films to form the lower and middle L-shaped films. After forming the spacers and the upper spacers, it is preferable to include removing the upper and middle spacers. In this case, at least the upper spacer is preferably formed by etching the upper insulating film by an anisotropic etching method.

The lower spacer may be formed of one of a nitride film, an oxynitride film, and polycrystalline silicon, and the middle spacer and the upper spacer may be formed of a material film having an etching selectivity with respect to the lower spacer and the middle spacer, respectively. .

In order to achieve the above technical problem, the present invention provides a MOS transistor having a T-shaped gate electrode including an L-shaped spacer and a heavily doped impurity region. The MOS transistor includes a gate electrode disposed in a T-shape on a semiconductor substrate, an L-shaped lower spacer disposed on a side of the gate electrode and covering the upper portion of the semiconductor substrate, and a low concentration impurity region and a medium concentration formed on the semiconductor substrates on both sides of the gate electrode. Impurity regions and high concentration impurity regions. The high concentration impurity region is disposed on the semiconductor substrate on the side of the lower spacer, and the medium concentration impurity region is disposed between the high concentration impurity region and the low concentration impurity region.

The gate electrode may include a lower conductive layer pattern and an upper conductive layer pattern that are sequentially stacked. In this case, the upper conductive film pattern may have a wider width than the lower conductive film pattern, so that an undercut region is provided under the upper conductive film pattern. In addition, the lower spacer may further include a horizontal extension portion filling the undercut region.

The lower conductive layer pattern and the upper conductive layer pattern may be formed of a material layer having an etching selectivity with each other. For example, the lower conductive layer pattern may be silicon germanium or titanium nitride, and the upper conductive layer pattern may be made of polycrystalline silicon or tungsten.

A surface insulating film may be interposed between the gate electrode and the lower spacer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

3 to 8 are cross-sectional views illustrating a method of manufacturing a MOS transistor according to a preferred embodiment of the present invention.

Referring to FIG. 3, an isolation layer pattern (not shown) defining an active region is formed in a predetermined region of the semiconductor substrate 100. A gate oxide film 110 is formed on the active region. A gate conductive film is formed on the entire surface of the semiconductor substrate including the gate oxide film 110. The gate conductive layer is patterned until the gate oxide layer 110 is exposed to form a gate pattern 140 crossing the active region. In this case, the gate pattern 140 is formed in a T-shape to have an undercut region.

The gate oxide film 110 may be formed by thermally oxidizing the semiconductor substrate 100 exposed to the active region. The gate conductive layer may be formed of a lower conductive layer and an upper conductive layer that are sequentially stacked on the entire surface of the semiconductor substrate including the gate oxide layer 110. In order to form the gate pattern 140 having the undercut region, the upper and lower conductive layers are patterned to form the lower conductive layer pattern 120 and the upper conductive layer pattern 130 which are sequentially stacked, and then the lower conductive layer is formed. The pattern 120 is selectively etched. In this case, the selective etching process for forming the undercut region is preferably performed by an isotropic etching method. In addition, another method for forming the undercut region may be a method of forming the upper conductive layer pattern 130 and then etching the lower conductive layer by isotropic etching. Accordingly, an undercut region in which side surfaces of the lower conductive layer pattern 120 are etched is formed below the upper conductive layer pattern 130. The upper conductive layer pattern 130 and the lower conductive layer pattern 120 constitute the gate pattern 140.

In order to minimize etching damage to the semiconductor substrate 100 in the etching process for forming the gate pattern 140, the lower conductive layer pattern 120 and the gate oxide layer 110 may have an etch selectivity with each other. It is preferable to form the material film which has. In addition, in order to minimize the occurrence of etching damage in the selective etching process for forming the undercut region, the lower conductive layer pattern 120 has an etch selectivity with respect to the upper conductive layer pattern 130 and the gate oxide layer 110. It is formed of a material film having

In consideration of the etching selectivity between the material layers 110, 120, and 130, the lower conductive layer pattern 120 and the upper conductive layer pattern 130 are formed of silicon germanium (SiGe) and polycrystalline silicon (Si), respectively. Or titanium nitride (TiN) and tungsten (W), respectively.

As described above, the gate pattern 140 may not be formed of two layers of the lower and upper conductive layer patterns 120 and 130, but may be formed of a single material layer. The gate pattern 140 is still a conductive material film and preferably a material film having an etch selectivity with respect to the gate oxide film 110. Therefore, in this case, it is preferable to form the gate pattern 140 of polycrystalline silicon.

In addition, in order to form the undercut region, the etching process for forming the gate pattern 140 may be a dry etching method having an etching selectivity with respect to the gate oxide layer 110. In this case, the etching gas in the plasma state used for the dry etching is diffusely reflected from the gate oxide layer 110 to form an undercut region in the gate pattern 140.

Referring to FIG. 4, the semiconductor substrate including the gate pattern 140 is thermally oxidized in order to cure the etching damage occurring in the etching process for forming the gate pattern 140. Accordingly, the surface insulating layer 150 is conformally formed on the exposed surface of the gate pattern 140 on which the undercut region is formed. The surface insulating layer 150 may be formed on an upper surface of the gate oxide layer 110 exposed to both sides of the gate pattern 140.

A low concentration ion implantation process using the gate pattern 140 as an ion implantation mask is performed on the semiconductor substrate including the surface insulating layer 150. Accordingly, the low concentration impurity region 160 is formed in the semiconductor substrate 100 on both sides of the gate pattern 140.

The low concentration impurity region 160 may be formed under the undercut region. For this purpose, the low concentration ion implantation process may use an ion implantation process inclined to the semiconductor substrate 100. The gate oxide film 110 and the surface insulating film 150 are used as an ion channeling prevention film in the low concentration ion implantation process.

Referring to FIG. 5, the lower insulating layer 170, the middle insulating layer 180, and the upper insulating layer 190 which are sequentially stacked on the entire surface of the semiconductor substrate including the low concentration impurity region 160 are conformally formed.

Accordingly, the lower insulating film 170 covers the entire surface of the surface insulating film 150 and fills the undercut region of the gate pattern 140 together with the surface insulating film 150. When the undercut region is narrow, the undercut region may be filled only with the surface insulating layer 150.

In this case, the lower insulating film 170 may be a material film having an etch selectivity with respect to the gate oxide film 110 and the surface insulating film 150, that is, the oxide film. In addition, the middle insulating film 180 may be a material film having a selectivity with respect to the lower insulating film 170, and the upper insulating film 190 may have a material selectivity with an etch selectivity with respect to the middle insulating film 180. Is preferably. Preferably, the lower insulating film 170 may be formed of one of a nitride film, an oxynitride film, and polycrystalline silicon, and the middle insulating film 180 and the upper insulating film 190 may be an oxide film and a nitride film, respectively.

The middle insulating layer 180 is a material layer for protecting the lower insulating layer 170 when all of the upper insulating layer 190 is removed in a subsequent process. Therefore, when the upper insulating film 190 and the lower insulating film 170 is a material film having a select ratio to each other, the middle insulating film 180 may not be formed.

Referring to FIG. 6, the upper, middle, and lower insulating layers 190, 180, and 170 are anisotropically etched in sequence until the surface insulating layer 150 is exposed. Accordingly, the upper insulating layer 190 forms an upper spacer 195 having a conventional shape. In contrast, the middle and lower insulating layers 180 and 170 form an L-shaped central spacer 185 and a lower spacer 175, respectively.

In this case, both the lower spacer 175 and the middle spacer 185 having an L shape have horizontal protrusions disposed under the upper spacer 195. That is, the middle spacer 185 is disposed on the horizontal protrusion of the lower spacer 175, and the upper spacer 195 is disposed on the horizontal protrusion of the middle spacer 185.

As an etching process for forming the middle and lower spacers 185 and 175, an isotropic etching method may be used. However, at least the etching process for forming the upper spacers 195 is performed by an anisotropic etching method.

Referring to FIG. 7, the upper spacer 195 is removed using an etch recipe having an etch selectivity with respect to the middle spacer 185 and the surface insulating layer 150. Thereafter, the middle spacer 185 is removed using an etch recipe having an etch selectivity with respect to the lower spacer 175 and the gate pattern 140.

Removing the upper spacers 195 and the middle spacers 185 is preferably performed by an isotropic etching method. When the middle spacer 185 is an oxide film, the surface insulating film 150 and the gate oxide film 110, which are similarly oxide films, may also be etched in a process of removing the middle spacer 185. Accordingly, in the isotropic etching method, the surface insulating layer pattern 155 and the gate oxide layer pattern 115 forming the undercut region are formed under the lower spacer 175 as shown. As a result, the upper surface of the gate pattern 140 and the semiconductor substrate 100 next to the lower spacer 175 are exposed. In addition, for the same reason, the surface insulating layer pattern 155 forms an upper surface lower than the gate pattern 140.

A high concentration ion implantation process using the gate pattern 140 and the lower spacer 175 as an ion implantation mask is performed on the resultant from which the middle spacer 185 is removed. Accordingly, a high concentration impurity region 200 is formed in the semiconductor substrate 100 next to the lower spacer 175. At this time, the horizontal protrusion of the lower spacer 175 serves to reduce the energy of ions implanted in the high concentration ion implantation process. Accordingly, an impurity region having a concentration lower than that of the high concentration impurity region 200, that is, a medium impurity region 205 is formed under the horizontal protrusion of the lower spacer 175.

The impurity concentration of the heavy impurity region 205 is determined by the thickness of the horizontal protrusion of the lower spacer 175, that is, the thickness of the lower insulating layer 170. Therefore, the thickness of the lower insulating layer 170 is formed in consideration of the impurity concentration desired to be formed in the medium concentration impurity region 205.

In addition, the distance between the high concentration impurity region 200 and the gate pattern 140 is determined by the length of the horizontal protrusion of the lower spacer 175. The length of the horizontal protrusion of the lower spacer 175 is determined by the thickness of the middle insulating layer 180 and the upper insulating layer 190.

However, when the upper spacers 195 and the lower spacers 175 are formed of the same material film, the horizontal protrusions of the lower spacers 175 are removed during the process of removing the upper spacers 195 using an isotropic etching method. Sidewalls are also etched. Accordingly, the thickness of the middle and upper insulating layers 180 and 190 may be determined in consideration of the length of the horizontal protrusions of the lower spacers 175 recessed during the removal of the upper spacers 195.

Referring to FIG. 8, a conventional silicide forming process may be performed to form junction region silicide 210 and gate silicide 215 on upper surfaces of the exposed high concentration impurity region 200 and the gate pattern 140, respectively. do.

The junction region silicide 210 and the gate silicide 215 may be one of cobalt silicide, nickel silicide, or tungsten silicide. In addition, as described above, since the surface insulating layer pattern 155 has a lower top surface than the gate pattern 140, the silicide forming process ensures a wider reaction area on the gate pattern 140. As a result, the gate silicide 215 may be stably formed without causing a phenomenon such as breaking due to miniaturization of the gate pattern 140.

9 is a perspective view illustrating a MOS transistor according to a preferred embodiment of the present invention.

Referring to FIG. 9, an isolation layer pattern 500 defining an active region is disposed in a predetermined region of the semiconductor substrate 100. The gate oxide pattern 115 is disposed on the predetermined region of the active region.

A T-shaped gate pattern 140 having an undercut region is disposed on the gate oxide layer pattern 115 while crossing the device isolation layer pattern 500. A gate silicide 215 may be further disposed on the gate pattern 140.

A lower spacer 175 having a horizontal protrusion extending above the gate oxide layer pattern 115 is disposed on a side surface of the gate pattern 140. A surface insulating layer pattern 155 is interposed between the lower spacer 175 and the gate pattern 140, and between the lower spacer 175 and the gate oxide layer pattern 115. In particular, the surface insulating layer pattern 155 fills the undercut region of the gate pattern 140 together with the lower spacers 175. To this end, the lower spacer 175 may further have a horizontal extension extending to the undercut area.

A high concentration impurity region 200 spaced apart from the gate pattern 140 is disposed on the semiconductor substrate 100 next to the lower spacer 175. The junction region silicide 210 may be disposed on the high concentration impurity region 200.

The low concentration impurity region 160 is disposed in the semiconductor substrate 100 under the undercut region of the gate pattern 140. In addition, a heavy impurity region 205 is disposed in the semiconductor substrate 100 under the horizontal protrusion of the lower spacer 175. That is, the medium concentration impurity region 205 is disposed between the high concentration and low concentration impurity regions 200 and 160.

According to the present invention, a medium impurity region is formed between a high concentration and a low concentration impurity region by using an L-shaped spacer formed on the side surface of the T-shaped gate electrode. Accordingly, the advantages of a transistor having a T-shaped gate electrode, that is, a decrease in capacitance, a decrease in channel length, an increase in gate cross-sectional area, and an advantage of a heavily doped impurity region, that is, a decrease in source / drain resistance R _sd Can be achieved at the same time.

Claims (20)

Forming a T-shaped gate electrode on the semiconductor substrate; Performing a low concentration ion implantation process using the gate electrode as an ion implantation mask to form low concentration impurity regions on semiconductor substrates on both sides of the gate electrode; Forming an L-shaped lower spacer, an L-shaped middle spacer, and an upper spacer sequentially stacked on the low concentration impurity region on the side of the gate electrode; Removing the upper and middle spacers to expose the lower spacers; And And forming a high concentration impurity region and a medium concentration impurity region by performing a high concentration ion implantation process on the semiconductor substrate to which the lower spacers are exposed. The method of claim 1, Forming the T-shaped gate electrode Forming a lower conductive layer pattern and an upper conductive layer pattern sequentially stacked on the semiconductor substrate; And And selectively etching the lower conductive layer pattern to form an undercut region at a lower edge of the upper conductive layer pattern. The method of claim 2, The lower conductive layer pattern and the upper conductive layer pattern may be formed of a material layer having an etching selectivity with each other. The method of claim 2, The lower conductive layer pattern is formed of silicon germanium or titanium nitride manufacturing method of the MOS transistor. The method of claim 2, And the upper conductive layer pattern is formed of polycrystalline silicon or tungsten. The method of claim 2, Selectively etching the lower conductive layer pattern is performed by an isotropic etching method. The method of claim 1, And conformally forming a surface insulating film over the entire surface of the semiconductor substrate including the gate electrode. The method of claim 1, And the lower spacers are formed of one of a nitride film, an oxynitride film, and polycrystalline silicon. The method of claim 1, And the middle spacers are formed of a material film having an etch selectivity with respect to the lower spacers. The method of claim 1, And the upper spacers are formed of a material film having an etch selectivity with respect to the middle spacers. The method of claim 1, Forming the upper, middle and lower spacers Conformally forming a lower insulating film, a middle insulating film, and an upper insulating film sequentially stacked on a front surface of the semiconductor substrate including the T-shaped gate electrode; And And sequentially etching the upper, middle, and lower insulating films, wherein at least the upper insulating film is etched by an anisotropic etching method. The method of claim 1, And forming a gate oxide film on the entire surface of the semiconductor substrate before forming the gate electrode. The method of claim 1, And forming a junction region silicide and a gate silicide on the high concentration impurity region and the upper conductive layer pattern, respectively, after performing the high concentration ion implantation process. A T-shaped gate electrode disposed on the semiconductor substrate; An L-shaped lower spacer disposed on a side of the gate electrode and covering an upper portion of the semiconductor substrate; Low concentration impurity regions formed on semiconductor substrates on both sides of the gate electrode; A high concentration impurity region formed in the semiconductor substrate on the side of the lower spacer; And And a heavy impurity region disposed between the high concentration impurity region and the low concentration impurity region. The method of claim 14, The gate electrode may include a lower conductive layer pattern and an upper conductive layer pattern that are sequentially stacked, and the upper conductive layer pattern may have a wider width than the lower conductive layer pattern to have an undercut region thereunder. transistor. The method of claim 15, And the lower spacers further include a horizontal extension part filling the undercut region. The method of claim 15, And the lower conductive layer pattern and the upper conductive layer pattern are formed of a material layer having an etch selectivity with each other. The method of claim 15, The lower conductive layer pattern is a MOS transistor, characterized in that the silicon germanium or titanium nitride. The method of claim 15, And the upper conductive layer pattern is polycrystalline silicon or tungsten. The method of claim 14, And a surface insulating film interposed between the gate electrode and the lower spacer.