JP2003273349A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having satisfactory element characteristics. <P>SOLUTION: This method for manufacturing a semiconductor comprises a step (a) for forming a side wall insulating layer 24 on the side wall of a gate electrode 14 formed through a gate insulating layer 12 at the upper part of a semiconductor layer and a step (b) for forming a cover layer 32 at least at the upper part of the side wall insulating layer 24, and for introducing impurity to the semiconductor layer, so that first impurity layers 16 and 18 being a source area or drain area can be formed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having good element characteristics.

[0002]

BACKGROUND ART At present, miniaturization and high integration of semiconductor devices are rapidly progressing. Along with this, for example, MIS (Metal
In a semiconductor device having an Insulator Semiconductor structure, a so-called punch-through phenomenon easily occurs due to a short channel length. The occurrence of punch through affects the transistor characteristics such as the threshold voltage of the transistor and the amount of off leak current. Therefore, in order to obtain good transistor characteristics, it is important to suppress the occurrence of punch through while achieving miniaturization and high integration of the semiconductor device.

[0003]

In order to suppress the occurrence of such punch through, the width of the sidewall insulating film may be increased. In this case, when the semiconductor layer between the gate electrode and the element isolation region or between the adjacent gate electrodes has a wiring contact with the impurity layer, the area of the impurity layer with which the wiring can come into contact depends on the width of the sidewall insulating film. Will decrease. In order to prevent this, if the distance between adjacent sidewalls is increased, the element area increases, and it is not possible to achieve high integration of the element.

An object of the present invention is to provide a method for manufacturing a semiconductor device having good element characteristics while achieving high integration of elements.

[0005]

According to a method of manufacturing a semiconductor device of the present invention, (a) a sidewall insulating layer is formed on a sidewall of a gate electrode formed above a semiconductor layer with a gate insulating layer interposed therebetween, (B) forming a cover layer above at least the sidewall insulating layer, and then introducing an impurity into the semiconductor layer to form a first impurity layer to be a source region or a drain region.

According to the method of manufacturing a semiconductor device of the present invention,
By forming the cover film above the sidewall insulating layer, the width of the sidewall insulating film can be apparently widened when the first impurity layer is formed. Accordingly, the distance between the first impurity layers can be increased without changing the size of the entire device. Here, by increasing the distance between the first impurity layers, it is possible to increase the area of the surface of the first impurity layer that the wiring can contact and increase the channel length. Therefore, the wiring contact to the first impurity layer can be improved, and the punch-through can be suppressed. As a result, it is possible to increase the threshold voltage of the transistor and reduce the amount of off-leakage current while achieving miniaturization of the element, and it is possible to obtain a transistor having excellent element characteristics.

By adjusting the film thickness of the cover layer, the position where the first impurity layer is formed can be adjusted. That is, the channel length can be adjusted by the film thickness of the cover layer.

The method of manufacturing a semiconductor device of the present invention can take the following aspects (1) to (5).

(1) In (b), the cover layer can be formed on the entire surface of the semiconductor layer.

In this case, further after (b),
(C) Annealing in a state where the cover layer is formed can be included. As a result, it is possible to suppress the outward diffusion of the impurities from the first impurity layer into the vapor phase. Accordingly, the resistance value of the first impurity layer can be prevented from increasing, and it is not necessary to introduce an excessive amount of the impurity when forming the first impurity layer.

(2) Further, before (a),
(E) After forming the gate electrode above the semiconductor layer, by introducing an impurity of the same conductivity type as the impurity introduced in (b) into the semiconductor layer, a third impurity layer to be at least an LDD region Can be formed. This makes it possible to obtain a device in which the increase in resistance of the impurity layer is further suppressed.

(3) Furthermore, after (a) and before (b), (d) at least the same impurities as those introduced in (b) into the semiconductor layer using the sidewall insulating film as a mask. The method may include forming a second impurity layer sandwiched between the first impurity layer and the third impurity layer by introducing a conductivity type impurity.
This makes it possible to obtain a device in which the resistance increase of the impurity layer is further suppressed.

(4) The method may further comprise (f) removing the cover layer by etching after (b) or (c).

In this case, in (f), the cover layer can be removed by isotropic etching.
This allows the cover layer to be removed without damaging the surface of the semiconductor layer.

Further, in this case, after (f), it may further include (g) forming a silicide layer on the upper surface of the gate electrode and the upper surface of the semiconductor layer.

Further, in this case, further, after the step (f) or after the step (g), (h) an interlayer insulating layer is formed on the entire surface, and (i) the interlayer insulating layer is etched. Forming an opening penetrating the interlayer insulating layer and connecting to the impurity layer, and (j) forming a conductive layer in the opening.

(5) Further, in any one of (1) to (3) above, (h) an interlayer insulating layer is formed on the entire surface,
(I) etching the interlayer insulating layer and the cover layer to form an opening penetrating the interlayer insulating layer and the cover layer and connecting to the impurity layer;
(J) forming a conductive layer in the opening.

In this case, in the above (i), after the interlayer insulating layer is removed by the first etching under the etching condition that the etching rate of the interlayer insulating layer and the etching rate of the cover layer are different, the first etching is performed. The cover film can be removed under etching conditions different from etching.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] 1. Structure of Semiconductor Device FIG. 1 is a sectional view schematically showing a semiconductor device 100 according to the first embodiment to which the present invention is applied.

The semiconductor device 100 of this embodiment shows an example in which the semiconductor substrate 10 is used as the semiconductor layer. As shown in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 10 and a gate electrode 14. The gate electrode 14 is formed on the semiconductor substrate 10 via the gate insulating layer 12. More specifically, the gate electrode 14 is the semiconductor substrate 1
0 denotes the first impurity layers 16 and 1 which become the source and drain regions
8 is formed. A sidewall insulating layer 24 is formed on the sidewall of the gate electrode 14.

The gate electrode 14 is made of, for example, polycrystalline silicon which is highly doped with impurities such as boron. The gate electrode 12 is made of, for example, a silicon oxide layer or a silicon nitride oxide layer. Note that the materials forming the gate insulating layer 12 and the gate electrode 14 are not limited to those described above, and known materials can be used.

The first impurity layers 16 and 18 are formed on the semiconductor substrate 1
It is formed at a predetermined interval in the element region surrounded by the two element isolation regions 20 formed in 0. This first
The impurity layers 16 and 18 function as a source or drain region. Furthermore, each of the first impurity layers 16 and 18 may be formed in a region separated from the sidewall insulating layer 24 by a predetermined distance. Further, each of the first impurity layers 16 and 18 may be formed in a region including below the sidewall insulating layer 24 or may extend to a region including below the gate insulating layer 12. In semiconductor device 100 of the present embodiment, as shown in FIG. 1, each of first impurity layers 16 and 18 is formed in a region separated from sidewall insulating layer 24 by a predetermined distance X. That is, in the semiconductor substrate 10, from the place closest to the first impurity layer 16 (or the first impurity layer 18) on the installation surface of the sidewall insulating layer 24,
Of the first impurity layers 16 and 18, the sidewall insulating layer 2
The first impurity layers 16 and 18 are formed so that the distance to the portion closest to 4 is X. The distance X can be adjusted by forming the cover layer 32 to have a predetermined film thickness in the manufacturing process of the semiconductor device 100 (see FIG. 6) described later.

A silicide layer 88 is formed on the surfaces of the first impurity layers 16 and 18, and a silicide layer 98 is formed on the upper surface of the gate electrode 14, if necessary.

Further, another semiconductor device 100 (not shown) having a similar structure may be formed adjacent to the semiconductor device 100 in the element region surrounded by the element isolation region 20. One of the first impurity layers 16 and 18 of the one semiconductor device 100 is connected to the other semiconductor device 1
00 may be connected to either one of the first impurity layers 16 and 18. In this case, the first impurity layer 16 or 1 thus connected by one wiring contact
8 can be simultaneously connected, and the semiconductor device can be further miniaturized. 2. Method for Manufacturing Semiconductor Device Semiconductor Device 100 According to One Embodiment to which the Present Invention is Applied
An example of the manufacturing method will be described with reference to FIGS. FIG. 1 is a sectional view schematically showing a semiconductor device 100 manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 2 to 8 are cross-sectional views schematically showing one manufacturing process of the semiconductor device 100 shown in FIG. 1, and each corresponds to the cross section shown in FIG.

(1) First, as shown in FIG. 2, an example using a semiconductor substrate 10 as a semiconductor layer will be described. The gate insulating layer 12 and the gate electrode 14 are formed on the semiconductor substrate 10. For example, the semiconductor substrate 10 in the element region surrounded by the element isolation regions 20 is oxidized by, for example, a thermal oxidation method to form an insulating layer (not shown). Then, after forming a conductive layer (not shown) made of, for example, a P-type polycrystalline silicon layer into which boron is introduced,
The insulating layer and the conductive layer are patterned into a predetermined shape by photolithography.

(2) Next, as shown in FIG. 3, the sidewall insulating film 24 is formed on at least the sidewall of the gate electrode 14.
To form. As shown in FIG. 3, the sidewall insulating layer 24 may be formed on the sidewalls of the gate insulating layer 12 and the gate electrode 14. The sidewall insulating layer 24 is formed, for example, by forming an insulating layer (not shown) on the entire surface so as to cover the upper surface and the side wall of the gate electrode 14 and then performing anisotropic etching.

The material of the sidewall insulating layer 24 is not particularly limited, but it can be formed of, for example, silicon oxide, silicon nitride or polycrystalline silicon.

(3) Next, as shown in FIG. 4, a cover layer 32 is formed. The cover layer 32 is formed on at least the sidewall insulating layer 24. Cover layer 32
Is formed by, for example, the CVD method. In this embodiment, as shown in FIG. 4, the cover layer 32 is formed over the entire surface of the semiconductor substrate 10. The film thickness of the cover layer 32 is the same as that of the first impurity layers 16 and 1 formed in a later step.
It becomes one of the factors that determine the position of 8 (details will be described later).

In the present embodiment, the case where the cover layer 32 is made of silicon oxide will be described, but the material of the cover layer 32 is not particularly limited. However, in the case where a step of leaving the sidewall insulating layer 24 and removing the cover layer 32 by etching is included in a later step as in the present embodiment, the cover layer 32 is etched under the etching conditions of the cover layer 32. The cover layer 32 may be formed so that the etching rate thereof is different from that of the sidewall insulating layer 24. That is,
Each of the cover layer 32 and the sidewall insulating layer 24 is made of a material having a high etching selection ratio between the cover layer 32 and the sidewall insulating layer 24 in the step of etching the cover layer 32. For example, the sidewall insulating layer 2
When 4 is made of silicon nitride, the cover layer 32 can be made of silicon oxide. Alternatively, when the sidewall insulating layer 24 is made of polycrystalline silicon, the cover layer 32 can be made of silicon nitride. In any case, the cover layer 32 is selectively removed by using an etching condition in which the etching rate of the cover layer 32 is higher than the etching rate of the sidewall insulating layer 24 under a predetermined etching condition. You can The etching conditions used here, such as the type of etchant and the type and ratio of the added gas, are not particularly limited as long as the above-described conditions are satisfied.

(4) Next, as shown in FIG. 5, impurities are introduced into the semiconductor substrate 10 by ion implantation. Thereby, as shown in FIG. 6, the first impurity layers 16 and 18 to be the source region or the drain region are formed on the semiconductor substrate 10. When the conductivity type of the semiconductor substrate 10 is P-type, N-type impurities having the opposite conductivity type may be introduced into the first impurity layer. In this step, when the sidewall insulating layer 24 and the portion of the cover layer 32 formed on the sidewall insulating layer 24 are referred to as a region A (see FIG. 5), this region A functions as a mask. That is, in the region A, the semiconductor substrate 10
The thickness of the layers (sidewall insulating layer 24 and cover layer 32) in the direction perpendicular to the surface on which the gate insulating layer 12 is formed (Z direction shown in FIG. 5) is the same as the semiconductor substrate 1
The cover layer 32 is formed to be larger than the film thickness of the cover layer 32 formed on the upper surface of 0. Therefore, the introduction of impurities into the region of the semiconductor substrate 10 located below the region A is prevented. As a result, as shown in FIG. 6, the first impurity layer 1 is formed in the region separated from the sidewall insulating layer 24 by a predetermined distance.
6, 18 may be formed.

(5) Next, as shown in FIG. 7, annealing is performed with the cover layer 32 formed on the entire surface.

(6) Next, as shown in FIG. 8, the cover layer 32 is removed. The cover layer 32 can be removed by isotropic etching such as wet etching. The isotropic etching can increase the selection ratio between the cover layer 32 and the semiconductor layer (semiconductor substrate 10) as compared with the anisotropic etching. Therefore, by removing the cover layer 32 by isotropic etching, the cover layer 32 can be removed with less damage to the surface of the semiconductor substrate 10. Examples of the isotropic etching include wet etching and chemical dry etching.

Next, a metal for forming a silicide may be entirely deposited (not shown). The metal for forming the silicide is, for example, titanium or cobalt. In this case, the metal formed on the semiconductor substrate 10 and the gate electrode 14 is subjected to a silicidation reaction to form a silicide layer 88 on the upper surface of the semiconductor substrate 10 and the upper surfaces of the source and drain regions. A silicide layer 98 can be formed on the upper surface of the drain region (see FIG. 1). Through the above steps, the semiconductor device 100 shown in FIG. 1 is obtained. (7) Further, the interlayer insulating layer 60 may be formed on the entire surface. After that, an opening 46 penetrating the interlayer insulating layer 60 is formed on the first impurity layer 16, a conductive layer is formed in the opening 46, and then a wiring layer is formed on the conductive layer.
A wiring contact for the first impurity 16 can be formed.

The advantages of the method of manufacturing the semiconductor device 100 according to this embodiment are as follows.

(A) In (3) above, after forming the cover layer 32 on at least the sidewall insulating layer 24, in (4) above, the sidewall insulating layer out of the sidewall insulating layer 24 and the cover layer 32. The first impurity layers 16 and 18 can be formed by introducing impurities into the semiconductor substrate 10 by using the portion formed on 24 as a mask. As a result, between the gate electrode 14 forming the semiconductor device 100 of the present embodiment and the gate electrode 14 forming the element isolation region 20 or another semiconductor device 100 (not shown) adjacent to the semiconductor device 100. The distance between the first impurity layer 16 and the first impurity layer 18 can be increased without changing the distance. Where the first
Since the channel length can be increased by increasing the distance between the impurity layer 16 and the first impurity layer 18,
The occurrence of so-called punch through can be suppressed.
Further, the contact area of the wiring with the first impurity layer 16 can be increased. As a result, it is possible to increase the threshold voltage of the transistor and reduce the amount of off-leakage current while achieving miniaturization of the element, and it is possible to obtain a transistor having excellent element characteristics.

(B) Further, in the above (3), by adjusting the film thickness of the cover layer 32, the first impurity layer 1
The position where 6, 18 are formed can be adjusted. That is, the channel length can be adjusted by the film thickness of the cover layer 32.

(C) In the present embodiment, in the above (3), the cover layer 32 is also formed on the exposed surface of the semiconductor substrate 10 (see FIG. 4). By performing the annealing in the above (5) in this state (see FIG. 7), it is possible to suppress the outward diffusion of impurities from the first impurity layers 16 and 18 to the vapor phase. This allows
The resistance of the first impurity layers 16 and 18 can be maintained.

In the above embodiment, when the semiconductor device 100 is an N-type MOS, the impurities introduced into the first impurity layers 16 and 18 are N-type impurities, and the semiconductor substrate 10 and the gate electrode. The impurity introduced into 14 is a P-type impurity, but replacement of these in each layer does not depart from the spirit of the present invention. That is,
The semiconductor device 100 may be a P-type MOS. This also applies to the second to fourth embodiments described later.

[Second Embodiment] 1. Structure of Semiconductor Device FIG. 9 is a sectional view schematically showing a semiconductor device 200 according to the second embodiment to which the present invention is applied.

The semiconductor device 200 of this embodiment is shown in FIG.
As shown in, the cover layer 32 is formed on the semiconductor substrate 10, the sidewall insulating layer 24, and the gate electrode 14, and thus the semiconductor device 100 according to the first embodiment.
Has a different structure from.

Further, in the semiconductor device 200 of the present embodiment, the interlayer insulating layer 60 is formed on the cover layer 32, and the opening 4 penetrating the interlayer insulating layer 60 and the cover layer 32.
6 is formed, and the conductive layer 40 is formed in the opening 46. The conductive layer 40 is formed on the first impurity layer 16 and electrically connects the first impurity layer 16 and the wiring layer 42.

The semiconductor device 200 of the present embodiment has substantially the same structure as the semiconductor device 100 according to the first embodiment except for the above points. Therefore, components having substantially the same functions as those of the semiconductor device 100 according to the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. 2. Method for manufacturing semiconductor device Semiconductor device 2 according to second embodiment to which the present invention is applied
An example of the method of manufacturing 00 will be described with reference to FIGS. FIG. 9 is a sectional view schematically showing a semiconductor device 200 manufactured by the method of manufacturing a semiconductor device according to the second embodiment of the present invention. 10 and 11 are similar to FIG.
FIG. 7 is a cross sectional view schematically showing a manufacturing step for semiconductor device 200 of the present exemplary embodiment shown in FIG.

The semiconductor device 200 according to the second embodiment.
Can be formed by using the same steps as the manufacturing process of the semiconductor device 100 according to the above-described first embodiment up to the intermediate manufacturing process. Specifically, in the manufacturing process of the semiconductor device 100 according to the first embodiment, after the annealing (see FIG. 7), the cover layer 32 is not removed and the entire surface is removed as shown in FIG. Then, an interlayer insulating layer 60 is formed. In this case, the interlayer insulating layer 60 has an etching rate different from the etching rate of the cover layer 32 under the conditions for etching the interlayer insulating layer 60. That is, the cover layer 32 and the interlayer insulating layer 60 are each made of a material having a high etching selection ratio between the cover layer 32 and the interlayer insulating layer 60 under the etching conditions of the interlayer insulating layer 60. That is, for example, when the cover layer 32 is made of silicon nitride, the interlayer insulating layer 60 is made of silicon oxide.

Next, as shown in FIG. 11, an opening 46 penetrating the interlayer insulating layer 60 and the cover layer 32 is formed on the first impurity layer 16. In the present embodiment, since the etching rate of the interlayer insulating layer 60 and the etching rate of the cover layer 32 are different, the interlayer insulating layer 60 is first etched under the etching conditions that are higher than the etching rate of the cover layer 32. The insulating layer 60 is selectively etched. Then, when the cover layer 32 is exposed, the etching conditions are changed to conditions for etching the cover layer 32, and the cover layer 32 is etched. That is, the cover layer 32 functions as a stopper for preventing the layer below the cover layer 32 from being etched. As long as the above conditions are met,
Etching conditions such as the type of etchant used here are not particularly limited.

Next, as shown in FIG. 9, after forming the conductive layer 40 in the opening 46, the wiring layer 42 is formed on the conductive layer 40.
To form. Through the above steps, the semiconductor device 200 shown in FIG. 9 is obtained.

The advantages of the method of manufacturing the semiconductor device 200 according to the present embodiment are almost the same as those of the method of manufacturing the semiconductor device 100 according to the first embodiment described above, and further have the following advantages.

Under the etching conditions of the interlayer insulating film 60, the etching rate of the interlayer insulating layer 60 is changed to the cover layer 32.
The etching rate is different from that of the cover layer 32.
Has a function as a stopper when the interlayer insulating layer 60 is etched. That is, when the interlayer insulating layer 60 is etched, the etching can be stopped when the cover layer 32 is exposed. As a result, overetching can be avoided.

Since the cover layer 32 also functions as a stopper, the step of separately forming a layer for the stopper can be omitted.

[Third Embodiment] 1. Structure of Semiconductor Device FIG. 12 is a sectional view schematically showing a semiconductor device 300 according to the third embodiment of the invention.

The semiconductor device 300 according to the present embodiment is shown in FIG.
As shown in FIG. 2, in the semiconductor substrate 10, the first impurity layers 16a and 18a
Impurity layers 16b, 18b and third impurity layers 16c, 1
8c is formed, which has a different structure from the semiconductor device 100 of the first embodiment. Here, the second impurity regions 16b and 18b are not necessarily required, and may be composed of only the first and third impurity layers 16a, 18a, 16c and 18c.

The semiconductor device 300 according to the present embodiment has substantially the same structure as the semiconductor device 100 according to the first embodiment except for the above points. Therefore, components having substantially the same functions as those of the semiconductor device 100 according to the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The first impurity layers 16a and 18a are respectively
It is formed similarly to the first impurity layers 16 and 18 constituting the semiconductor device 100 of the first embodiment. The third impurity layers 16c and 18c are so-called LDD (Long Doped Drain).
And, if necessary, they are formed in regions of the semiconductor substrate 10 that are closer to the lower side of the gate electrode than the first impurity layers 16 and 18. In addition, the second impurity layer 1
6b is formed between the first impurity layer 16a and the third impurity layer 16c, and the second impurity layer 18b is formed between the first impurity layer 18a and the third impurity layer 18c. here,
The second impurity regions 16b and 18b are not always necessary, and the first and third impurity layers 16a, 18a, 16c, 1
It may be composed of only 8c.

The concentration of these impurity layers is formed so that the third impurity layer ≦ the second impurity layer ≦ the first impurity layer or the third impurity layer <the second impurity layer ≦ the first impurity layer. In addition, the depth of these impurity layers is less than the third impurity layer <
The second impurity layer <the first impurity layer is formed.
In addition, the first impurity layers 16a and 18a and the second impurity layer 16
b, 18b and the third impurity layers 16c, 18c are impurity layers of the same conductivity type.

According to the semiconductor device 300 of the present embodiment, the third impurity layers 16c and 18c are formed in addition to the first impurity layers 16a and 18a, so that the resistance increase of the element can be suppressed. it can. Further, since the second impurity layers 16b and 18b are formed, it is possible to suppress an increase in the resistance of the element due to the distance between the source region and the drain region from the region below the gate insulating film. As a result, the characteristics of the device can be maintained. 2. Manufacturing Method of Semiconductor Device Next, an example of a manufacturing method of the semiconductor device 300 according to the third embodiment to which the present invention is applied will be described with reference to FIGS.
Will be explained. 13 to 20 are sectional views schematically showing one manufacturing process of the semiconductor device 300 of the present embodiment shown in FIG.

A semiconductor device 300 according to the third embodiment
Up to an intermediate manufacturing process, can be formed using substantially the same steps as the manufacturing process of the semiconductor device 100 according to the first embodiment described above. Specifically, the first
Similar to the manufacturing process of the semiconductor device 100 according to the embodiment (see FIG. 2), the gate insulating layer 12 and the gate electrode 14 are formed. The subsequent steps will be described below.

(1) First, using the gate electrode 14 as a mask, ions are implanted to introduce impurities into the semiconductor substrate 10. The impurities are of the same conductivity type as the impurities introduced at the time of forming the first impurity layers 16a and 18a to be the source and drain regions. As a result, as shown in FIG. 13, in the semiconductor substrate 10, the third impurity layers 16c and 18 are sandwiched so as to sandwich the gate electrode 14.
form c.

(2) Next, as shown in FIG. 14, a sidewall insulating layer 24 is formed on at least the sidewall of the gate electrode 14. The sidewall insulating layer 24 can be formed by the method described in the first embodiment.

(3) Next, impurities may be introduced into the semiconductor substrate 10 by performing ion implantation using at least the sidewall insulating layer 24 as a mask. This impurity is the first impurity layer 1 which becomes the source and drain regions.
The impurities are of the same conductivity type as the impurities introduced at the time of forming 6a and 18a. As a result, as shown in FIG.
In the semiconductor substrate 10, the third impurity layers 16c and 18c
The second impurity layers 16b and 18b can be formed in a region farther from the gate electrode 14. In this step, the second impurity layers 16b and 18b are changed to the third impurity layer 1
Impurities are introduced so as to be deeper than 6c and 18c.

(4) Next, as shown in FIG. 16, a cover layer 32 is formed by, eg, CVD method. The method of forming the cover layer 32, and the shape, thickness, and material of the cover layer 32 are the same as those described in the section of the first embodiment.

(5) Next, as shown in FIG. 17, the second impurity layer 16b is formed on the semiconductor substrate 10 by ion implantation.
By introducing impurities of the same conductivity type as 18b and the third impurity layers 16c, 18c, the first impurity layers 16a, 18
a is formed. In this step, similar to the step (4) of the first embodiment (see FIG. 5) described above, the area A
(See FIG. 17) functions as a mask. This allows
As shown in FIG. 18, the first impurity layers 16 a and 18 a forming the source region or the drain region are formed on the semiconductor substrate 10.
Is formed. The first impurity layers 16a and 18a to be the source region or the drain region may be formed in a region separated from the sidewall insulating layer 24 by a predetermined distance. Here, the method of forming the first impurity layers 16a and 18a is the same as the method of forming the first impurity layers 16 and 18 in the manufacturing method of the first embodiment described above.

The steps after (6) are the same as in the manufacturing method of the first embodiment described above. That is, as shown in FIG. 19, annealing is performed with the cover layer 32 formed on the entire surface. Next, as shown in FIG. 20, after removing the cover layer 32, a silicide layer 88 may be formed on the upper surface of the semiconductor substrate 10 and a silicide layer 98 may be formed on the upper surface of the gate electrode 14 (see FIG. 12). . Through the above steps, the semiconductor device 300 shown in FIG. 12 is obtained.

(7) Further, the interlayer insulating layer 60 may be formed on the entire surface. After that, an opening 46 penetrating the interlayer insulating layer 60 is formed on the first impurity layer 16, a conductive layer is formed in the opening 46, and then a wiring layer is formed on the conductive layer. A wiring contact for the impurity 16 can be formed.

The advantages of the method of manufacturing the semiconductor device 300 according to the present embodiment are substantially the same as those of the method of manufacturing the semiconductor device 100 according to the first embodiment described above, and further have the following advantages.

According to the method of manufacturing the semiconductor device 300 of the present embodiment, the resistance of the impurity layer is further increased by using the same steps as those used in the method of manufacturing the semiconductor device 100 of the first embodiment. A suppressed device can be obtained.

[Fourth Embodiment] 1. Structure of Semiconductor Device FIG. 21 is a sectional view schematically showing a semiconductor device 400 according to the fourth embodiment of the invention.

The semiconductor device 400 of this embodiment is shown in FIG.
1, the cover layer 32 is formed on the semiconductor substrate 10, the sidewall insulating layer 24, and the gate electrode 14, and thus the semiconductor device 20 according to the second embodiment.
It has the same structure as 0. In addition, the first impurity layer 16a,
In addition to 18a, second impurity layers 16b and 18b and third impurity layers 16c and 18c are formed.
It has the same structure as the semiconductor device 300 of the embodiment. Here, the second impurity regions 16b and 18b are not always necessary, and the first and second impurity layers 16a and 18b are not necessary.
It may be composed of only a, 16c and 18c.

The semiconductor device 400 of the present embodiment has substantially the same structure as the semiconductor device 100 according to the first embodiment except for the above points. Therefore, components having substantially the same functions as those of the semiconductor device 100 according to the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. 2. Method for Manufacturing Semiconductor Device The semiconductor device 400 according to the present embodiment is the same as the semiconductor device 3 according to the third embodiment until the manufacturing process in the middle.
It can be formed by using steps substantially similar to the manufacturing process of No. 00. Specifically, in the manufacturing process of the semiconductor device 300 according to the third embodiment, after performing the annealing (see FIG. 19), the cover layer 32 is not removed and the second embodiment is concerned. By the same method as the manufacturing process (see FIGS. 10 and 11), after forming the interlayer insulating layer 60, the conductive layer 40 and the wiring layer 42 are formed.

The advantages of the method of manufacturing the semiconductor device 400 according to the present embodiment are almost the same as those of the method of manufacturing the semiconductor devices 100, 200, 300 according to the above-described first to third embodiments. Is omitted.

The present invention is not limited to the above-mentioned embodiment, but various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations having the same function, method and result, or configurations having the same object and result). Further, the invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Further, the present invention includes a configuration having the same effects as the configurations described in the embodiments or a configuration capable of achieving the same object. Further, the invention includes configurations in which known techniques are added to the configurations described in the embodiments.

For example, although the bulk semiconductor substrate is used as the semiconductor layer in the above-mentioned embodiment, the semiconductor layer of the SOI substrate may be used.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a semiconductor device according to a first embodiment to which the present invention is applied.

FIG. 2 is a cross-sectional view that schematically shows one step of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view that schematically shows one step of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 4 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 5 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 6 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 7 is a cross-sectional view that schematically shows one step of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 8 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 9 is a sectional view schematically showing a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view that schematically shows one step of the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 11 is a cross-sectional view that schematically shows one step of the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 12 is a sectional view schematically showing a semiconductor device according to a third embodiment of the invention.

FIG. 13 is a cross-sectional view that schematically shows one step of the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 14 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 15 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 16 is a cross-sectional view that schematically shows one step of the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 17 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 18 is a cross-sectional view that schematically shows one step of the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 19 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 20 is a cross-sectional view that schematically shows one step of the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 21 is a sectional view schematically showing a semiconductor device according to a fourth embodiment of the present invention.

[Explanation of symbols]

12 Gate insulating layer 14 Gate electrode 16, 16a, 18, 18a First impurity layer 16b, 18b Second impurity layer 16c, 18c Third impurity layer 20 element isolation region 32 cover layer 24 Sidewall insulation layer 40 Conductive layer 42 wiring layer 46 opening 60 Interlayer insulation layer 88,98 Silicide layer 100, 200, 300, 400 Semiconductor device

Continued front page    F-term (reference) 5F140 AA06 AA10 AA18 AA24 AA39                       AC36 BA01 BD09 BE07 BF04                       BF11 BF18 BG08 BG12 BG14                       BG15 BG51 BG53 BH05 BH13                       BH14 BH15 BH18 BJ01 BJ08                       BJ25 BJ27 BJ28 BK03 BK08                       BK13 BK20 BK21 BK26 BK34                       CB01 CC01 CC03 CC08 CC12                       CF04

Claims (13)

[Claims] 1. A side wall insulating layer is formed on a side wall of a gate electrode formed above a semiconductor layer via a gate insulating layer, and a cover layer is formed at least above the side wall insulating layer. And forming a source region or a drain region by introducing impurities into the semiconductor layer.
A method of manufacturing a semiconductor device, the method including forming an impurity layer. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the cover layer is formed on the entire surface of the semiconductor layer in (b). 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: (c) annealing after the step (b) while the cover layer is formed. 4. The semiconductor device according to claim 1, further comprising: (e) forming the gate electrode above the semiconductor layer before (a), and then forming the gate electrode (b) on the semiconductor layer. A method of manufacturing a semiconductor device, comprising: forming an impurity of the same conductivity type as that introduced in 1. to form at least a third impurity layer to be an LDD region. 5. The method according to claim 4, further comprising after (a) and before (b),
(D) By introducing an impurity of the same conductivity type as the impurity introduced in (b) into the semiconductor layer using at least the sidewall insulating film as a mask, the first
Forming a second impurity layer sandwiched by an impurity layer and the third impurity layer. 6. The method of manufacturing a semiconductor device according to claim 1, further comprising (f) removing the cover layer by etching after the step (b). 7. The method according to claim 3, further comprising the step (c).
After that, (f) removing the cover layer by etching, a method for manufacturing a semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 6, wherein in step (f), the cover layer is removed by isotropic etching. 9. The semiconductor according to claim 6, further comprising: (g) forming a silicide layer on the upper surface of the gate electrode and the upper surface of the semiconductor layer after the step (f). Device manufacturing method. 10. The interlayer insulating layer according to claim 7, further comprising (h) forming an interlayer insulating layer on the entire surface after (f), and (i) etching the interlayer insulating layer. And (j) forming a conductive layer in the opening.
Manufacturing method of semiconductor device. 11. The interlayer insulating layer according to claim 9, further comprising: (h) forming an interlayer insulating layer on the entire surface after the step (g), and (i) etching the interlayer insulating layer. And forming an opening connected to the impurity layer, and (j) forming a conductive layer in the opening.
Manufacturing method of semiconductor device. 12. The method according to claim 1, further comprising (h) forming an interlayer insulating layer over the entire surface after (b), (i) the interlayer insulating layer and the cover. Etching a layer to form an opening penetrating the interlayer insulating layer and the cover layer and connecting to the impurity layer, and (j) forming a conductive layer in the opening.
Manufacturing method of semiconductor device. 13. The interlayer according to claim 3, further comprising (h) forming an interlayer insulating layer on the entire surface after (c), and (i) etching the interlayer insulating layer and the cover layer. Forming an opening penetrating the insulating layer and the cover layer and connecting to the impurity layer, and (j) forming a conductive layer in the opening.
Manufacturing method of semiconductor device.