JP2006196821A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce contact resistance in the source/drain of a field effect transistor having a fin type structure. <P>SOLUTION: In a method for manufacturing a semiconductor device: an insulating gate electrode structure having second height that is higher than first one is formed on a fin-type semiconductor region at the first height, and a sidewall insulating film is completely removed from the side of the fin-type semiconductor region by anisotropic etching and is removed by etching from the upper portion of an upper section while the upper and lower sections of both the sides of the gate electrode remain so that the upper and side surfaces of the fin-type semiconductor region are surrounded by the sidewall insulating film on both the sides of the gate electrode near the fin-type semiconductor region; and the silicide layer is formed from an upper edge to a lower one on at least exposed both sides in the fin-type semiconductor region. After an interlayer insulating film is formed, a contact hole, which exposes the silicide layer on both the sides of the fin-type semiconductor region, is formed for burying a conductive plug. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a field effect transistor having a fin-type structure and a manufacturing method thereof.
Note that a field effect transistor having a fin-type structure is generally called a Fin-FET or a double-gate Fin-FET, and a three-dimensional field effect in which the channel surface is perpendicular to the surface of the substrate. A transistor having thin wall (fin) projections perpendicular to the surface of the substrate, a gate insulating film and a gate electrode are formed on both side surfaces of the fin, and source / drain regions are formed on the fins on both sides of the gate. It has a formed structure.

  A field effect transistor having a fin-type structure has a channel surface arranged perpendicular to the substrate surface, so that the occupied area on the substrate can be reduced, dielectric separation is facilitated, and adaptability to miniaturization and high-speed operation is high. An oxide film or a cap layer such as an oxide film / nitride film stack is provided on a silicon layer of an SOI (semiconductor on insulator) substrate in which a silicon layer is arranged on an insulating film, and patterned to form silicon fins. After forming a gate insulating film such as silicon oxide or silicon nitride oxide on the fin surface, a polysilicon layer is deposited and patterned to form an insulated gate electrode. If the source / drain regions are formed by doping the fin regions on both sides of the gate electrode, a basic FET structure can be formed.

An example of the configuration of the Fin-FET is shown in FIG. In FIG. 3, the silicon layer of the SOI substrate is patterned to form the fins 51 and contact regions 52 and 53 whose widths are widened on both sides thereof. The cap layer 61 remains on the silicon layer. After the sacrificial oxide film is formed on the fin sidewall and removed, the gate insulating film 62 is formed by oxidation, nitridation, or the like. A polysilicon layer is deposited on the substrate and patterned to form the gate electrode 71. A contact region 72 having an increased width is formed at the end of the gate electrode 71. Impurities are added by ion implantation or the like to form the source / drain. After the transistor structure is embedded with an interlayer insulating film, a contact hole reaching the contact region is opened, and a conductive plug 80 such as a tungsten plug is embedded in the contact hole. The gate resistance can be reduced by stacking the polysilicon layer and the silicide layer as the gate electrode.
Fu-Liang Yang et al .; 2002 Symposium onVLSI Technology Digest of Technical Papers, p.104, 2002 Bin Yu et al .; IEDM Tech, Dig. P.251, 2002 The channel of the Fin-FET is formed on the side surface facing the gate electrode through the gate insulating film. The channel length is determined by the width of the gate electrode (polysilicon layer). The channel width is determined by the height of the fin. Although the length of the fin is determined by the process accuracy or the like, the narrow source / drain lead portion increases the resistance of the source / drain. There is also a proposal for forming a Schottky contact by cutting the fin and embedding a metal layer without expanding the end of the fin.

JP 2002-298771 A

An object of the present invention is to provide a semiconductor device including a high-performance field effect transistor having a fin-type structure and a method for manufacturing the same.
Another object of the present invention is to provide a semiconductor device including a field effect transistor having a fin-type structure with a low source / drain contact resistance and a method for manufacturing the same.

According to one aspect of the present invention,
A support substrate having an insulating surface;
A fin-type semiconductor region having a first conductivity type, which is formed on the support substrate, has a pair of side surfaces having a first height and is substantially perpendicular to the support substrate surface, and an upper surface connecting the both side surfaces. When,
A gate insulating film and a conductive gate electrode formed thereon are formed across the intermediate portion of the fin-type semiconductor region, and the gate electrode has a second height higher than the first height. An insulated gate electrode structure having a lateral surface;
A source / drain region having a second conductivity type formed in the fin-type semiconductor region on both sides of the gate electrode structure;
The side surface of the gate electrode does not exist on the upper surface and the side surface of the fin type semiconductor region, and surrounds the upper surface and both side surfaces of the fin type semiconductor region on the gate electrode side surface in the vicinity of the fin type semiconductor region. A sidewall insulating film formed on the lower portion;
A silicide layer formed from the upper end to the lower end on at least both side surfaces of the fin-type semiconductor region outside the sidewall insulating film;
Source / drain electrodes in contact with silicide layers on both side surfaces of the fin-type semiconductor region;
A semiconductor device is provided.

According to another aspect of the invention,
(A) The semiconductor layer of the SOI substrate is patterned, and on the support substrate having an insulating surface, a pair of side surfaces having a first height that are substantially perpendicular to the support substrate surface and upper surfaces connecting the both side surfaces are provided. Forming a fin-type semiconductor region;
(B) a side surface having a second height that crosses an intermediate portion of the fin-type semiconductor region, includes a gate insulating film and a conductive gate electrode thereon, and the gate electrode is higher than the first height. Forming an insulated gate electrode structure having:
(C) forming a sidewall insulating film covering the fin-type semiconductor region and the insulated gate electrode structure;
(D) forming source / drain regions in the fin-type semiconductor regions on both sides of the insulated gate electrode structure;
(E) The sidewall insulating film is anisotropically etched to be completely removed from the upper surface and side surfaces of the fin-type semiconductor region, and is removed from the upper surface of the gate electrode and upper portions of both side surfaces. Leaving the lower side of both sides of the gate electrode so as to surround the upper and side surfaces of the fin-type semiconductor region on both sides of the gate electrode in the vicinity of the region;
(F) forming a silicide layer from the upper end to the lower end on at least both exposed side surfaces of the fin-type semiconductor region;
(G) depositing an interlayer insulating film covering the fin-type semiconductor region and the gate electrode;
(H) forming a contact hole penetrating the interlayer insulating film and exposing a silicide layer on both side surfaces of the fin-type semiconductor region;
(I) burying a conductive plug in the contact hole;
A method for manufacturing a semiconductor device is provided.

  On both side surfaces of the gate electrode, a sidewall insulating film is formed below the both side surfaces so as to surround the fin type semiconductor region, and in the fin type semiconductor region, the sidewall insulating film is completely removed, and at least silicide is formed on both side surfaces thereof. Since the layer is formed, the source / drain contact resistance can be reduced.

Embodiments of the present invention will be described below with reference to the drawings.
1A to 1T are a cross-sectional view, a plan view, and a perspective view for explaining a method of manufacturing a semiconductor device including a field effect transistor having a fin-type structure according to an embodiment of the present invention.

  As shown in FIG. 1A, an SOI substrate provided with a buried silicon oxide layer 12 on a silicon support substrate 11 and a thin silicon layer 13 thereon is prepared. The silicon layer 13 forming the semiconductor element is adjusted to a thickness of 100 nm, for example. The thickness of this silicon layer is the height of a fin type region to be formed later, and determines the channel width of the fin type field effect transistor.

As shown in FIG. 1B, the SOI substrate is 800 ° C. to 1000 ° C. in a nitriding atmosphere such as N ₂ , NO, NH ₃ , NF ₃ , N ₂ O, a nitrogen atmosphere activated by electron cyclotron resonance (ECR) plasma. And anneal for 5 to 60 minutes. A silicon nitride film 14 x is formed at the interface between the silicon layer 13 and the buried oxide film 12, and a silicon nitride layer 14 y is also formed on the surface of the silicon layer 13. The silicon nitride layer has a function as an etch stopper. Regarding heat treatment in a nitriding atmosphere, JP-A-2002-26299, paragraphs 0016 to 0026 can be referred to.

As shown in FIG. 1C1, the silicon nitride layer 14y on the surface is removed with hot phosphoric acid or the like.
As shown in FIG. 1C2, a cap layer CL such as a stacked layer of a silicon oxide layer and a silicon nitride layer can be formed on the silicon layer 13. Note that the silicon nitride layer 14y shown in FIG. 1B may be used as it is as a cap layer. Hereinafter, a description will be given mainly of a structure without the cap layer CL as an example, but the case where the cap layer CL is provided will also be described as appropriate.

  As shown in FIG. 1D, a silicon oxide layer 15 is deposited on the silicon layer 13 by CVD, for example, with a thickness of 10 nm to 20 nm to form a hard mask layer. A resist mask RM1 is formed on the silicon oxide layer 15. The resist mask RM1 is a mask for etching the silicon layer 13 to form fins. The width of the fin is, for example, about 20 nm. The hard mask layer 15 is etched using the resist mask RM1 as an etching mask. Subsequently, the silicon layer 13 is etched using the resist mask RM1 and the hard mask layer 15 as a mask.

  As shown in FIG. 1E, the silicon layer 13 is etched following the initial shape of the resist mask RM1. The silicon nitride layer 14 below the silicon layer 13 functions as an etch stopper.

As shown in FIG. 1F, using an acid-based solution, the resist mask RM1 and the hard mask layer 15 are removed by solution cleaning.
As shown in FIG. 1G1, by performing oxidation treatment in a gas containing oxygen at a temperature of 800 ° C. to 1200 ° C., a gate insulating film having a thickness of 0.6 nm to 2 nm is formed on the surface of the silicon layer 13. Thereafter, nitriding is performed in a gas containing nitrogen at a temperature of 800 ° C. to 1200 ° C., so that the gate insulating film becomes an oxynitride film. As the gas containing nitrogen, a nitriding atmosphere such as N ₂ , NO, NH ₃ , NF ₃ , or N ₂ O may be used.
In this manner, an oxynitride gate insulating film 15 is formed on the upper surface and side surfaces of the silicon layer 13.

As shown in FIG. 1G2, when the cap layer CL is present, the gate insulating film 15 is formed only on both side surfaces of the silicon layer 13.
As shown in FIG. 1H, a polysilicon layer 16 covering the fin-type structure and having a height higher than the height of the fin is deposited by CVD, for example, with a thickness of about 120 nm to 200 nm. On the fin-type semiconductor region and in the vicinity thereof, the height of the polysilicon layer 16 is about 220 nm to 300 nm.

  As shown in FIG. 1I, a silicon oxide layer 17 having a thickness of 10 nm to 20 nm is formed on the polysilicon 16 by CVD to form a hard mask layer. A resist mask RM2 for etching the polysilicon layer 16 is formed on the silicon oxide layer 17. The resist mask RM2 is a mask for etching the gate electrode, and the width for determining the gate length is 100 nm or less, for example, 50 nm. The hard mask layer 17 is etched using the resist mask RM2 as a mask, and the polysilicon layer 16 is etched using the resist mask RM2 and the hard mask layer 17 as a mask. Thereafter, the resist mask RM2 and the hard mask layer 17 are removed by acid-based solution cleaning.

  As shown in FIGS. 1J and 1K, a polysilicon gate electrode 16 traversing the intermediate portion of the fin-type semiconductor region 13 is formed. FIG. 1J is a cross-sectional view through the gate electrode, and FIG. 1K is a plan view of the state in which the gate electrode 16 is formed. A polysilicon gate electrode 16 having a width of about 50 nm is formed across the intermediate portion of the fin-type semiconductor region 13 having a width of about 20 nm.

Hereinafter, description will be made using the XX cross section and the YY cross section of FIG. 1K. The suffix X in the figure number indicates the XX section, and the suffix Y in the figure number indicates the YY section.
1LX and 1LY schematically show the states of FIGS. 1J and 1K again. A gate electrode 16 higher than the fin is formed across the intermediate portion of the fin-type semiconductor region 13.

As shown in FIGS. 1MX and 1MY, a silicon oxide layer 21p having a thickness of 10 nm to 20 nm is deposited on the entire surface of the substrate by CVD.
As shown in FIGS. 1NX and 1NY, reactive ion etching (RIE) is performed to anisotropically etch the silicon oxide layer 21p. As the etching conditions, for example, a reactive gas containing fluorine (CF ₄ , CHF ₃ , C ₂ F ₆ , C ₄ F _8, etc.) is used, and a pressure of 1 Pa to 100 Pa and an applied high frequency of 13.56 MHz are used. The figure shows a state in which the silicon oxide layer 21 on the flat portion is etched and the silicon oxide layer 21 remains only on the side surface substantially perpendicular to the substrate surface. A normal side wall spacer is in this state.
As shown in FIGS. 1OX and 1OY, anisotropic etching RIE is further continued. The upper portions of the gate electrode 16 and the fin-type semiconductor region 13 are exposed. The anisotropic etching RIE is continued until the side surface of the fin-type semiconductor region 13 is completely exposed.

  1PX and 1PY show a state in which the silicon oxide layer 21 is completely etched away on the side surface of the fin-type semiconductor region 13. This state is called overetching of 100% or more with respect to the fin-type semiconductor region. However, the silicon oxide film 21 remains on the side surface of the gate electrode 16, and the side surface of the gate electrode 16 is covered to a position higher than the fin type semiconductor region 13 around the fin type semiconductor region 13. In other words, a silicon oxide layer 21 having a constant width remains between the exposed fin-type semiconductor region 13 and the exposed upper side surface of the gate electrode 16 to electrically isolate the two.

  As shown in FIGS. 1QX and 1QY, ions are implanted into the fin-type silicon region 13 from an oblique direction to form source / drain region extensions and high-concentration regions 18. If necessary, reverse conductivity type pocket regions may be ion-implanted. In addition, what is necessary is just to perform these ion implantation by a well-known method. For example, extension and pocket ion implantation may be performed before the sidewall insulating film 21 is formed, and ion implantation in the high concentration region may be performed at the stage where the sidewall 21 is formed or the RIE is completed.

  In the case of an n-channel MOS transistor, n-type source / drain regions 18 are formed on the upper surface and both side surfaces of the p-type fin-type silicon region 13. After ion implantation, annealing is performed at a temperature of 800 ° C. to 1200 ° C. to activate the implanted impurities.

  Through the above steps, a polysilicon gate electrode 16 is formed across the fin-type silicon region 13, and source / drain regions are formed on both sides of the polysilicon gate electrode 16 to form a basic FET structure.

  As shown in FIGS. 1RX and 1RY, a metal layer capable of silicide reaction such as Co and Ni is deposited on the entire surface of the substrate by sputtering, for example, with a thickness of 2 nm to 30 nm, and a primary silicide reaction is caused by annealing at 200 ° C. to 600 ° C. . The metal layer deposited on the silicon layer undergoes a primary silicide reaction to form a silicide layer 24. The unreacted metal layer is removed by an acid solution treatment or the like, and a secondary silicide reaction is performed again by annealing at 300 ° C. to 900 ° C. to form a low resistance silicide layer 24.

  In the portion of the fin-type semiconductor region 13 that protrudes from the gate electrode 16, a silicide layer 24 is formed on all side surfaces and the upper surface. Although the fin-type semiconductor region has a small width but a high height, a silicide layer is formed from the upper end to the lower end on side surfaces that are much wider than the upper surface and on both side surfaces. A silicide layer 24 is formed on the upper surface and upper side surface of the gate electrode 16. The effective resistance of the source / drain region is reduced, and a low resistance contact with the source / drain region of the source / drain extraction electrode is possible. The resistance of the gate electrode and the contact resistance of the lead electrode are also reduced. The silicide layer on the gate electrode is electrically separated from the silicide layer on the fin-type semiconductor region by the remaining silicon oxide layer 21 which is a sidewall spacer.

As shown in FIGS. 1SX and 1SY, an interlayer insulating film 22 is deposited by a silicon oxide film, a PSG film, a BPSG film or the like so as to cover the fin-type FET structure. The interlayer insulating film 22 has a thickness of 400 nm to 1000 nm, for example. After deposition by CVD or sputtering, the surface is planarized by chemical mechanical polishing (CMP) or the like. Contact holes for the source / drain and gate are formed in the interlayer insulating film 22 by RIE. In the etching of the contact hole CH, a gas containing fluorine as a reactive gas, for example, CF ₄ , CHF ₃ , C ₂ F ₆ , C ₄ F _8, etc. is used, the pressure is set to 1 Pa to 100 Pa, and 13.56 MHz. It can be performed by RIE to which high frequency power is applied. Etching of silicon oxide is stopped at the silicon nitride layer 14.

  After a barrier layer such as Ti or TiN is formed by sputtering or CVD, a W layer is deposited by CVD, and unnecessary portions on the interlayer insulating film are removed by CMP. In this way, the W conductive plug 26 is embedded in the interlayer insulating film 22. The conductive plugs constitute source / drain and gate lead electrodes. On the source / drain region, a silicide layer is formed to the height close to the channel, particularly on a wide side, and the contact resistance of the extraction electrode to the channel region can be significantly reduced. Thereafter, a multilayer wiring is formed by a known method disclosed in US Pat. Nos. 6,707,156 and 6,693,046.

  FIG. 1T is a perspective view showing a fin-type FET structure. The width of the gate electrode is widened at the end, a contact hole is formed thereon, and the W plug 26 is embedded. The fin-type silicon region Fin extends in the horizontal direction in the figure, and the portion protruding from the gate electrode G is silicided from the upper end to the lower end of both side surfaces and the upper surface connecting both side surfaces. Contacts both sides and top. When the width of the fin-type region is narrower than the height, it is difficult to sufficiently reduce the resistance if contact is made only on the upper surface. According to this embodiment, the silicide layer is also formed on both side surfaces of the fin-type silicon region and on the upper surface when there is no cap layer. Since the source / drain electrodes are in contact with the silicide layers on the wide side surfaces, the source / drain contact resistance can be reduced, and the series resistance between the source / drain can be reduced.

  2A shows a form in which a cap layer CL of silicon nitride or silicon oxynitride is provided on the fin-type semiconductor region Fin and the gate electrode G. FIG. In the etching of the fin-type semiconductor region Fin and the gate electrode G, a cap layer may be used as a hard mask layer. The silicide process shown in FIGS. 1RX and 1RY is performed on the side surfaces of the fin-type semiconductor region Fin and the gate electrode G, and the upper surface covered with the cap layer is not silicided. In the contact hole etching, the cap layer CL is also etched. After removing the cap layer, a silicide process may be further performed.

  In the above embodiment, a nitriding process is performed through the silicon layer 13 to form a silicon nitride layer at the interface between the silicon layer and the buried oxide film. If an SOI substrate having a buried insulating layer of silicon nitride or silicon oxynitride is used, the nitriding step can be omitted.

  As shown in FIG. 2B, an SOI substrate in which the buried insulating layer is formed of a silicon nitride layer or a silicon oxynitride layer 12x instead of a silicon oxide layer is used. In this case, the buried insulating layer 12x itself functions as an etch stopper without forming a silicon nitride layer.

    Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by the Example of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by the Example of this invention. It is sectional drawing and a top view for demonstrating the manufacturing process of the semiconductor device by the Example of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device by the Example of this invention. It is sectional drawing and a perspective view for demonstrating the manufacturing process of the semiconductor device by the Example of this invention. It is a perspective view which shows the modification of an Example. It is a perspective view which shows the example of a prior art.

Explanation of symbols

11 (Si) support substrate 12 buried silicon oxide layer (BOX layer)
12x silicon nitride (silicon oxynitride) layer 13 silicon layer (fin type semiconductor region)
14 Silicon nitride layer 15, 17 CVD silicon oxide layer 16 Polysilicon layer 18 Source / drain region RM Resist mask CL Cap layer 21 Side wall oxide film (insulating layer)
22 Interlayer insulating layer 24 Silicide layer

Claims (10)

A support substrate having an insulating surface;
A fin-type semiconductor region having a first conductivity type, which is formed on the support substrate, has a pair of side surfaces having a first height and is substantially perpendicular to the support substrate surface, and an upper surface connecting the both side surfaces. When,
A gate insulating film and a conductive gate electrode formed thereon are formed across the intermediate portion of the fin-type semiconductor region, and the gate electrode has a second height higher than the first height. An insulated gate electrode structure having a lateral surface;
A source / drain region having a second conductivity type formed in the fin-type semiconductor region on both sides of the gate electrode structure;
The side surface of the gate electrode does not exist on the upper surface and the side surface of the fin type semiconductor region, and surrounds the upper surface and both side surfaces of the fin type semiconductor region on the gate electrode side surface in the vicinity of the fin type semiconductor region. A sidewall insulating film formed on the lower portion;
A silicide layer formed from the upper end to the lower end on at least both side surfaces of the fin-type semiconductor region outside the sidewall insulating film;
Source / drain electrodes in contact with silicide layers on both side surfaces of the fin-type semiconductor region;
A semiconductor device.   2. The semiconductor device according to claim 1, wherein the source / drain regions are formed on a side surface and an upper surface of the fin type semiconductor region, and the silicide layer is formed on a side surface and an upper surface of the fin type semiconductor region. And an insulating protective film formed on the upper surface of the fin-type semiconductor region,
2. The semiconductor device according to claim 1, wherein the gate insulating film is formed on both side surfaces of the fin type semiconductor region, and the silicide layer is formed on both side surfaces of the fin type semiconductor region. And further comprising an interlayer insulating film in which the fin type semiconductor region and the insulated gate electrode structure are embedded and contact holes are formed to expose silicide layers on both side surfaces of the fin type semiconductor region,
The semiconductor device according to claim 1, wherein the source / drain electrodes are in contact with silicide layers on both side surfaces of the fin-type semiconductor region in the contact hole.   The semiconductor device according to claim 1, wherein the buried insulating film of the SOI substrate has a surface of silicon nitride or silicon oxynitride. (A) The semiconductor layer of the SOI substrate is patterned, and on the support substrate having an insulating surface, a pair of side surfaces having a first height that are substantially perpendicular to the support substrate surface and upper surfaces connecting the both side surfaces are provided. Forming a fin-type semiconductor region;
(B) a side surface having a second height that crosses an intermediate portion of the fin-type semiconductor region, includes a gate insulating film and a conductive gate electrode thereon, and the gate electrode is higher than the first height. Forming an insulated gate electrode structure having:
(C) forming a sidewall insulating film covering the fin-type semiconductor region and the insulated gate electrode structure;
(D) forming source / drain regions in the fin-type semiconductor regions on both sides of the insulated gate electrode structure;
(E) The sidewall insulating film is anisotropically etched to be completely removed from the upper surface and side surfaces of the fin-type semiconductor region, and is removed from the upper surface of the gate electrode and upper portions of both side surfaces. Leaving the lower side of both sides of the gate electrode so as to surround the upper and side surfaces of the fin-type semiconductor region on both sides of the gate electrode in the vicinity of the region;
(F) forming a silicide layer from the upper end to the lower end on at least both exposed side surfaces of the fin-type semiconductor region;
(G) depositing an interlayer insulating film covering the fin-type semiconductor region and the gate electrode;
(H) forming a contact hole penetrating the interlayer insulating film and exposing a silicide layer on both side surfaces of the fin-type semiconductor region;
(I) burying a conductive plug in the contact hole;
A method of manufacturing a semiconductor device including:   The step (a) forms a fin-type semiconductor region having an exposed upper surface and side surfaces, and the step (f) forms the silicide layer on the upper surface and both side surfaces of the fin-type semiconductor region. 6. A method for manufacturing a semiconductor device according to 6.   The step (a) forms a fin-type structure having an insulating protective film on the fin-type semiconductor region, and the step (f) forms the silicide layer on both side surfaces of the fin-type semiconductor region. Item 7. A method for manufacturing a semiconductor device according to Item 6.   The method for manufacturing a semiconductor device according to claim 6, further comprising: (j) removing the insulating protective film exposed in the contact hole. 10. The method of manufacturing a semiconductor device according to claim 6, further comprising: (k) performing a nitriding process on the SOI substrate to form a nitride film at an interface between the semiconductor layer and the buried insulating film.

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