WO2010103714A1 - Semiconductor device and method for producing the same - Google Patents

Semiconductor device and method for producing the same Download PDF

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Publication number
WO2010103714A1
WO2010103714A1 PCT/JP2010/000395 JP2010000395W WO2010103714A1 WO 2010103714 A1 WO2010103714 A1 WO 2010103714A1 JP 2010000395 W JP2010000395 W JP 2010000395W WO 2010103714 A1 WO2010103714 A1 WO 2010103714A1
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Prior art keywords
semiconductor device
conductive members
fin
gate electrode
diffusion layer
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PCT/JP2010/000395
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French (fr)
Japanese (ja)
Inventor
中林隆
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a Fin-type transistor having a Fin-like active region and a manufacturing method thereof.
  • the Fin-type transistor uses the upper surface and side surface in the Fin-like active region as the channel of the MOS transistor, and therefore, a large drive current can be obtained.
  • gate control is improved because the gate voltage is applied from three directions of both side surfaces and the upper surface. As a result, the short channel effect, which is the biggest problem in miniaturization of devices, can be suppressed, so that it is expected as a next-generation device.
  • the driving capability of the Fin-type transistor greatly depends on the height of the Fin, and increases as the Fin height increases.
  • the Fin width is usually as small as about 20 nm, it is difficult to increase the Fin height in processing. For this reason, the driving capability per one Fin type transistor is determined by this processing limit.
  • a height of about 50 nm is used.
  • Many circuits having high load parasitic resistance and parasitic capacitance exist in semiconductor integrated circuits (LSIs). In order to drive these high load circuits, the gate width is as high as several ⁇ m to several tens ⁇ m. Driving ability is required.
  • a Fin portion of a Fin-type transistor is formed on an SOI substrate made of a substrate 200 made of silicon, a buried oxide film 201, and a silicon layer 202.
  • the first resist pattern 230 is formed.
  • the silicon layer 202 is etched using the resist patterns 230, 231 and 232 as masks, so that the Fin portion 233 in the Fin-type transistor and its A common source pad 234 and a common drain pad 235 connected to both ends are formed.
  • the gate insulating film 205 and polycrystalline silicon are formed on the buried oxide film 201 and the Fin portion 233 so as to intersect the Fin portion 233.
  • a gate electrode 206 is sequentially formed.
  • arsenic (As) ions are implanted four times in total, once each from four directions perpendicular to the normal of the SOI substrate and at a 45 ° angle to the gate electrode 206 and the Fin portion 233. Do.
  • a source side LDD diffusion layer 236, a source common pad portion 237, a drain side LDD diffusion layer 238 and a drain common pad portion 239 are formed in the Fin portion 233.
  • the gate electrode 206, the source side LDD diffusion layer 236, the source common pad portion 237, the drain side LDD diffusion layer 238, and the drain common pad portion 239 are included.
  • a silicon nitride film is deposited over the entire surface of the buried oxide film 201.
  • the silicon nitride film is etched back to form a sidewall 209 made of silicon nitride and covering at least the source-side LDD diffusion layer 236 and the drain-side LDD diffusion layer 238.
  • the source diffusion layer 240, the source common pad portion 241, the drain diffusion layer 242, and the drain common pad portion 243 are formed in the Fin portion 233.
  • a nickel silicide film 244 on the gate electrode is formed on the surface of the gate electrode 206 by a known salicide technique.
  • a nickel silicide film 245 on the source diffusion layer and a nickel silicide film 246 on the source common pad are formed on the surfaces of the source diffusion layer 240 and the source common pad portion 241.
  • a nickel silicide film 247 on the drain diffusion layer and a nickel silicide film 248 on the drain common pad are formed on the surfaces of the drain diffusion layer 242 and the drain common pad portion 243.
  • an interlayer insulating film 249 is formed on the buried oxide film 201 so as to cover the nickel silicide films 244 to 248. Thereafter, openings 250, 251 and 252 exposing the nickel silicide film 244 on the gate electrode, the nickel silicide film 246 on the source common pad, and the nickel silicide film 248 on the common drain pad are respectively formed in the formed interlayer insulating film 249. Form.
  • the openings 250, 251 and 252 are filled with a tungsten film, and contact plugs 253, 254 and 255 are formed.
  • metal wirings 256 connected to the respective contact plugs 253, 254 and 255 are formed on the interlayer insulating film 249, respectively. Form.
  • the semiconductor device using the conventional manufacturing method has the following problems. That is, by the double patterning composed of the steps of FIGS. 16 and 17, the resist patterns 230 to 232 are formed with substantially planar openings.
  • the silicon layer 202 shown in FIG. 18 is etched, the end of the opening is rounded due to the etching characteristics, and the planar shape thereof is almost elliptical.
  • the retraction amount of the opening due to the rounding is about 50 nm in the case of Multi-Fin in the 80 nm space. This amount of receding increases as miniaturization progresses and the space becomes narrower. Since this rounding substantially widens the Fin width, it cannot be used for the channel portion of the Fin-type transistor.
  • An object of the present invention is to solve the above-mentioned problems and to realize a multi-fin transistor having a small layout area and a high driving capability without increasing the number of process steps.
  • the semiconductor device has a configuration in which the end portions of each Fin portion are connected to each other by one contact instead of the configuration in which the source / drain common pad region is formed in the Fin portion.
  • a semiconductor device includes a plurality of rectangular parallelepiped conductive members (Fin) formed on a substrate and spaced apart from each other in parallel, and a plurality of conductive members.
  • a gate electrode formed so as to intersect with each conductive member, and a contact electrically connected to at least two conductive members in the vicinity of at least one end of the plurality of conductive members. I have.
  • the contact is provided in the vicinity of at least one end of the plurality of conductive members and electrically connected to at least two conductive members. For this reason, since the plurality of conductive members (Fin) do not need to be provided with a common pad portion for the source or drain, the length of the Fin portion can be shortened. As a result, the layout area of the Multi-Fin transistor can be reduced, the parasitic resistance can be kept low, and the driving capability can be improved.
  • the substrate and the plurality of conductive members may be insulated by an insulating film, and the contact may reach the insulating film.
  • the contact may be formed at a position closer to the gate electrode side than the ends of the plurality of conductive members.
  • the semiconductor device can be further miniaturized.
  • the contacts may be formed inside the conductive members located at both ends of the plurality of conductive members.
  • the semiconductor device can be further miniaturized.
  • the method of manufacturing a semiconductor device includes a step of arranging a plurality of rectangular parallelepiped conductive members on a substrate in parallel with a space between each other, and intersecting each conductive member on the plurality of conductive members. And forming a gate electrode through an insulating film, and forming a source / drain diffusion layer from each conductive member by implanting impurities into each conductive member using the gate electrode as a mask, After forming the source / drain diffusion layer, forming an interlayer insulating film on the substrate so as to cover the gate electrode and each conductive member, and at least one end of the plurality of conductive members with respect to the interlayer insulating film A step of forming an opening in the vicinity of the portion and exposing at least two conductive members, and a step of forming a contact electrically connected to the exposed conductive member in the opening. To have.
  • an opening is formed in the interlayer insulating film in the vicinity of at least one end of the plurality of conductive members and exposing at least two conductive members.
  • a contact that is electrically connected to the exposed conductive member is formed on the portion.
  • the opening may be formed so as to reach the insulating film in the step of forming the opening.
  • the opening in the step of forming the opening, may be formed at a position closer to the gate electrode side than the ends of the plurality of conductive members.
  • the opening in the step of forming the opening, may be formed inside the conductive members positioned at both ends of the plurality of conductive members.
  • FIG. 1A and 1B show a semiconductor device according to an embodiment of the present invention
  • FIG. 1A is a perspective view
  • FIG. 1B is a plan view
  • 2A and 2B show a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 2A is a perspective view
  • FIG. 2B is a plan view
  • It is. 3A and 3B show a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 3A is a perspective view
  • FIG. 3B is a plan view.
  • FIG. 4 (a) and 4 (b) show one step of the method of manufacturing a semiconductor device according to one embodiment of the present invention
  • FIG. 4 (a) is a perspective view
  • FIG. 4 (b) is a plan view.
  • FIG. 5A and 5B show a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 5A is a perspective view
  • FIG. 5B is a plan view.
  • FIG. 6 (a) and 6 (b) show a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention
  • FIG. 6 (a) is a perspective view
  • FIG. 6 (b) is a plan view.
  • FIG. 7A to FIG. 7C show one step of the method of manufacturing the semiconductor device according to one embodiment of the present invention
  • FIG. 7A is a perspective view
  • FIG. 7B is a plan view.
  • FIG. 7C is a cross-sectional view taken along the line VIIc-VIIc in FIG.
  • FIG. 8A and FIG. 8B show one step of the method of manufacturing a semiconductor device according to one embodiment of the present invention
  • FIG. 8A is a perspective view
  • FIG. 8B is a plan view.
  • FIG. 9A to FIG. 9C show one step of the method of manufacturing the semiconductor device according to one embodiment of the present invention
  • FIG. 9A is a perspective view
  • FIG. 9B is a plan view
  • FIG. 9C is a cross-sectional view taken along the line IXc-IXc in FIG.
  • FIG. 10A is a plan view showing the layout of the patterning mask for the silicon layer of the semiconductor device according to one embodiment of the present invention
  • FIG. 10B is the silicon pattern after etching, the gate electrode, and the contact plug. It is a top view which shows a layout.
  • FIG. 11A is a plan view showing a layout of a patterning mask for a silicon layer of a semiconductor device according to a conventional example
  • FIG. 11B is a plan view showing a layout of a silicon pattern, a gate electrode and a contact plug after etching.
  • FIG. FIG. 12 is a graph showing a simulation result of Id-Vd characteristics in the semiconductor device according to one embodiment of the present invention together with a conventional example.
  • FIG. 13A and FIG. 13B show a semiconductor device according to a first modification of one embodiment of the present invention
  • FIG. 13A is a plan view of the main part
  • FIG. 13A is a plan view of the main part
  • FIG. 14A and 14B show a semiconductor device according to a second modification of the embodiment of the present invention.
  • FIG. 14A is a plan view of the main part, and FIG. It is sectional drawing in the XIVb-XIVb line
  • FIG. 15A and FIG. 15B show a semiconductor device according to a third modification of one embodiment of the present invention,
  • FIG. 15A is a plan view of the main part, and FIG. FIG. 16 is a cross-sectional view taken along line XVb-XVb in FIG. 16 (a) and 16 (b) show one step in the method of manufacturing a semiconductor device according to the conventional example, FIG.
  • FIG. 16 (a) is a perspective view
  • FIG. 16 (b) is a plan view
  • 17 (a) and 17 (b) show one step of the manufacturing method of the semiconductor device according to the conventional example
  • FIG. 17 (a) is a perspective view
  • FIG. 17 (b) is a plan view
  • 18 (a) and 18 (b) show one step of the manufacturing method of the semiconductor device according to the conventional example
  • FIG. 18 (a) is a perspective view
  • FIG. 18 (b) is a plan view
  • FIG. 19A and FIG. 19B show one step of a method of manufacturing a semiconductor device according to a conventional example
  • FIG. 19A is a perspective view
  • FIG. 19B is a plan view.
  • FIG. 20 (a) and 20 (b) show a step of the manufacturing method of the semiconductor device according to the conventional example
  • FIG. 20 (a) is a perspective view
  • FIG. 20 (b) is a plan view
  • FIG. 21A and FIG. 21B show one process of the manufacturing method of the semiconductor device according to the conventional example
  • FIG. 21A is a perspective view
  • FIG. 21B is a plan view
  • 22 (a) and 22 (b) show one step in the method of manufacturing a semiconductor device according to the conventional example
  • FIG. 22 (a) is a perspective view
  • FIG. 22 (b) is a plan view
  • FIG. 23A and FIG. 23B show one process of the manufacturing method of the semiconductor device according to the conventional example
  • FIG. 23A is a perspective view
  • FIG. 23A is a perspective view
  • FIG. 23A is a perspective view
  • FIG. 23A is a perspective view
  • FIG. 23A is a perspective view
  • FIG. 23A is a perspective view
  • FIG. 23B is a plan view.
  • 24 (a) to 24 (c) show one step in the method of manufacturing a semiconductor device according to the conventional example, FIG. 24 (a) is a perspective view, and FIG. 24 (b) is a plan view.
  • 24 (c) is a cross-sectional view taken along the line XXIVc-XXIVc in FIG. 24 (a).
  • FIG. 1A and 1B are semiconductor devices according to the present invention, showing an N-channel Multi-Fin type transistor, FIG. 1A being a perspective view, and FIG. 1B being a plan view.
  • FIG. 1A being a perspective view
  • FIG. 1B being a plan view.
  • an embedded oxide film 101 made of silicon oxide having a thickness of 80 nm is formed on the main surface of a substrate 100 made of silicon.
  • a plurality of rectangular parallelepiped source diffusion layers 110 and drain diffusion layers 111 made of silicon each having a height of 50 nm are spaced apart from each other. They are arranged in parallel.
  • a gate electrode 106 is formed which intersects with each Fin portion and is formed with a gate insulating film (not shown) interposed therebetween.
  • nitriding is performed at the lower portion of each side surface of the gate electrode 106, the source diffusion layer 110, and the drain diffusion layer 111, and at the intersection of the side surfaces of the gate electrode 106, the source diffusion layer 110, and the gate electrode 106, the drain diffusion layer 111 A side wall 109 made of silicon is formed.
  • An interlayer insulating film 115 made of silicon oxide is formed on the buried oxide film 101 so as to cover the gate electrode 106, the source diffusion layer 110, and the drain diffusion layer 111.
  • a gate electrode portion contact plug 119 that is electrically connected to the gate electrode 106 is formed in the interlayer insulating film 115.
  • the nickel silicide films formed on the surfaces of the gate electrode 106, the source diffusion layer 110, and the drain diffusion layer 111 are omitted.
  • FIGS. 2 to 9 show a method for manufacturing an N-channel Multi-Fin transistor according to this embodiment.
  • (a) of each figure is a perspective view
  • (b) is a top view
  • (c) is sectional drawing.
  • an SOI substrate made of a buried oxide film 101 having a thickness of 80 nm and a silicon layer 102 having a thickness of 50 nm
  • a resist pattern 103 for forming the Fin portion of the Fin transistor is formed by lithography.
  • the silicon layer 102 is etched using the resist pattern 103 as a mask to form a plurality of Fin portions 104 from the silicon layer 102.
  • a mask formation film made of silicon nitride or the like is formed on the silicon layer 102, and then the mask formation film is patterned using the resist pattern 103 as a mask, and the silicon layer 102 is formed using the patterned mask formation film as a hard mask. May be processed.
  • the gate insulating film 105 and polycrystalline silicon are formed on the buried oxide film 101 and the Fin portion 104 so as to intersect the Fin portion 104.
  • a gate electrode 106 is sequentially formed.
  • a silicon oxide film or a silicon nitride film can be used for the gate insulating film 105.
  • a high dielectric constant film such as hafnia (hafnium oxide) or zirconium oxide (zirconia) may be used.
  • the gate electrode 106 may be a stacked film of a conductive film containing metal such as titanium nitride and silicon, or a metal film such as tungsten, instead of polycrystalline silicon.
  • arsenic (As) ions are implanted at an acceleration energy of 2 keV, a dose of 2 ⁇ 10 14 cm ⁇ 2 , and at an angle of 45 ° with respect to the normal of the SOI substrate.
  • a total of four times of ion implantation are performed once from four directions perpendicular to the Fin portion 104.
  • the source side LDD diffusion layer 107 and the drain side LDD diffusion layer 108 are formed in each Fin portion 104.
  • the thickness of the entire surface of the buried oxide film 101 including the gate electrode 106, the source side LDD diffusion layer 107 and the drain side LDD diffusion layer 108 is increased.
  • a silicon nitride film having a thickness of 30 nm is deposited. Thereafter, the deposited silicon nitride film is etched back to form a sidewall 109 made of silicon nitride and covering at least the source-side LDD diffusion layer 107 and the drain-side LDD diffusion layer 108.
  • a nickel film is deposited over the entire surface of the buried oxide film 101 including the gate electrode 106, the source diffusion layer 110, and the drain diffusion layer 111. . Thereafter, a predetermined heat treatment is performed, and a nickel silicide film 112 on the gate electrode, a nickel silicide film 113 on the source diffusion layer, and a nickel silicide film 114 on the drain diffusion layer are formed by a salicide technique for removing an unnecessary nickel film, respectively.
  • the nickel silicide films 112 to 114 are covered on the buried oxide film 101 by, for example, chemical vapor deposition (CVD).
  • An interlayer insulating film 115 made of silicon oxide is formed.
  • a first contact opening 116 that exposes the nickel silicide film 112 on the gate electrode, the nickel silicide film 113 on the source diffusion layer, and the nickel silicide film 114 on the drain diffusion layer to the formed interlayer insulating film 115,
  • a second contact opening 117 and a third contact opening 118 are formed.
  • the second contact opening 117 is formed across the plurality of source diffusion layers 110 composed of a plurality of Fin portions, and the bottom thereof is each source diffusion layer. It is formed deeper than the upper surface of 110. The same applies to the third contact opening 118 that exposes the nickel silicide films 114 on the plurality of drain diffusion layers.
  • each contact opening 116, 117, and 118 is filled with a tungsten film, so that the gate electrode contact plug 119 and the source diffusion layer contact plug 120 are filled.
  • the drain diffusion layer portion contact plug 121 is formed.
  • the gate electrode contact plug 119 On the interlayer insulating film 115, the gate electrode contact plug 119, the source diffusion layer contact plug 120, and the drain diffusion are formed. A plurality of metal wirings 122 connected to the layer contact plug 121 are formed.
  • each source diffusion layer 110 is in contact with one source diffusion layer portion contact plug 120 on the upper surface and side surfaces thereof, so that the contact resistance can be reduced.
  • FIG. 10A shows the layout of the patterning mask for the silicon layer according to this embodiment
  • FIG. 10B shows the layout of the etched silicon pattern, gate electrode, and contact plug.
  • 11A and 11B are for comparison
  • FIG. 11A shows a layout of a patterning mask for a silicon layer according to a conventional example
  • FIG. 11B shows a silicon pattern after etching
  • 2 shows a layout of gate electrodes and contact plugs. 10
  • the same reference numerals as those in FIGS. 2, 3, 4, and 8 are given.
  • FIG. 11 the same reference numerals as those in FIGS. 16, 18, 19, and 23 are given. is doing.
  • the length of the opening (gap) of the etched silicon layer is retreated (a part in the figure), and the rounded part (FIG. Middle part b) occurs. Since the width of the Fin portion 233 is increased by the a portion and the b portion, it cannot be used as a transistor channel.
  • the length of the Fin portion 104 is shortened after etching the silicon layer (e in the figure).
  • OPC optical proximity correction
  • the length of the Fin portion 104 is determined by the respective overlapping margins (f in the figure) of the source diffusion layer portion contact plug 120, the drain diffusion layer portion contact plug 121, and the gate electrode 106.
  • FIG. 12 shows the simulation result of the current-voltage (Id-Vd) characteristics of the N-channel Multi-Fin transistor according to this embodiment together with the conventional example.
  • the length of the fin portion 104 having a narrow high resistance width can be reduced from 60 nm of the conventional example to 20 nm.
  • the parasitic resistance can be reduced.
  • the driving power of the transistor can be improved by about 15%.
  • the source diffusion layer portion contact plug 120 and the drain diffusion layer portion contact plug 121 are formed so as to reach the buried oxide film 101. ing. In this way, the contact area of each contact plug 120, 121 can be increased, and the contact resistance can be reduced.
  • the source diffusion layer portion contact plug 120 and the drain diffusion layer portion contact plug 121 are provided from the end portions of the plurality of Fin portions 104. Is also formed at a position close to the gate electrode 106 side. In this case, since the occupied area per transistor is reduced, the transistor can be further miniaturized and highly integrated.
  • the source diffusion layer portion contact plug 120 and the drain diffusion layer portion contact plug 121 are provided at both ends of the plurality of Fin portions 104. It is formed inside the Fin portion 104. In this case, since the occupied area per transistor is reduced, the transistor can be further miniaturized and highly integrated.
  • the semiconductor device and the manufacturing method thereof according to the present invention can reduce the length of Fin, and as a result, a Multi-Fin type transistor having a small layout area and a high driving capability without increasing the number of process steps. It can be realized and is useful for a Fin-type transistor and a manufacturing method thereof.
  • Substrate 101 Embedded oxide film 103 Resist pattern 104 Fin portion 105 Gate insulating film 106 Gate electrode 107 Source side LDD diffusion layer 108 Drain side LDD diffusion layer 109 Side wall 110 Source diffusion layer 111 Drain diffusion layer 112 Nickel silicide film 113 on gate electrode Nickel silicide film on diffusion layer 114 Nickel silicide film on drain diffusion layer 115 Interlayer insulating film 116 First contact opening 117 Second contact opening 118 Third contact opening 119 Gate electrode contact plug 120 Source diffusion layer Contact plug 121 Drain diffusion layer contact plug 122 Metal wiring

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Abstract

Disclosed is a semiconductor device comprised of fin portions composed of a plurality of source diffusion layers (110) and a plurality of drain diffusion layers (111); and a gate electrode (106) is formed on the fin portions via a gate insulation layer (105) so as to intersect with the fin portions. The source diffusion layers (110) and the drain diffusion layers (111) are formed in the form of a rectangular parallelepiped, on a substrate (100) composed of silicone, and are arranged in parallel and spaced at a distance. A contact plug (120) for the source diffusion layers, which is electrically connected to at least two of the fin portions, is formed in at least one end portion of the fin portions.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置及びその製造方法に関し、特に、Ｆｉｎ（フィン）状の活性領域を有するＦｉｎ型トランジスタ及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a Fin-type transistor having a Fin-like active region and a manufacturing method thereof.
　Ｆｉｎ型トランジスタは、Ｆｉｎ状の活性領域における上面及び側面をＭＯＳトランジスタのチャネルとして用いており、このため、大きな駆動電流を得ることができる。その上、両側面と上面との三方向からゲート電圧が印加されるため、ゲート制御性が向上する。その結果、デバイスの微細化において最大の課題である短チャネル効果を抑制できるため、次世代のデバイスとして期待されている。 The Fin-type transistor uses the upper surface and side surface in the Fin-like active region as the channel of the MOS transistor, and therefore, a large drive current can be obtained. In addition, gate control is improved because the gate voltage is applied from three directions of both side surfaces and the upper surface. As a result, the short channel effect, which is the biggest problem in miniaturization of devices, can be suppressed, so that it is expected as a next-generation device.
　Ｆｉｎ型トランジスタの駆動能力は、Ｆｉｎの高さに大きく依存し、Ｆｉｎの高さが高くなるにつれて増大する。しかしながら、Ｆｉｎの幅は通常２０ｎｍ程度と極めて小さいため、Ｆｉｎの高さを高くすることは加工の上で困難である。このため、１つのＦｉｎ型トランジスタ当たりの駆動能力は、この加工限界により決定される。通常５０ｎｍ程度の高さが用いられており、この場合、実効的なゲート幅は、Ｆｉｎの高さ（５０ｎｍ）×２＋Ｆｉｎの幅（２０ｎｍ）＝１２０ｎｍとなる。半導体集積回路（ＬＳＩ）には、高負荷の寄生抵抗及び寄生容量を有する回路が多く存在しており、これらの高負荷回路を駆動するには、ゲート幅で数μｍ～数十μｍ相当の高駆動能力が必要とされる。ところが、単位ゲート幅当たりの駆動能力が、プレーナ型トランジスタと比べてＦｉｎ型トランジスタの方が大きいからといって、それに対応することは極めて困難である。このため、Ｆｉｎ型トランジスタにおいては、複数のＦｉｎ型トランジスタを並列に接続する（Ｍｕｌｔｉ－Ｆｉｎ）ことによって、高駆動能力を実現する構成が提案されている。 The driving capability of the Fin-type transistor greatly depends on the height of the Fin, and increases as the Fin height increases. However, since the Fin width is usually as small as about 20 nm, it is difficult to increase the Fin height in processing. For this reason, the driving capability per one Fin type transistor is determined by this processing limit. Usually, a height of about 50 nm is used. In this case, the effective gate width is Fin height (50 nm) × 2 + Fin width (20 nm) = 120 nm. Many circuits having high load parasitic resistance and parasitic capacitance exist in semiconductor integrated circuits (LSIs). In order to drive these high load circuits, the gate width is as high as several μm to several tens μm. Driving ability is required. However, it is extremely difficult to cope with the Fin type transistor because the driving capability per unit gate width is larger in the Fin type transistor than in the planar type transistor. For this reason, in the Fin-type transistor, a configuration has been proposed in which a plurality of Fin-type transistors are connected in parallel (Multi-Fin) to realize high driving capability.
　以下、図１６～図２４を参照しながら、下記の特許文献１に示されている、ＮチャネルＭｕｌｔｉ－Ｆｉｎ型トランジスタの製造方法について説明する。なお、各図の（ａ）は斜視図であり、（ｂ）は平面図であり、（ｃ）は断面図である。 Hereinafter, a method for manufacturing an N-channel Multi-Fin transistor disclosed in Patent Document 1 described below will be described with reference to FIGS. In addition, (a) of each figure is a perspective view, (b) is a top view, (c) is sectional drawing.
　まず、図１６（ａ）及び図１６（ｂ）に示すように、シリコンからなる基板２００、埋め込み酸化膜２０１及びシリコン層２０２からなるＳＯＩ基板の上に、Ｆｉｎ型トランジスタのＦｉｎ部を構成するための第１のレジストパターン２３０を形成する。 First, as shown in FIGS. 16A and 16B, a Fin portion of a Fin-type transistor is formed on an SOI substrate made of a substrate 200 made of silicon, a buried oxide film 201, and a silicon layer 202. The first resist pattern 230 is formed.
　次に、図１７（ａ）及び図１７（ｂ）に示すように、第１のレジストパターン２３０の両端部と接続するように、ソース共通パッド部を構成するための第２のレジストパターン２３１及びドレイン共通パッド部を構成するための第３のレジストパターン２３２をそれぞれ形成する。 Next, as shown in FIGS. 17A and 17B, a second resist pattern 231 for configuring a source common pad portion so as to be connected to both ends of the first resist pattern 230, and A third resist pattern 232 for forming the drain common pad portion is formed.
　次に、図１８（ａ）及び図１８（ｂ）に示すように、各レジストパターン２３０、２３１及び２３２をマスクとして、シリコン層２０２をエッチングすることにより、Ｆｉｎ型トランジスタにおけるＦｉｎ部２３３、並びにその両端部と接続されるソース共通パッド部２３４及びドレイン共通パッド部２３５を形成する。 Next, as shown in FIGS. 18A and 18B, the silicon layer 202 is etched using the resist patterns 230, 231 and 232 as masks, so that the Fin portion 233 in the Fin-type transistor and its A common source pad 234 and a common drain pad 235 connected to both ends are formed.
　次に、図１９（ａ）及び図１９（ｂ）に示すように、埋め込み酸化膜２０１及びＦｉｎ部２３３の上に該Ｆｉｎ部２３３と交差するように、ゲート絶縁膜２０５と多結晶シリコンからなるゲート電極２０６とを順次形成する。続いて、ヒ素（Ａｓ）イオンを、ＳＯＩ基板の法線に対して４５°の角度で且つゲート電極２０６及びＦｉｎ部２３３に対して垂直な四方向から１回ずつ、計４回のイオン注入を行う。これにより、Ｆｉｎ部２３３には、ソース側ＬＤＤ拡散層２３６、ソース共通パッド部２３７、ドレイン側ＬＤＤ拡散層２３８及びドレイン共通パッド部２３９が形成される。 Next, as shown in FIGS. 19A and 19B, the gate insulating film 205 and polycrystalline silicon are formed on the buried oxide film 201 and the Fin portion 233 so as to intersect the Fin portion 233. A gate electrode 206 is sequentially formed. Subsequently, arsenic (As) ions are implanted four times in total, once each from four directions perpendicular to the normal of the SOI substrate and at a 45 ° angle to the gate electrode 206 and the Fin portion 233. Do. As a result, a source side LDD diffusion layer 236, a source common pad portion 237, a drain side LDD diffusion layer 238 and a drain common pad portion 239 are formed in the Fin portion 233.
　次に、図２０（ａ）及び図２０（ｂ）に示すように、ゲート電極２０６、ソース側ＬＤＤ拡散層２３６、ソース共通パッド部２３７、ドレイン側ＬＤＤ拡散層２３８及びドレイン共通パッド部２３９を含め、埋め込み酸化膜２０１の上の全面にわたって、シリコン窒化膜を堆積する。その後、シリコン窒化膜に対してエッチバックを行って、窒化シリコンからなり、少なくともソース側ＬＤＤ拡散層２３６及びドレイン側ＬＤＤ拡散層２３８を覆う側壁２０９を形成する。続いて、Ａｓイオンを、ＳＯＩ基板の法線に対して４５°の角度で且つゲート電極２０６及びＦｉｎ部２３３に対して垂直な四方向から１回ずつ、計４回のイオン注入を行う。これにより、Ｆｉｎ部２３３には、ソース拡散層２４０、ソース共通パッド部２４１、ドレイン拡散層２４２及びドレイン共通パッド部２４３が形成される。 Next, as shown in FIGS. 20A and 20B, the gate electrode 206, the source side LDD diffusion layer 236, the source common pad portion 237, the drain side LDD diffusion layer 238, and the drain common pad portion 239 are included. Then, a silicon nitride film is deposited over the entire surface of the buried oxide film 201. Thereafter, the silicon nitride film is etched back to form a sidewall 209 made of silicon nitride and covering at least the source-side LDD diffusion layer 236 and the drain-side LDD diffusion layer 238. Subsequently, As ions are implanted four times in total from the four directions perpendicular to the gate electrode 206 and the Fin portion 233 at an angle of 45 ° with respect to the normal line of the SOI substrate. Accordingly, the source diffusion layer 240, the source common pad portion 241, the drain diffusion layer 242, and the drain common pad portion 243 are formed in the Fin portion 233.
　次に、図２１（ａ）及び図２１（ｂ）に示すように、周知のサリサイド技術により、ゲート電極２０６の表面に、ゲート電極上ニッケルシリサイド膜２４４を形成する。同様に、ソース拡散層２４０及びソース共通パッド部２４１の表面には、ソース拡散層上ニッケルシリサイド膜２４５及びソース共通パッド上ニッケルシリサイド膜２４６を形成する。また、ドレイン拡散層２４２及びドレイン共通パッド部２４３の表面には、ドレイン拡散層上ニッケルシリサイド膜２４７及びドレイン共通パッド上ニッケルシリサイド膜２４８を形成する。 Next, as shown in FIGS. 21A and 21B, a nickel silicide film 244 on the gate electrode is formed on the surface of the gate electrode 206 by a known salicide technique. Similarly, a nickel silicide film 245 on the source diffusion layer and a nickel silicide film 246 on the source common pad are formed on the surfaces of the source diffusion layer 240 and the source common pad portion 241. Also, a nickel silicide film 247 on the drain diffusion layer and a nickel silicide film 248 on the drain common pad are formed on the surfaces of the drain diffusion layer 242 and the drain common pad portion 243.
　次に、図２２（ａ）及び図２２（ｂ）に示すように、埋め込み酸化膜２０１の上に各ニッケルシリサイド膜２４４～２４８を覆うように層間絶縁膜２４９を成膜する。その後、成膜した層間絶縁膜２４９に対して、ゲート電極上ニッケルシリサイド膜２４４、ソース共通パッド上ニッケルシリサイド膜２４６及びドレイン共通パッド上ニッケルシリサイド膜２４８をそれぞれ露出する開口部２５０、２５１及び２５２を形成する。 Next, as shown in FIGS. 22A and 22B, an interlayer insulating film 249 is formed on the buried oxide film 201 so as to cover the nickel silicide films 244 to 248. Thereafter, openings 250, 251 and 252 exposing the nickel silicide film 244 on the gate electrode, the nickel silicide film 246 on the source common pad, and the nickel silicide film 248 on the common drain pad are respectively formed in the formed interlayer insulating film 249. Form.
　次に、図２３（ａ）及び図２３（ｂ）に示すように、各開口部２５０、２５１及び２５２をタングステン膜で埋めて、コンタクトプラグ２５３、２５４及び２５５を形成する。 Next, as shown in FIGS. 23A and 23B, the openings 250, 251 and 252 are filled with a tungsten film, and contact plugs 253, 254 and 255 are formed.
　次に、図２４（ａ）、図２４（ｂ）及び図２４（ｃ）に示すように、層間絶縁膜２４９の上に、各コンタクトプラグ２５３、２５４及び２５５とそれぞれ接続される金属配線２５６を形成する。 Next, as shown in FIGS. 24A, 24B and 24C, metal wirings 256 connected to the respective contact plugs 253, 254 and 255 are formed on the interlayer insulating film 249, respectively. Form.
　このように製造されたＮチャネルＭｕｌｔｉ-Ｆｉｎ型トランジスタは、図１６及び図１７の工程で示されるように、シリコン層２０２のレジストマスクによるパターニングをＦｉｎ部２３３と共通パッド部２３４、２３５との２回に分けること（ダブルパターニング）により、Ｆｉｎ部２３３の狭ピッチ化が可能となる。このため、単位面積当たりのＦｉｎの本数を増加する、すなわちＭｕｌｔｉ－Ｆｉｎ型トランジスタの駆動能力を増加させることができる。 In the N-channel Multi-Fin type transistor manufactured in this way, as shown in the steps of FIGS. 16 and 17, patterning of the silicon layer 202 with a resist mask is performed using a Fin portion 233 and common pad portions 234 and 235. By dividing into two times (double patterning), the pitch of the Fin portions 233 can be reduced. Therefore, the number of Fins per unit area can be increased, that is, the driving capability of the Multi-Fin type transistor can be increased.
国際公開第２００８／０５９４４０号パンフレットInternational Publication No. 2008/059440 Pamphlet
　しかしながら、前記従来の製造方法を用いた半導体装置には以下のような問題がある。すなわち、図１６及び図１７の工程からなるダブルパターニングによって、各レジストパターン２３０～２３２は、ほぼ平面方形状の開口部が形成される。しかしながら、図１８に示すシリコン層２０２のエッチング時には、エッチング特性により開口部端が丸まり、その平面形状はほぼ楕円形となる。この丸まりによる開口部の後退量は、８０ｎｍスペースのＭｕｌｔｉ－Ｆｉｎでは約５０ｎｍ程度となる。この後退量は、微細化が進み、スペースが狭くなるにつれて拡大する。この丸まりによってＦｉｎ幅が実質的に広がるため、Ｆｉｎ型トランジスタのチャネル部に用いることができない。このため、この丸まり領域を避けるように、Ｆｉｎ部２３３をあらかじめ長くすることが必要となる。その結果、Ｍｕｌｔｉ－Ｆｉｎ型トランジスタのレイアウト面積が大きくなる。さらには、断面が小さく抵抗が高いＦｉｎ部２３３の長さの増大によって寄生抵抗が増加することから、トランジスタの特性が劣化する。 However, the semiconductor device using the conventional manufacturing method has the following problems. That is, by the double patterning composed of the steps of FIGS. 16 and 17, the resist patterns 230 to 232 are formed with substantially planar openings. However, when the silicon layer 202 shown in FIG. 18 is etched, the end of the opening is rounded due to the etching characteristics, and the planar shape thereof is almost elliptical. The retraction amount of the opening due to the rounding is about 50 nm in the case of Multi-Fin in the 80 nm space. This amount of receding increases as miniaturization progresses and the space becomes narrower. Since this rounding substantially widens the Fin width, it cannot be used for the channel portion of the Fin-type transistor. For this reason, it is necessary to lengthen the Fin portion 233 in advance so as to avoid this rounded region. As a result, the layout area of the multi-fin transistor increases. Furthermore, since the parasitic resistance increases due to the increase in the length of the Fin portion 233 having a small cross section and a high resistance, the characteristics of the transistor deteriorate.
　本発明は、前記の問題を解決し、プロセス工程数を増加させることなく、レイアウト面積が小さく且つ駆動能力が高いＭｕｌｔｉ－Ｆｉｎ型トランジスタを実現できるようにすることを目的とする。 An object of the present invention is to solve the above-mentioned problems and to realize a multi-fin transistor having a small layout area and a high driving capability without increasing the number of process steps.
　前記の目的を達成するため、本発明は、半導体装置を、Ｆｉｎ部にソースドレイン共通パッド領域を形成する構成に代えて、各Ｆｉｎ部の端部同士を一のコンタクトで接続する構成とする。 In order to achieve the above object, according to the present invention, the semiconductor device has a configuration in which the end portions of each Fin portion are connected to each other by one contact instead of the configuration in which the source / drain common pad region is formed in the Fin portion.
　具体的に、本発明に係る半導体装置は、基板の上に形成され、それぞれ互いに間隔をおき且つ並列に配置された直方体状の複数の導電性部材（Ｆｉｎ）と、複数の導電性部材の上に、各導電性部材と交差するように形成されたゲート電極と、複数の導電性部材における少なくとも一方の端部の近傍で、且つ少なくとも２つの導電性部材と電気的に接続されたコンタクトとを備えている。 Specifically, a semiconductor device according to the present invention includes a plurality of rectangular parallelepiped conductive members (Fin) formed on a substrate and spaced apart from each other in parallel, and a plurality of conductive members. A gate electrode formed so as to intersect with each conductive member, and a contact electrically connected to at least two conductive members in the vicinity of at least one end of the plurality of conductive members. I have.
　本発明の半導体装置によると、複数の導電性部材における少なくとも一方の端部の近傍で、且つ少なくとも２つの導電性部材と電気的に接続されたコンタクトを備えている。このため、複数の導電性部材（Ｆｉｎ）は、ソース又はドレインの共通パッド部を設ける必要がなくなるので、Ｆｉｎ部の長さを短くすることができる。これにより、Ｍｕｌｔｉ－Ｆｉｎ型トランジスタのレイアウト面積を縮小し、且つ寄生抵抗を低く抑え、駆動能力を向上することができる。 According to the semiconductor device of the present invention, the contact is provided in the vicinity of at least one end of the plurality of conductive members and electrically connected to at least two conductive members. For this reason, since the plurality of conductive members (Fin) do not need to be provided with a common pad portion for the source or drain, the length of the Fin portion can be shortened. As a result, the layout area of the Multi-Fin transistor can be reduced, the parasitic resistance can be kept low, and the driving capability can be improved.
　本発明の半導体装置において、基板と複数の導電性部材とは絶縁膜により絶縁され、コンタクトは、絶縁膜に達していてもよい。 In the semiconductor device of the present invention, the substrate and the plurality of conductive members may be insulated by an insulating film, and the contact may reach the insulating film.
　このようにすると、コンタクト抵抗を下げることができる。 In this way, the contact resistance can be lowered.
　また、本発明の半導体装置において、コンタクトは、複数の導電性部材の端部よりもゲート電極側に近い位置に形成されていてもよい。 In the semiconductor device of the present invention, the contact may be formed at a position closer to the gate electrode side than the ends of the plurality of conductive members.
　このようにすると、半導体装置をより微細化することができる。 In this way, the semiconductor device can be further miniaturized.
　また、本発明の半導体装置において、コンタクトは、複数の導電性部材の両端に位置する導電性部材よりも内側に形成されていてもよい。 In the semiconductor device of the present invention, the contacts may be formed inside the conductive members located at both ends of the plurality of conductive members.
　このようにすると、半導体装置をより微細化することができる。 In this way, the semiconductor device can be further miniaturized.
　本発明に係る半導体装置の製造方法は、基板の上に直方体状の複数の導電性部材を互いに間隔をおいて並列に配置する工程と、複数の導電性部材の上に各導電性部材と交差すると共にそれぞれ絶縁膜を介在させてゲート電極を形成する工程と、ゲート電極をマスクとして、各導電性部材に不純物を注入することにより、各導電性部材からソースドレイン拡散層を形成する工程と、ソースドレイン拡散層を形成した後、基板の上に、ゲート電極及び各導電性部材を覆うように層間絶縁膜を形成する工程と、層間絶縁膜に対し、複数の導電性部材における少なくとも一方の端部の近傍で且つ少なくとも２つの導電性部材を露出する開口部を形成する工程と、開口部に、露出した導電性部材と電気的に接続されるコンタクトを形成する工程とを備えている。 The method of manufacturing a semiconductor device according to the present invention includes a step of arranging a plurality of rectangular parallelepiped conductive members on a substrate in parallel with a space between each other, and intersecting each conductive member on the plurality of conductive members. And forming a gate electrode through an insulating film, and forming a source / drain diffusion layer from each conductive member by implanting impurities into each conductive member using the gate electrode as a mask, After forming the source / drain diffusion layer, forming an interlayer insulating film on the substrate so as to cover the gate electrode and each conductive member, and at least one end of the plurality of conductive members with respect to the interlayer insulating film A step of forming an opening in the vicinity of the portion and exposing at least two conductive members, and a step of forming a contact electrically connected to the exposed conductive member in the opening. To have.
　本発明の半導体装置の製造方法によると、層間絶縁膜に対し、複数の導電性部材における少なくとも一方の端部の近傍で且つ少なくとも２つの導電性部材を露出する開口部を形成し、その後、開口部に、露出した導電性部材と電気的に接続されるコンタクトを形成する。このため、複数の導電性部材（Ｆｉｎ）は、ソース又はドレインの共通パッド部を設ける必要がなくなるので、Ｆｉｎの長さを短くすることができる。これにより、Ｍｕｌｔｉ－Ｆｉｎ型トランジスタのレイアウト面積を縮小し、且つ寄生抵抗を低く抑え、駆動能力を向上することができる。 According to the method for manufacturing a semiconductor device of the present invention, an opening is formed in the interlayer insulating film in the vicinity of at least one end of the plurality of conductive members and exposing at least two conductive members. A contact that is electrically connected to the exposed conductive member is formed on the portion. For this reason, since the plurality of conductive members (Fin) do not need to be provided with a common pad portion for the source or drain, the length of Fin can be shortened. As a result, the layout area of the Multi-Fin transistor can be reduced, the parasitic resistance can be kept low, and the driving capability can be improved.
　本発明の半導体装置の製造方法は、開口部を形成する工程において、開口部は絶縁膜に達するように形成してもよい。 In the method for manufacturing a semiconductor device of the present invention, the opening may be formed so as to reach the insulating film in the step of forming the opening.
　また、本発明の半導体装置の製造方法は、開口部を形成する工程において、開口部は、複数の導電性部材の端部よりもゲート電極側に近い位置に形成してもよい。 In the method for manufacturing a semiconductor device of the present invention, in the step of forming the opening, the opening may be formed at a position closer to the gate electrode side than the ends of the plurality of conductive members.
　また、本発明の半導体装置の製造方法は、開口部を形成する工程において、開口部は、前記複数の導電性部材の両端に位置する導電性部材よりも内側に形成してもよい。 Further, in the method of manufacturing a semiconductor device of the present invention, in the step of forming the opening, the opening may be formed inside the conductive members positioned at both ends of the plurality of conductive members.
　本発明に係る半導体装置及びその製造方法によれば、複数の導電性部材（Ｆｉｎ）の電気的な接続を一のコンタクトで行うことにより、共通パッド部を設ける必要がなくなるため、Ｆｉｎの長さを短くすることができるので、プロセス工程数を増加させることなく、レイアウト面積が小さく且つ駆動能力が高いＭｕｌｔｉ－Ｆｉｎ型トランジスタを実現することができる。 According to the semiconductor device and the method of manufacturing the same according to the present invention, it is not necessary to provide a common pad portion by electrically connecting a plurality of conductive members (Fin) with one contact. Therefore, a multi-fin transistor having a small layout area and a high driving capability can be realized without increasing the number of process steps.
図１（ａ）及び図１（ｂ）は本発明の一実施形態に係る半導体装置を示し、図１（ａ）は斜視図であり、図１（ｂ）は平面図である。1A and 1B show a semiconductor device according to an embodiment of the present invention, FIG. 1A is a perspective view, and FIG. 1B is a plan view. 図２（ａ）及び図２（ｂ）は本発明の一実施形態に係る半導体装置の製造方法の一工程を示し、図２（ａ）は斜視図であり、図２（ｂ）は平面図である。2A and 2B show a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention, FIG. 2A is a perspective view, and FIG. 2B is a plan view. It is. 図３（ａ）及び図３（ｂ）は本発明の一実施形態に係る半導体装置の製造方法の一工程を示し、図３（ａ）は斜視図であり、図３（ｂ）は平面図である。3A and 3B show a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention, FIG. 3A is a perspective view, and FIG. 3B is a plan view. It is. 図４（ａ）及び図４（ｂ）は本発明の一実施形態に係る半導体装置の製造方法の一工程を示し、図４（ａ）は斜視図であり、図４（ｂ）は平面図である。4 (a) and 4 (b) show one step of the method of manufacturing a semiconductor device according to one embodiment of the present invention, FIG. 4 (a) is a perspective view, and FIG. 4 (b) is a plan view. It is. 図５（ａ）及び図５（ｂ）は本発明の一実施形態に係る半導体装置の製造方法の一工程を示し、図５（ａ）は斜視図であり、図５（ｂ）は平面図である。5A and 5B show a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention, FIG. 5A is a perspective view, and FIG. 5B is a plan view. It is. 図６（ａ）及び図６（ｂ）は本発明の一実施形態に係る半導体装置の製造方法の一工程を示し、図６（ａ）は斜視図であり、図６（ｂ）は平面図である。6 (a) and 6 (b) show a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention, FIG. 6 (a) is a perspective view, and FIG. 6 (b) is a plan view. It is. 図７（ａ）～図７（ｃ）は本発明の一実施形態に係る半導体装置の製造方法の一工程を示し、図７（ａ）は斜視図であり、図７（ｂ）は平面図であり、図７（ｃ）は図７（ａ）のVIIc－VIIc線における断面図である。FIG. 7A to FIG. 7C show one step of the method of manufacturing the semiconductor device according to one embodiment of the present invention, FIG. 7A is a perspective view, and FIG. 7B is a plan view. FIG. 7C is a cross-sectional view taken along the line VIIc-VIIc in FIG. 図８（ａ）及び図８（ｂ）は本発明の一実施形態に係る半導体装置の製造方法の一工程を示し、図８（ａ）は斜視図であり、図８（ｂ）は平面図である。FIG. 8A and FIG. 8B show one step of the method of manufacturing a semiconductor device according to one embodiment of the present invention, FIG. 8A is a perspective view, and FIG. 8B is a plan view. It is. 図９（ａ）～図９（ｃ）は本発明の一実施形態に係る半導体装置の製造方法の一工程を示し、図９（ａ）は斜視図であり、図９（ｂ）は平面図であり、図９（ｃ）は図９（ａ）のIXc－IXc線における断面図である。FIG. 9A to FIG. 9C show one step of the method of manufacturing the semiconductor device according to one embodiment of the present invention, FIG. 9A is a perspective view, and FIG. 9B is a plan view. FIG. 9C is a cross-sectional view taken along the line IXc-IXc in FIG. 図１０（ａ）は本発明の一実施形態に係る半導体装置のシリコン層用のパターニングマスクのレイアウトを示す平面図であり、図１０（ｂ）はエッチング後のシリコンパターン、ゲート電極及びコンタクトプラグのレイアウトを示す平面図である。FIG. 10A is a plan view showing the layout of the patterning mask for the silicon layer of the semiconductor device according to one embodiment of the present invention, and FIG. 10B is the silicon pattern after etching, the gate electrode, and the contact plug. It is a top view which shows a layout. 図１１（ａ）は従来例に係る半導体装置のシリコン層用のパターニングマスクのレイアウトを示す平面図であり、図１１（ｂ）はエッチング後のシリコンパターン、ゲート電極及びコンタクトプラグのレイアウトを示す平面図である。FIG. 11A is a plan view showing a layout of a patterning mask for a silicon layer of a semiconductor device according to a conventional example, and FIG. 11B is a plan view showing a layout of a silicon pattern, a gate electrode and a contact plug after etching. FIG. 図１２は本発明の一実施形態に係る半導体装置におけるＩｄ－Ｖｄ特性のシミュレーション結果を従来例と共に示したグラフである。FIG. 12 is a graph showing a simulation result of Id-Vd characteristics in the semiconductor device according to one embodiment of the present invention together with a conventional example. 図１３（ａ）及び図１３（ｂ）は本発明の一実施形態の第１変形例に係る半導体装置を示し、図１３（ａ）は要部の平面図であり、図１３（ｂ）は図１３（ａ）のXIIIb－XIIIb線における断面図である。FIG. 13A and FIG. 13B show a semiconductor device according to a first modification of one embodiment of the present invention, FIG. 13A is a plan view of the main part, and FIG. It is sectional drawing in the XIIIb-XIIIb line | wire of Fig.13 (a). 図１４（ａ）及び図１４（ｂ）は本発明の一実施形態の第２変形例に係る半導体装置を示し、図１４（ａ）は要部の平面図であり、図１４（ｂ）は図１４（ａ）のXIVb－XIVb線における断面図である。14A and 14B show a semiconductor device according to a second modification of the embodiment of the present invention. FIG. 14A is a plan view of the main part, and FIG. It is sectional drawing in the XIVb-XIVb line | wire of Fig.14 (a). 図１５（ａ）及び図１５（ｂ）は本発明の一実施形態の第３変形例に係る半導体装置を示し、図１５（ａ）は要部の平面図であり、図１５（ｂ）は図１５（ａ）のXVb－XVb線における断面図である。FIG. 15A and FIG. 15B show a semiconductor device according to a third modification of one embodiment of the present invention, FIG. 15A is a plan view of the main part, and FIG. FIG. 16 is a cross-sectional view taken along line XVb-XVb in FIG. 図１６（ａ）及び図１６（ｂ）は従来例に係る半導体装置の製造方法の一工程を示し、図１６（ａ）は斜視図であり、図１６（ｂ）は平面図である。16 (a) and 16 (b) show one step in the method of manufacturing a semiconductor device according to the conventional example, FIG. 16 (a) is a perspective view, and FIG. 16 (b) is a plan view. 図１７（ａ）及び図１７（ｂ）は従来例に係る半導体装置の製造方法の一工程を示し、図１７（ａ）は斜視図であり、図１７（ｂ）は平面図である。17 (a) and 17 (b) show one step of the manufacturing method of the semiconductor device according to the conventional example, FIG. 17 (a) is a perspective view, and FIG. 17 (b) is a plan view. 図１８（ａ）及び図１８（ｂ）は従来例に係る半導体装置の製造方法の一工程を示し、図１８（ａ）は斜視図であり、図１８（ｂ）は平面図である。18 (a) and 18 (b) show one step of the manufacturing method of the semiconductor device according to the conventional example, FIG. 18 (a) is a perspective view, and FIG. 18 (b) is a plan view. 図１９（ａ）及び図１９（ｂ）は従来例に係る半導体装置の製造方法の一工程を示し、図１９（ａ）は斜視図であり、図１９（ｂ）は平面図である。FIG. 19A and FIG. 19B show one step of a method of manufacturing a semiconductor device according to a conventional example, FIG. 19A is a perspective view, and FIG. 19B is a plan view. 図２０（ａ）及び図２０（ｂ）は従来例に係る半導体装置の製造方法の一工程を示し、図２０（ａ）は斜視図であり、図２０（ｂ）は平面図である。20 (a) and 20 (b) show a step of the manufacturing method of the semiconductor device according to the conventional example, FIG. 20 (a) is a perspective view, and FIG. 20 (b) is a plan view. 図２１（ａ）及び図２１（ｂ）は従来例に係る半導体装置の製造方法の一工程を示し、図２１（ａ）は斜視図であり、図２１（ｂ）は平面図である。FIG. 21A and FIG. 21B show one process of the manufacturing method of the semiconductor device according to the conventional example, FIG. 21A is a perspective view, and FIG. 21B is a plan view. 図２２（ａ）及び図２２（ｂ）は従来例に係る半導体装置の製造方法の一工程を示し、図２２（ａ）は斜視図であり、図２２（ｂ）は平面図である。22 (a) and 22 (b) show one step in the method of manufacturing a semiconductor device according to the conventional example, FIG. 22 (a) is a perspective view, and FIG. 22 (b) is a plan view. 図２３（ａ）及び図２３（ｂ）は従来例に係る半導体装置の製造方法の一工程を示し、図２３（ａ）は斜視図であり、図２３（ｂ）は平面図である。FIG. 23A and FIG. 23B show one process of the manufacturing method of the semiconductor device according to the conventional example, FIG. 23A is a perspective view, and FIG. 23B is a plan view. 図２４（ａ）～図２４（ｃ）は従来例に係る半導体装置の製造方法の一工程を示し、図２４（ａ）は斜視図であり、図２４（ｂ）は平面図であり、図２４（ｃ）は図２４（ａ）のXXIVc－XXIVc線における断面図である。24 (a) to 24 (c) show one step in the method of manufacturing a semiconductor device according to the conventional example, FIG. 24 (a) is a perspective view, and FIG. 24 (b) is a plan view. 24 (c) is a cross-sectional view taken along the line XXIVc-XXIVc in FIG. 24 (a).
　（一実施形態）
　本発明の第１の実施形態について図面を参照しながら説明する。 (One embodiment)
A first embodiment of the present invention will be described with reference to the drawings.
　図１（ａ）及び図１（ｂ）は本発明に係る半導体装置であって、ＮチャネルＭｕｌｔｉ－Ｆｉｎ型トランジスタを示し、図１（ａ）は斜視図であり、図１（ｂ）は平面図である。 1A and 1B are semiconductor devices according to the present invention, showing an N-channel Multi-Fin type transistor, FIG. 1A being a perspective view, and FIG. 1B being a plan view. FIG.
　図１（ａ）及び図１（ｂ）に示すように、例えば、シリコンからなる基板１００の主面上には、厚さが８０ｎｍの酸化シリコンからなる埋め込み酸化膜１０１が形成されている。該埋め込み酸化膜１０１の上には、それぞれ高さが５０ｎｍのシリコンからなる直方体状の複数（ここでは３つ）のＦｉｎ部からなるソース拡散層１１０及びドレイン拡散層１１１が、互いに間隔をおき且つ並列に配置されている。 As shown in FIGS. 1A and 1B, for example, an embedded oxide film 101 made of silicon oxide having a thickness of 80 nm is formed on the main surface of a substrate 100 made of silicon. On the buried oxide film 101, a plurality of rectangular parallelepiped source diffusion layers 110 and drain diffusion layers 111 made of silicon each having a height of 50 nm are spaced apart from each other. They are arranged in parallel.
　Ｆｉｎ部の上には、各Ｆｉｎ部と交差すると共にそれぞれゲート絶縁膜（図示せず）を介在させて形成されたゲート電極１０６が形成されている。 On the Fin portion, a gate electrode 106 is formed which intersects with each Fin portion and is formed with a gate insulating film (not shown) interposed therebetween.
　また、ゲート電極１０６、ソース拡散層１１０及びドレイン拡散層１１１の各側面の下部、さらにはゲート電極１０６とソース拡散層１１０及びゲート電極１０６とドレイン拡散層１１１との側面の交差部には、窒化シリコンからなる側壁１０９が形成されている。 Further, nitriding is performed at the lower portion of each side surface of the gate electrode 106, the source diffusion layer 110, and the drain diffusion layer 111, and at the intersection of the side surfaces of the gate electrode 106, the source diffusion layer 110, and the gate electrode 106, the drain diffusion layer 111 A side wall 109 made of silicon is formed.
　埋め込み酸化膜１０１の上には、ゲート電極１０６、ソース拡散層１１０及びドレイン拡散層１１１を覆うように、酸化シリコンからなる層間絶縁膜１１５が形成されている。層間絶縁膜１１５には、ゲート電極１０６と電気的に接続されるゲート電極部コンタクトプラグ１１９が形成されている。また、Ｆｉｎ部であるソース拡散層１１０及びドレイン拡散層１１１とそれぞれ電気的に接続される、ソース拡散層部コンタクトプラグ１２０及びドレイン拡散層部コンタクトプラグ１２１が形成されている。なお、ここでは、ゲート電極１０６、ソース拡散層１１０及びドレイン拡散層１１１の表面に形成されるニッケルシリサイド膜は省略している。 An interlayer insulating film 115 made of silicon oxide is formed on the buried oxide film 101 so as to cover the gate electrode 106, the source diffusion layer 110, and the drain diffusion layer 111. A gate electrode portion contact plug 119 that is electrically connected to the gate electrode 106 is formed in the interlayer insulating film 115. In addition, a source diffusion layer portion contact plug 120 and a drain diffusion layer portion contact plug 121 that are electrically connected to the source diffusion layer 110 and the drain diffusion layer 111 that are Fin portions, respectively, are formed. Here, the nickel silicide films formed on the surfaces of the gate electrode 106, the source diffusion layer 110, and the drain diffusion layer 111 are omitted.
　以下、前記のように構成された半導体装置の製造方法について図面を参照しながら説明する。 Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to the drawings.
　図２～図９は本実施形態に係るＮチャネルＭｕｌｔｉ－Ｆｉｎ型トランジスタの製造方法を示している。なお、各図の（ａ）は斜視図であり、（ｂ）は平面図であり、（ｃ）は断面図である。 2 to 9 show a method for manufacturing an N-channel Multi-Fin transistor according to this embodiment. In addition, (a) of each figure is a perspective view, (b) is a top view, (c) is sectional drawing.
　まず、図２（ａ）及び図２（ｂ）に示すように、シリコンからなる基板１００、厚さが８０ｎｍの埋め込み酸化膜１０１及び厚さが５０ｎｍのシリコン層１０２からなるＳＯＩ基板の上に、リソグラフィ法により、Ｆｉｎ型トランジスタのＦｉｎ部を構成するためのレジストパターン１０３を形成する。 First, as shown in FIGS. 2A and 2B, on a substrate 100 made of silicon, an SOI substrate made of a buried oxide film 101 having a thickness of 80 nm and a silicon layer 102 having a thickness of 50 nm, A resist pattern 103 for forming the Fin portion of the Fin transistor is formed by lithography.
　次に、図３（ａ）及び図３（ｂ）に示すように、レジストパターン１０３をマスクとしてシリコン層１０２をエッチングして、シリコン層１０２から複数のＦｉｎ部１０４を形成する。なお、シリコン層１０２の上に窒化シリコン等からなるマスク形成膜を成膜し、その後、レジストパターン１０３をマスクとしてマスク形成膜をパターニングし、パターニングされたマスク形成膜をハードマスクとして、シリコン層１０２を加工してもよい。 Next, as shown in FIGS. 3A and 3B, the silicon layer 102 is etched using the resist pattern 103 as a mask to form a plurality of Fin portions 104 from the silicon layer 102. Note that a mask formation film made of silicon nitride or the like is formed on the silicon layer 102, and then the mask formation film is patterned using the resist pattern 103 as a mask, and the silicon layer 102 is formed using the patterned mask formation film as a hard mask. May be processed.
　次に、図４（ａ）及び図４（ｂ）に示すように、埋め込み酸化膜１０１及びＦｉｎ部１０４の上に該Ｆｉｎ部１０４と交差するように、ゲート絶縁膜１０５と多結晶シリコンからなるゲート電極１０６とを順次形成する。なお、ゲート絶縁膜１０５には、シリコン酸化膜又はシリコン窒化膜を用いることができる。さらには、ハフニア（酸化ハフニウム）又は酸化ジルコニウム（ジルコニア）等の高誘電率膜を用いてもよい。また、ゲート電極１０６には、多結晶シリコンに代えて、窒化チタン等の金属を含む導電膜とシリコンとの積層膜又はタングステン等の金属膜を用いても構わない。続いて、ヒ素（Ａｓ）イオンを、加速エネルギーが２ｋｅＶで、ドーズ量が２×１０１４ｃｍ－２の注入条件で、且つＳＯＩ基板の法線に対して４５°の角度で、ゲート電極１０６及びＦｉｎ部１０４に対して垂直な四方向から１回ずつ、計４回のイオン注入を行う。これにより、各Ｆｉｎ部１０４には、ソース側ＬＤＤ拡散層１０７及びドレイン側ＬＤＤ拡散層１０８が形成される。 Next, as shown in FIGS. 4A and 4B, the gate insulating film 105 and polycrystalline silicon are formed on the buried oxide film 101 and the Fin portion 104 so as to intersect the Fin portion 104. A gate electrode 106 is sequentially formed. Note that a silicon oxide film or a silicon nitride film can be used for the gate insulating film 105. Furthermore, a high dielectric constant film such as hafnia (hafnium oxide) or zirconium oxide (zirconia) may be used. The gate electrode 106 may be a stacked film of a conductive film containing metal such as titanium nitride and silicon, or a metal film such as tungsten, instead of polycrystalline silicon. Subsequently, arsenic (As) ions are implanted at an acceleration energy of 2 keV, a dose of 2 × 10 14 cm −2 , and at an angle of 45 ° with respect to the normal of the SOI substrate. A total of four times of ion implantation are performed once from four directions perpendicular to the Fin portion 104. As a result, the source side LDD diffusion layer 107 and the drain side LDD diffusion layer 108 are formed in each Fin portion 104.
　次に、図５（ａ）及び図５（ｂ）に示すように、ゲート電極１０６、ソース側ＬＤＤ拡散層１０７及びドレイン側ＬＤＤ拡散層１０８を含め、埋め込み酸化膜１０１の上の全面にわたって、厚さが３０ｎｍのシリコン窒化膜を堆積する。その後、堆積したシリコン窒化膜に対してエッチバックを行って、窒化シリコンからなり、少なくともソース側ＬＤＤ拡散層１０７及びドレイン側ＬＤＤ拡散層１０８を覆う側壁１０９を形成する。続いて、Ａｓイオンを、加速エネルギーが２０ｋｅＶで、ドーズ量が１．５×１０１５ｃｍ－２の注入条件で、且つＳＯＩ基板の法線に対して４５°の角度で、ゲート電極１０６及びＦｉｎ部１０４に対して垂直な四方向から１回ずつ、計４回のイオン注入を行う。これにより、各Ｆｉｎ部１０４には、ソース拡散層１１０及びドレイン拡散層１１１が形成される。 Next, as shown in FIGS. 5A and 5B, the thickness of the entire surface of the buried oxide film 101 including the gate electrode 106, the source side LDD diffusion layer 107 and the drain side LDD diffusion layer 108 is increased. A silicon nitride film having a thickness of 30 nm is deposited. Thereafter, the deposited silicon nitride film is etched back to form a sidewall 109 made of silicon nitride and covering at least the source-side LDD diffusion layer 107 and the drain-side LDD diffusion layer 108. Subsequently, As ions are implanted into the gate electrode 106 and the Fin under the implantation conditions of an acceleration energy of 20 keV and a dose of 1.5 × 10 15 cm −2 and at an angle of 45 ° with respect to the normal of the SOI substrate. A total of four ion implantations are performed once from four directions perpendicular to the portion 104. Thus, the source diffusion layer 110 and the drain diffusion layer 111 are formed in each Fin portion 104.
　次に、図６（ａ）及び図６（ｂ）に示すように、ゲート電極１０６、ソース拡散層１１０及びドレイン拡散層１１１を含め、埋め込み酸化膜１０１の上の全面にわたって、ニッケル膜を堆積する。その後、所定の熱処理を行い、不要なニッケル膜を除去するサリサイド技術により、ゲート電極上ニッケルシリサイド膜１１２、ソース拡散層上ニッケルシリサイド膜１１３及びドレイン拡散層上ニッケルシリサイド膜１１４をそれぞれ形成する。 Next, as shown in FIGS. 6A and 6B, a nickel film is deposited over the entire surface of the buried oxide film 101 including the gate electrode 106, the source diffusion layer 110, and the drain diffusion layer 111. . Thereafter, a predetermined heat treatment is performed, and a nickel silicide film 112 on the gate electrode, a nickel silicide film 113 on the source diffusion layer, and a nickel silicide film 114 on the drain diffusion layer are formed by a salicide technique for removing an unnecessary nickel film, respectively.
　次に、図７（ａ）及び図７（ｂ）に示すように、例えば化学的気相堆積（ＣＶＤ）法により、埋め込み酸化膜１０１の上に各ニッケルシリサイド膜１１２～１１４を覆うように、酸化シリコンからなる層間絶縁膜１１５を成膜する。その後、成膜した層間絶縁膜１１５に対して、ゲート電極上ニッケルシリサイド膜１１２、ソース拡散層上ニッケルシリサイド膜１１３及びドレイン拡散層上ニッケルシリサイド膜１１４をそれぞれ露出する第１のコンタクト開口部１１６、第２のコンタクト開口部１１７及び第３のコンタクト開口部１１８を形成する。ここで、図７（ｃ）の断面図に示すように、第２のコンタクト開口部１１７は、複数のＦｉｎ部からなる複数のソース拡散層１１０に跨って形成され、その底部は各ソース拡散層１１０の上面より深く形成される。なお、複数のドレイン拡散層上ニッケルシリサイド膜１１４を露出する第３のコンタクト開口部１１８も同様である。 Next, as shown in FIGS. 7A and 7B, the nickel silicide films 112 to 114 are covered on the buried oxide film 101 by, for example, chemical vapor deposition (CVD). An interlayer insulating film 115 made of silicon oxide is formed. Thereafter, a first contact opening 116 that exposes the nickel silicide film 112 on the gate electrode, the nickel silicide film 113 on the source diffusion layer, and the nickel silicide film 114 on the drain diffusion layer to the formed interlayer insulating film 115, A second contact opening 117 and a third contact opening 118 are formed. Here, as shown in the cross-sectional view of FIG. 7C, the second contact opening 117 is formed across the plurality of source diffusion layers 110 composed of a plurality of Fin portions, and the bottom thereof is each source diffusion layer. It is formed deeper than the upper surface of 110. The same applies to the third contact opening 118 that exposes the nickel silicide films 114 on the plurality of drain diffusion layers.
　次に、図８（ａ）及び図８（ｂ）に示すように、各コンタクト開口部１１６、１１７及び１１８をタングステン膜で埋めることにより、ゲート電極部コンタクトプラグ１１９、ソース拡散層部コンタクトプラグ１２０及びドレイン拡散層部コンタクトプラグ１２１をそれぞれ形成する。 Next, as shown in FIGS. 8A and 8B, each contact opening 116, 117, and 118 is filled with a tungsten film, so that the gate electrode contact plug 119 and the source diffusion layer contact plug 120 are filled. The drain diffusion layer portion contact plug 121 is formed.
　次に、図９（ａ）、図９（ｂ）及び図９（ｃ）に示すように、層間絶縁膜１１５の上に、ゲート電極部コンタクトプラグ１１９、ソース拡散層部コンタクトプラグ１２０及びドレイン拡散層部コンタクトプラグ１２１と接続される複数の金属配線１２２をそれぞれ形成する。 Next, as shown in FIGS. 9A, 9B, and 9C, on the interlayer insulating film 115, the gate electrode contact plug 119, the source diffusion layer contact plug 120, and the drain diffusion are formed. A plurality of metal wirings 122 connected to the layer contact plug 121 are formed.
　以下、本実施形態に係る半導体装置の効果について、図９（ｃ）、図１０、図１１及び図１２を用いて説明する。 Hereinafter, effects of the semiconductor device according to the present embodiment will be described with reference to FIGS. 9C, 10, 11, and 12.
　まず、図９（ｃ）に示すように、各ソース拡散層１１０は、一のソース拡散層部コンタクトプラグ１２０とその上面及び側面で接触しているため、コンタクト抵抗を低減することができる。 First, as shown in FIG. 9C, each source diffusion layer 110 is in contact with one source diffusion layer portion contact plug 120 on the upper surface and side surfaces thereof, so that the contact resistance can be reduced.
　図１０（ａ）は本実施形態に係るシリコン層用のパターニングマスクのレイアウトを示し、図１０（ｂ）はエッチング後のシリコンパターン、ゲート電極及びコンタクトプラグのレイアウトを示している。図１１（ａ）及び図１１（ｂ）は比較用であって、図１１（ａ）は従来例に係るシリコン層用のパターニングマスクのレイアウトを示し、図１１（ｂ）はエッチング後のシリコンパターン、ゲート電極及びコンタクトプラグのレイアウトを示している。なお、図１０においては、図２、図３、図４及び図８と同一の符号を付しており、図１１においては、図１６、図１８、図１９及び図２３と同一の符号を付している。 FIG. 10A shows the layout of the patterning mask for the silicon layer according to this embodiment, and FIG. 10B shows the layout of the etched silicon pattern, gate electrode, and contact plug. 11A and 11B are for comparison, FIG. 11A shows a layout of a patterning mask for a silicon layer according to a conventional example, and FIG. 11B shows a silicon pattern after etching. 2 shows a layout of gate electrodes and contact plugs. 10, the same reference numerals as those in FIGS. 2, 3, 4, and 8 are given. In FIG. 11, the same reference numerals as those in FIGS. 16, 18, 19, and 23 are given. is doing.
　図１１（ｂ）に示すように、従来例では、シリコン層に対するエッチング後に、エッチングされたシリコン層の開口部（空隙部）の長さが後退して（図中ａ部）、丸まり部（図中ｂ部）が発生する。このａ部及びｂ部によってＦｉｎ部２３３の幅が大きくなるため、トランジスタのチャネルとして用いることはできない。 As shown in FIG. 11B, in the conventional example, after etching the silicon layer, the length of the opening (gap) of the etched silicon layer is retreated (a part in the figure), and the rounded part (FIG. Middle part b) occurs. Since the width of the Fin portion 233 is increased by the a portion and the b portion, it cannot be used as a transistor channel.
　その上、ゲート電極２０６とシリコンパターンとの重ね合わせマージン（図中ｃ）を考慮する必要がある。Ｆｉｎ部２３３のピッチが１００ｎｍ、各Ｆｉｎ幅が２０ｎｍ、ゲート長が３０ｎｍ、及びコンタクトプラグの径が５０ｎｍであると想定した場合、トランジスタピッチ（コンタクトプラグ２５４の中心とコンタクトプラグ２５５の中心との距離）は、２×（ａ＋ｂ）＋ｄ（＝（２×ｃ＋ゲート長））＋コンタクトプラグ径＝２×（１０ｎｍ＋４０ｎｍ）＋（２×２０ｎｍ＋３０ｎｍ）＋５０ｎｍ＝２２０ｎｍとなる。 In addition, it is necessary to consider the overlap margin (c in the figure) between the gate electrode 206 and the silicon pattern. Assuming that the pitch of the Fin portion 233 is 100 nm, each Fin width is 20 nm, the gate length is 30 nm, and the diameter of the contact plug is 50 nm, the transistor pitch (the distance between the center of the contact plug 254 and the center of the contact plug 255) ) Is 2 × (a + b) + d (= (2 × c + gate length)) + contact plug diameter = 2 × (10 nm + 40 nm) + (2 × 20 nm + 30 nm) +50 nm = 220 nm.
　これに対し、図１０（ｂ）に示すように、本実施形態においては、シリコン層に対するエッチング後に、Ｆｉｎ部１０４の長さが短くなる（図中ｅ）、しかしながら、最終加工形状に合わせて、Ｆｉｎ部１０４のマスクレイアウトを長く設計する等、極めて簡単な光近接効果補正（ＯＰＣ）により、Ｆｉｎ部１０４の後退を抑制することができる。このため、Ｆｉｎ部１０４の長さは、ソース拡散層部コンタクトプラグ１２０、ドレイン拡散層部コンタクトプラグ１２１及びゲート電極１０６のそれぞれの重ね合わせマージン（図中ｆ）により決定されることになる。 On the other hand, as shown in FIG. 10B, in this embodiment, the length of the Fin portion 104 is shortened after etching the silicon layer (e in the figure). However, according to the final processing shape, The receding of the Fin portion 104 can be suppressed by an extremely simple optical proximity correction (OPC) such as designing a long mask layout of the Fin portion 104. Therefore, the length of the Fin portion 104 is determined by the respective overlapping margins (f in the figure) of the source diffusion layer portion contact plug 120, the drain diffusion layer portion contact plug 121, and the gate electrode 106.
　従来例と同一の条件を想定した場合、トランジスタピッチは、ｇ（＝（２×ｆ＋ゲート長））＋コンタクト径＝（２×２０ｎｍ＋３０ｎｍ）＋５０ｎｍ＝１２０ｎｍとなる。すなわち、本実施形態においては、トランジスタピッチを約５５％に縮小することができる。 Assuming the same conditions as in the conventional example, the transistor pitch is g (= (2 × f + gate length)) + contact diameter = (2 × 20 nm + 30 nm) +50 nm = 120 nm. That is, in this embodiment, the transistor pitch can be reduced to about 55%.
　図１２は本実施形態に係るＮチャネルＭｕｌｔｉ－Ｆｉｎ型トランジスタの電流電圧（Ｉｄ－Ｖｄ）特性のシミュレーション結果を従来例と共に表している。 FIG. 12 shows the simulation result of the current-voltage (Id-Vd) characteristics of the N-channel Multi-Fin transistor according to this embodiment together with the conventional example.
　本実施形態においては、高抵抗の幅が細いＦｉｎ部１０４の長さを、従来例の６０ｎｍから２０ｎｍに短縮することができる。このため、寄生抵抗を削減できる結果、図１２に示すように、約１５％トランジスタの駆動力を向上させることができる。 In the present embodiment, the length of the fin portion 104 having a narrow high resistance width can be reduced from 60 nm of the conventional example to 20 nm. As a result, the parasitic resistance can be reduced. As a result, as shown in FIG. 12, the driving power of the transistor can be improved by about 15%.
　（一実施形態の第１変形例）
　以下、本発明の一実施形態の第１変形例について図面を参照しながら説明する。 (First Modification of One Embodiment)
Hereinafter, a first modification of one embodiment of the present invention will be described with reference to the drawings.
　図１３（ａ）及び図１３（ｂ）、特に図１３（ｂ）に示すように、ソース拡散層部コンタクトプラグ１２０及びドレイン拡散層部コンタクトプラグ１２１は、埋め込み酸化膜１０１に達するように形成されている。このようにすると、各コンタクトプラグ１２０、１２１の接触面積をそれぞれ増やすことができるため、コンタクト抵抗を低減することができる。 As shown in FIGS. 13A and 13B, particularly FIG. 13B, the source diffusion layer portion contact plug 120 and the drain diffusion layer portion contact plug 121 are formed so as to reach the buried oxide film 101. ing. In this way, the contact area of each contact plug 120, 121 can be increased, and the contact resistance can be reduced.
　（一実施形態の第２変形例）
　次に、本発明の一実施形態の第２変形例について図面を参照しながら説明する。 (Second Modification of One Embodiment)
Next, a second modification of the embodiment of the present invention will be described with reference to the drawings.
　図１４（ａ）及び図１４（ｂ）、特に図１４（ａ）に示すように、ソース拡散層部コンタクトプラグ１２０及びドレイン拡散層部コンタクトプラグ１２１は、複数のＦｉｎ部１０４の各端部よりもゲート電極１０６側に近い位置に形成されている。このようにすると、一トランジスタ当たりの占有面積が縮小するため、トランジスタのさらなる微細化及び高集積化が可能となる。 As shown in FIGS. 14A and 14B, particularly FIG. 14A, the source diffusion layer portion contact plug 120 and the drain diffusion layer portion contact plug 121 are provided from the end portions of the plurality of Fin portions 104. Is also formed at a position close to the gate electrode 106 side. In this case, since the occupied area per transistor is reduced, the transistor can be further miniaturized and highly integrated.
　（一実施形態の第３変形例）
　次に、本発明の一実施形態の第３変形例について図面を参照しながら説明する。 (Third Modification of One Embodiment)
Next, a third modification of the embodiment of the present invention will be described with reference to the drawings.
　図１５（ａ）及び図１５（ｂ）、特に図１５（ａ）に示すように、ソース拡散層部コンタクトプラグ１２０及びドレイン拡散層部コンタクトプラグ１２１は、複数のＦｉｎ部１０４のうちの両端のＦｉｎ部１０４よりも内側に形成されている。このようにすると、一トランジスタ当たりの占有面積が縮小するため、トランジスタのさらなる微細化及び高集積化が可能となる。 As shown in FIGS. 15A and 15B, particularly FIG. 15A, the source diffusion layer portion contact plug 120 and the drain diffusion layer portion contact plug 121 are provided at both ends of the plurality of Fin portions 104. It is formed inside the Fin portion 104. In this case, since the occupied area per transistor is reduced, the transistor can be further miniaturized and highly integrated.
　なお、以上の各変形例は、本実施形態の図７（ｂ）、図７（ｃ）、図９（ｂ）及び図９（ｃ）と対応する構成を模式的に表している。また、これらの各変形例を任意に組み合わせることにより、それぞれの効果を相乗させることも可能である。 Note that each of the above-described modifications schematically represents a configuration corresponding to FIGS. 7B, 7C, 9B, and 9C of the present embodiment. Moreover, it is also possible to make each effect synergistic by combining these each modified example arbitrarily.
　本発明に係る半導体装置及びその製造方法は、Ｆｉｎの長さを短くすることができ、その結果、プロセス工程数を増加させることなく、レイアウト面積が小さく且つ駆動能力が高いＭｕｌｔｉ－Ｆｉｎ型トランジスタを実現することができ、Ｆｉｎ型トランジスタ及びその製造方法等に有用である。 The semiconductor device and the manufacturing method thereof according to the present invention can reduce the length of Fin, and as a result, a Multi-Fin type transistor having a small layout area and a high driving capability without increasing the number of process steps. It can be realized and is useful for a Fin-type transistor and a manufacturing method thereof.
１００　　基板
１０１　　埋め込み酸化膜
１０３ 　レジストパターン
１０４　　Ｆｉｎ部
１０５　　ゲート絶縁膜
１０６　　ゲート電極
１０７　　ソース側ＬＤＤ拡散層
１０８　　ドレイン側ＬＤＤ拡散層
１０９　　側壁
１１０　　ソース拡散層
１１１　　ドレイン拡散層
１１２　　ゲート電極上ニッケルシリサイド膜
１１３　　ソース拡散層上ニッケルシリサイド膜
１１４　　ドレイン拡散層上ニッケルシリサイド膜
１１５　　層間絶縁膜
１１６　　第１のコンタクト開口部
１１７　　第２のコンタクト開口部
１１８　　第３のコンタクト開口部
１１９　　ゲート電極部コンタクトプラグ
１２０　　ソース拡散層部コンタクトプラグ
１２１　　ドレイン拡散層部コンタクトプラグ
１２２　　金属配線 100 Substrate 101 Embedded oxide film 103 Resist pattern 104 Fin portion 105 Gate insulating film 106 Gate electrode 107 Source side LDD diffusion layer 108 Drain side LDD diffusion layer 109 Side wall 110 Source diffusion layer 111 Drain diffusion layer 112 Nickel silicide film 113 on gate electrode Nickel silicide film on diffusion layer 114 Nickel silicide film on drain diffusion layer 115 Interlayer insulating film 116 First contact opening 117 Second contact opening 118 Third contact opening 119 Gate electrode contact plug 120 Source diffusion layer Contact plug 121 Drain diffusion layer contact plug 122 Metal wiring

Claims (8)

  1. 　基板の上に形成され、それぞれ互いに間隔をおき且つ並列に配置された直方体状の複数の導電性部材と、
    　前記複数の導電性部材の上に、前記各導電性部材と交差するように形成されたゲート電極と、
    　前記複数の導電性部材における少なくとも一方の端部の近傍で、且つ少なくとも２つの導電性部材と電気的に接続されたコンタクトとを備えている半導体装置。     A plurality of rectangular parallelepiped conductive members formed on the substrate and spaced apart from each other and arranged in parallel;
    A gate electrode formed on the plurality of conductive members so as to intersect the conductive members;
    A semiconductor device comprising a contact in the vicinity of at least one end portion of the plurality of conductive members and electrically connected to at least two conductive members.
  2. 　請求項１において、
    　前記基板と前記複数の導電性部材とは絶縁膜により絶縁され、
    　前記コンタクトは、前記絶縁膜に達する半導体装置。     In claim 1,
    The substrate and the plurality of conductive members are insulated by an insulating film,
    The contact is a semiconductor device that reaches the insulating film.
  3. 　請求項１又は２において、
    　前記コンタクトは、前記複数の導電性部材の端部よりも前記ゲート電極側に近い位置に形成されている半導体装置。     In claim 1 or 2,
    The contact is a semiconductor device formed at a position closer to the gate electrode side than ends of the plurality of conductive members.
  4. 　請求項１～３のいずれか１項において、
    　前記コンタクトは、前記複数の導電性部材の両端に位置する導電性部材よりも内側に形成されている半導体装置。     In any one of claims 1 to 3,
    The said contact is a semiconductor device currently formed inside the electroconductive member located in the both ends of these electroconductive members.
  5. 　基板の上に、直方体状の複数の導電性部材を互いに間隔をおいて並列に配置する工程と、
    　前記複数の導電性部材の上に、前記各導電性部材と交差すると共にそれぞれ絶縁膜を介在させてゲート電極を形成する工程と、
    　前記ゲート電極をマスクとして、前記各導電性部材に不純物を注入することにより、前記各導電性部材からソースドレイン拡散層を形成する工程と、
    　前記ソースドレイン拡散層を形成した後、前記基板の上に、前記ゲート電極及び前記各導電性部材を覆うように層間絶縁膜を形成する工程と、
    　前記層間絶縁膜に対し、前記複数の導電性部材における少なくとも一方の端部の近傍で、且つ少なくとも２つの導電性部材を露出する開口部を形成する工程と、
    　前記開口部に、露出した導電性部材と電気的に接続されるコンタクトを形成する工程とを備えている半導体装置の製造方法。     On the substrate, a plurality of rectangular parallelepiped conductive members arranged in parallel with an interval between each other;
    Forming a gate electrode on each of the plurality of conductive members, intersecting with each of the conductive members and interposing an insulating film, respectively;
    Forming a source / drain diffusion layer from each conductive member by implanting impurities into each conductive member using the gate electrode as a mask;
    Forming an interlayer insulating film on the substrate so as to cover the gate electrode and each conductive member after forming the source / drain diffusion layer;
    Forming an opening in the interlayer insulating film in the vicinity of at least one end of the plurality of conductive members and exposing at least two conductive members;
    Forming a contact electrically connected to the exposed conductive member in the opening.
  6. 　請求項５において、
    　前記開口部を形成する工程では、
    　前記開口部は、前記絶縁膜に達するように形成する半導体装置の製造方法。     In claim 5,
    In the step of forming the opening,
    The method of manufacturing a semiconductor device, wherein the opening is formed to reach the insulating film.
  7. 　請求項５又は６において、
    　前記開口部を形成する工程では、
    　前記開口部は、前記複数の導電性部材の端部よりも前記ゲート電極側に近い位置に形成する半導体装置の製造方法。     In claim 5 or 6,
    In the step of forming the opening,
    The method of manufacturing a semiconductor device, wherein the opening is formed at a position closer to the gate electrode side than ends of the plurality of conductive members.
  8. 　請求項５～７のいずれか１項において、
    　前記開口部を形成する工程では、
    　前記開口部は、前記複数の導電性部材の両端に位置する導電性部材よりも内側に形成する半導体装置の製造方法。     In any one of claims 5 to 7,
    In the step of forming the opening,
    The method of manufacturing a semiconductor device, wherein the opening is formed inside a conductive member positioned at both ends of the plurality of conductive members.
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