KR100824919B1 - Transistor of a semiconductor device and method of manufacturing thereof - Google Patents

Abstract

A transistor of a semiconductor device and a method for manufacturing the same are provided to suppress a drain leakage current due to a gate by forming a drain contact apart from a gate in a center of a drain region. An isolation region and an active region are defined on a semiconductor substrate(100). An isolation layer(102) is formed on the isolation layer of the semiconductor substrate. A gate pattern is formed in a predetermined region of the active region. Source and drain regions(110,112) are formed on the active region between the gate pattern and the isolation layer and are separated from the isolation layer. Source and drain contacts(116,118) are connected to surfaces of the source and drain regions. A gap between the drain contact and the gate pattern is larger than a gap between the drain contact and an edge of the drain region.

Description

Transistor of semiconductor device and method of manufacturing thereof

1A and 1B are a cross-sectional view and a layout view of a device for explaining a transistor structure of a semiconductor device according to the prior art.

2 is a graph illustrating BVDSS characteristics of a high voltage transistor of a semiconductor device according to the related art.

3 to 5B are cross-sectional views and layout views of devices for describing a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 device isolation film

104: gate oxide film 106: gate conductive film

108: ion implantation mask 110: source region

112 drain region 114 interlayer insulating film

116: source contact 118: drain contact

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same, and more particularly to a high voltage transistor and a method of manufacturing the same.

The NAND flash memory device performs program operation and erase operation using a Fowler-Nordheim tunneling (FN-tunneling) method. That is, a potential difference is generated between the gate and the substrate to generate the movement of electrons. A high voltage of 20V is used to generate effective FN tunneling, and a transistor capable of withstanding 20V or more of breakdown voltage of a junction is required to generate such a high voltage and transport it to the cell region.

1A and 1B are a layout view and a cross-sectional view of a high voltage transistor of a semiconductor device according to the prior art.

Referring to FIGS. 1A and 1B, a symmetrical source is formed on both sides of a gate pattern in which a gate oxide layer 12 and a gate conductive layer 15 are sequentially stacked on a P or N type doped semiconductor substrate 10. And the contacts 13 and 14 connected to the / drain region 11 and the source / drain region 11, respectively.

2 is a graph illustrating BVDSS characteristics of a high voltage transistor of a semiconductor device according to the related art.

In the high voltage transistor configured as shown in FIG. 1, a repetitive high voltage is applied to the source / drain region to generate a breakdown phenomenon in the junction region. This is caused by a high drain voltage, the electric field is strongly generated on the surface of the semiconductor substrate in the overlapping portion of the gate and drain region, and the charge generated by the drain is partially trapped in the gate oxide film. This state stresses the gate oxide layer and increases the tunneling current due to the effect of gate induced drain leakage (GIDL) by the drain voltage. As a result, they cannot sustain high voltage and the device is destroyed at a low voltage, thereby preventing them from serving as a high voltage transistor.

The technical problem to be achieved by the present invention is to separate the source and drain regions and the device isolation region using an ion implantation mask to prevent leakage current easily occurring at the interface, the drain contact is located far from the gate side from the central portion of the drain region The present invention provides a transistor and a manufacturing method for a semiconductor device capable of suppressing the drain leakage current caused by the gate.

A transistor of a semiconductor device according to an embodiment of the present invention may include an isolation layer formed in the isolation region of a semiconductor substrate divided into an isolation region and an active region, a gate pattern formed in a predetermined region of the active region, and the gate pattern Source and drain regions formed in both directions of the active region adjacent to the source and source and drain contacts respectively connected to surfaces of the source and drain regions, wherein the source and drain regions are spaced apart from an interface of the device isolation layer. The drain contact is farther from the gate pattern than the edge of the drain region.

A size of the drain region is 1.5 to 2 times larger than a size of the source region, a distance between the drain contact and the gate pattern is 0.7 to 1 μm, and a distance between the drain contact and an edge of the drain region is 0.2 to 0.3 μm.

In the method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention, forming a device isolation film in the device isolation region of the semiconductor substrate defined by the device isolation region and the active region, and on the entire structure including the device isolation film Sequentially forming a gate oxide film and a gate conductive film, performing an etching process to form a gate pattern by remaining the gate oxide film and the gate conductive film in a predetermined region of the active region, and ion implantation using an ion implantation mask Forming a source and a drain region on the active region adjacent to the gate pattern, wherein the source and the drain region are spaced apart from the device isolation layer, and interlayer on the entire structure including the source and drain region. Forming an insulating film, and said source and drain Forming a contact hole through which a portion of the phosphorus region is exposed, and filling the conductive hole with a conductive material to form a source and a drain contact plug, wherein a distance between the drain contact and the gate pattern is a distance between an edge of the drain contact plug and the drain region. Forming further away.

The method may further include performing a heat treatment process after the ion implantation process and before forming the interlayer insulating film. The heat treatment process may be performed at a temperature of 800 to 1000 ° C. in a rapid heat treatment process.

The drain region is formed to have a size 1.5 to 2 times larger than that of the source region, the distance between the drain contact plug and the gate pattern is 0.7 to 1 μm, and the distance between the edge of the drain contact plug and the drain region is 0.2. To 0.3 µm.

In the ion implantation step, impurities are dosed at a dose of about 1E12 to 1E13 atoms / cm 2, and the gate oxide film is formed to a thickness of 300 to 500 kPa.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 to 5B are cross-sectional views and layout views of devices for describing a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, an element isolation process is performed in an element isolation region of the semiconductor substrate 100 to form an element isolation layer 102. Thereafter, the gate oxide film 104 and the gate conductive film 106 are sequentially formed on the entire structure including the device isolation film 102. The gate oxide film 104 is preferably formed to a thickness of 300 to 500 kPa. Subsequently, the gate etching process is performed so that the gate oxide layer 102 and the gate conductive layer 106 remain only in a predetermined region on the active region where the device isolation layer 102 is not formed.

Referring to FIG. 4, an ion implantation mask 108 for performing an ion implantation process is formed. In this case, the ion implantation mask 108 performs a subsequent ion implantation process so that the region formed is spaced apart from the device isolation layer 102. That is, the ion implantation mask 108 is formed so that the semiconductor substrate 100 adjacent to the device isolation layer 102 is not exposed in the exposed active region of the semiconductor substrate 100.

Thereafter, an ion implantation process is performed to form the source region 110 and the drain region 112 in the active region of the exposed semiconductor substrate 100. Thereafter, a heat treatment process is performed to diffuse the source region 110 and the drain region 112. The separation distance may be adjusted through the ion implantation mask 108 such that the diffused source region 110 and the drain region 112 do not contact the interface of the device isolation layer 102. In addition, the drain region 112 is formed to be larger than the source region 110. This is to increase the breakdown voltage in order to prevent the breakdown phenomenon caused by the high drain voltage. The size of the drain region 112 is preferably formed to be 1.5 to 2 times larger than the size of the source region 110. The ion implantation step is preferably performed with a dose of about 1E12 to 1E13 atoms / cm 2. The heat treatment step is preferably carried out at a temperature of 800 to 1000 ℃ using a rapid heat treatment method.

Since the interface of the device isolation layer 102 and the interface of the source region 110 and the drain region 112 are spaced apart from each other, leakage current easily occurring at their contact surfaces can be prevented. That is, the BVDSS characteristics can be improved.

Referring to FIG. 5A, after removing the ion implantation mask, an interlayer insulating layer 114 is formed on the entire structure including the source region 110 and the drain region 112. The interlayer insulating film 114 is preferably formed of an oxide film. Thereafter, an etching process for forming contact holes is performed to form source contact holes and drain contact holes through which a portion of the source region 110 and the drain region 112 are exposed. In this case, the source contact hole is formed so that the center portion of the source region 110 is exposed, and the drain contact hole is formed so that the region spaced apart from the gate patterns 102 and 104 from the drain region 112 by a predetermined distance B is exposed. Thereafter, the source contact hole and the drain contact hole are filled with a conductive film to form the source contact 116 and the drain contact 118. The distance between the source contact 116 and the gate patterns 104 and 106 is 0.2 to 0.3 mu m, and the distance between the drain contact 118 and the gate patterns 104 and 106 is preferably 0.7 to 1 mu m. The drain leakage current (GIDL) decreases as the distance between the contact and the gate increases. Therefore, the drain contact 118 is formed far from the gate patterns 104 and 106 to reduce the drain leakage current.

Referring to FIG. 5B, the drain contact 118 is formed such that the gate conductive film 106 is separated by a predetermined distance (B).

By forming the device isolation region 102 and the source and drain regions 110 and 112 apart from each other, leakage current generated at the interface can be prevented, and the drain contact 118 connected to the drain region 112 can be formed by a gate pattern ( 104, 106) As far as possible, the GIDL characteristics can be improved to form high-voltage transistors of highly reliable semiconductor devices.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, an ion implantation mask is used to separate the source and drain regions from the device isolation region to prevent leakage current that is likely to occur at the interface, and the drain contact is far from the gate side at the center of the drain region. Formation at this point can suppress the drain leakage current caused by the gate.

Claims (14)

An isolation layer formed in the isolation region of the semiconductor substrate divided into an isolation region and an active region; A gate pattern formed on a predetermined region of the active region; Source and drain regions formed in the active region between the gate pattern and the device isolation layer and spaced apart from the device isolation layer; And source and drain contacts connected to surfaces of the source and drain regions, respectively. The method of claim 1, And the drain contact is farther away from the gate pattern than the edge of the drain region. The method of claim 1, The size of the drain region is a transistor of a semiconductor device 1.5 to 2 times larger than the size of the source region. The method of claim 1, And a distance between the drain contact and the gate pattern is 0.7 to 1 μm. The method of claim 1, And a distance between the drain contact and an edge of the drain region is 0.2 to 0.3 mu m. Forming an isolation layer in the isolation region of the semiconductor substrate, the isolation region being an isolation region and an active region; Sequentially forming a gate oxide film and a gate conductive film on the entire structure including the device isolation film; Performing an etching process to form a gate pattern by leaving the gate oxide layer and the gate conductive layer in a predetermined region of the active region; Performing ion implantation using an ion implantation mask to form source and drain regions on the active region adjacent to the gate pattern, wherein the source and drain regions are spaced apart from the device isolation layer; Forming an interlayer insulating film on the entire structure including the source and drain regions; And Forming a source and a drain contact plug in a portion of the source and drain regions. The method of claim 6, The forming of the source and drain contact plugs may be performed such that a distance between the drain contact plug and the gate pattern is greater than a distance between an edge of the drain contact plug and the drain region. The method of claim 6, And performing a heat treatment step after the ion implantation step and before forming the interlayer insulating film. The method of claim 8, The heat treatment step is a rapid heat treatment step of a transistor manufacturing method of a semiconductor device performed at a temperature of 800 to 1000 ℃. The method of claim 6, And the drain region is formed to be 1.5 to 2 times larger than the size of the source region. The method of claim 6, And a distance between the drain contact plug and the gate pattern is 0.7 to 1 μm. The method of claim 6, And a distance between the drain contact plug and the edge of the drain region is 0.2 to 0.3 mu m. The method of claim 6, The ion implantation process is a transistor manufacturing method of a semiconductor device in which impurities are carried out with a dose of about 1E12 to 1E13 atoms / cm 2. The method of claim 6, The gate oxide film is a transistor manufacturing method of a semiconductor device to form a thickness of 300 to 500Å.

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