KR20050086291A - Method of manufacturing nand flash memory device - Google Patents

Abstract

The present invention relates to a method for manufacturing a NAND flash memory device. The present invention provides a drain contact plug in a cell region and a junction contact plug in a high voltage device region using doped polycrystalline silicon, and then performs a predetermined thermal process. Contact resistance can be reduced without additional junction ion implantation, and the on-current characteristics of the high voltage transistor can be improved by maintaining the impurity concentration of the junction at a target level. Provided is a method of manufacturing a NAND flash memory device capable of greatly improving characteristics.

Description

Method of manufacturing NAND flash memory device {Method of manufacturing NAND flash memory device}

The present invention relates to a method for manufacturing a NAND flash memory device, and more particularly, to a method for forming a junction contact for a high voltage device of a NAND flash device.

In general, NAND flash memory uses FN tunneling in the program of a cell, unlike NOR flash memory. The FN tunneling program has the advantage of being able to program a large number of cells at the same time by consuming less current, but a higher voltage transistor capable of controlling the high voltage is required because a higher voltage must be applied during program and erase operations. . Since high voltage transistors used in NAND flash memory must use high voltages of 15V or higher, they must have a structure different from that of a general transistor. In other words, to operate at 15V, a high junction breakdown voltage of more than 25V must be shown. Therefore, instead of the P type well structure, a P type semiconductor substrate is used as a well to form a transistor. Junction is formed by using N type impurities. The source / drain region of the junction is connected to the outside through the metal filling of the contact, whereby additional plug ion implantation is performed after the contact is formed to prevent the formation of non-ohmic contact between the metal and the junction. In addition to compensating, the structure of the junction is maintained in proper order.

Since the junction ion implantation must be performed separately in the high voltage device region for NMOS, a separate masking process must be additionally performed, and the characteristics of the high voltage transistor are greatly affected by the junction ion implantation process conditions. Happens.

Therefore, the present invention uses a doped polycrystalline silicon film, which is used as a contact plug in a cell region, for junction contact in a high voltage device region for NMOS to solve the above problem, thereby reducing contact resistance without performing a junction ion implantation process. The present invention provides a method of manufacturing a NAND flash memory device capable of improving the reliability of the device.

Forming a first interlayer insulating film on a semiconductor substrate on which a high voltage device transistor is formed in a first region and a flash memory cell is formed in a second region, and patterning the first interlayer insulating film; Forming a source contact hole for opening the source terminal of the cell, and then embedding and planarizing it with a first conductive material film to form a source line plug, forming a second interlayer insulating film over the entire structure, and then Patterning a second interlayer insulating film to form a junction contact hole for opening the junction region of the high voltage device transistor in the first region and a drain contact hole for opening the drain terminal of the flash memory cell in the second region; And planarizing the junction contact hole and the drain contact hole with a second conductive material film doped with a predetermined impurity. And forming a junction contact plug and a drain contact plug, and performing a heat treatment process for diffusion of impurities in the junction contact plug and the drain contact plug.

Preferably, the second conductive film is effective to use a polycrystalline silicon film doped with Phosphorous (P) or Arsenic (As) 1.0E19 to 5.0E20.

Preferably, the heat treatment step is effective to be carried out in the temperature range of 700 to 1000 ℃ using the furnace.

Preferably, the method may further include sequentially forming an etch stop layer and a third interlayer insulating layer on the entire structure between the step of forming the junction contact plug and the drain contact plug and performing the heat treatment process. .

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1A to 1C are cross-sectional views illustrating a method of manufacturing a NAND flash device according to the present invention.

Referring to FIG. 1A, a transistor for a high voltage device is formed in a first area A of a semiconductor substrate 10 in which a first region A in which a high voltage device is to be formed and a second region B in which a flash memory cell are to be defined are defined. 20 and a flash memory cell 30 are formed in the second region B. As shown in FIG.

The flash memory cell 30 of the second region B is configured in a string form, and both sides thereof select a drain select transistor 40 and a source terminal 47 for selecting the drain terminal 49 of the cell. A source select transistor 45 may be further included.

In the above description, the device isolation layer may be formed through a self-aligned shallow trench isolation process, or the floating gate electrode may be formed through a self-aligned floating gate electrode process. The gate oxide film formed in the first region A is preferably formed to a thickness sufficient to operate even at a high voltage. The high voltage device transistor 20 is preferably formed of the junction 22 of the DDD structure. The junction of the high voltage device transistor 20 is preferably formed by injecting N-type impurities of about 1.0E12 to 1.0E14. As the high voltage device transistor 20, an NMOS transistor is preferably used.

Referring to FIG. 1B, a first interlayer insulating film 50 is deposited on the entire structure, and then a source line contact for opening the source terminal 47 of the flash memory cell 30 in the second region B is formed. A source line plug 60 is formed by filling the source line contact with the first conductive material layer.

The source line contact preferably opens the source region of the source select transistor 45. It is preferable to use a doped polycrystalline silicon film as the first conductive material film. It is preferable to use a silicon film doped with Phosphorous (P) or Arsenic (As) as the doped polycrystalline silicon film.

The source line plug 60 may be formed by filling the source line contact with the first conductive material film, and then etching the entire surface by etching the planarization process to remove the conductive material film on the first interlayer insulating film 50. Do. The planarization step may be carried out using a chemical mechanical polishing step (CMP).

A barrier film for protecting the underlying structure may be further deposited before the first interlayer insulating film 50 is formed.

Referring to FIG. 1C, after forming the second interlayer insulating film 70 on the entire structure, a junction contact hole for opening the junction region 22 of the first region A is formed, and the second region B A drain contact hole for opening the drain terminal 49 of the flash memory cell 30 is formed. The junction contact hole and the drain contact hole are buried and planarized with a second conductive material film to form the junction contact plug 80 and the drain contact plug 90. The etch stop layer 100 and the third interlayer insulating layer 110 are deposited on the entire structure, and then a heat treatment process is performed. The metal line forming process is performed to form the bit line 120 on the drain contact plug 90 and the metal wire 125 on the junction contact plug 80.

The junction contact hole and the drain contact hole apply a photoresist film on the second interlayer insulating film 70, and then form a photoresist pattern through a photolithography process using a mask. The second interlayer insulating film 70 and the first interlayer insulating film 50 are preferably etched by performing an etching process using the photoresist pattern as an etching mask. That is, when forming the drain contact hole of the second region B, it is effective to simultaneously open the junction contact hole region together.

As the second conductive material film, a doped polycrystalline silicon film is preferably used, and the doped polycrystalline silicon film is preferably a phosphorous (P) or arsenic (Asonic) As 1.0E19 to 5.0E20 doped film. The second conductive material film is preferably formed to a thickness such that the drain contact hole and the junction contact hole are sufficiently filled.

The drain contact plug 90 and the junction contact plug 80 deposit a second conductive material film on the entire structure, and then perform a planarization process using an entire surface etching process to remove the second conductive material film on the second interlayer insulating film 70. It is preferable to form. As the planarization process, a chemical mechanical polishing process may be used.

On the second interlayer insulating film 70 on which the drain contact plug 90 and the junction contact plug 80 are formed, an etch stop film 100 using a nitride film-based material film is formed, but the thin film having a thickness of 200 to 500 Å is formed. desirable. In this case, the etch stop layer 100 may be omitted to prevent a problem caused by the excessive etching process in the subsequent process.

The third interlayer insulating layer 110 is sequentially deposited on the etch stop layer 100. After deposition of the third interlayer insulating layer 110, it is preferable to perform a heat treatment process for diffusion of impurities in the second conductive material film forming the drain contact plug 90 and the junction contact plug 80. The heat treatment process is preferably such that the diffusion of phosphorus and arsenic of the second conductive material film to the junction region 22 of the semiconductor substrate 10 in the temperature range of 700 to 1000 ℃. Through such a thermal process, impurities doped in the polycrystalline silicon film are diffused from the polycrystalline silicon into the junction region to properly compensate the impurity concentration of the junction generated during the etching process.

As described above, since the doped impurities in the junction contact plug diffuse into the junction region through the heat treatment process, the same effect as the heat treatment process after the plug ion implantation, which is generally performed, can be obtained.

In this embodiment, it is preferable to perform a sufficient heat treatment through a furnace (Furnace) for sufficient diffusion of impurities. This sufficient thermal process limits the amount of impurities contained in the polycrystalline silicon and limits the impurities that can be moved by diffusion, so that current characteristics can be reduced without degrading the basic characteristics of the existing high voltage transistor formed by the junction of the DDD structure. Can also be improved.

It is preferable to form the first to third interlayer insulating films of the present embodiment using an oxide film-based material film. In addition, the thickness thereof is preferably 1000 to 5000 kPa and formed to a sufficient thickness in consideration of insulation between the wiring or the plug.

2A and 2B are graphs showing characteristics of a junction plug using a doped polysilicon film.

FIG. 2A is a graph illustrating a junction doping profile of a transistor when impurities are not diffused in the junction region during contact formation and when a predetermined impurity is diffused in the junction region according to the present invention. It can be seen that the concentration of impurities is about 100 times lower than when diffused. In addition, FIG. 2B is a result of measuring the on current of the high voltage device. When impurities are not diffused, the increase in contact resistance and the low on current of the high voltage transistor are reduced. When the impurity diffusion is performed in the junction region, the doping concentration of the junction can be prevented from being reduced, the increase in contact resistance can be prevented, and the on current of the high voltage transistor can be improved to prevent the delay problem of the device. Will be.

As described above, the present invention forms a drain contact plug in a cell region and a junction contact plug in a high voltage element region using doped polycrystalline silicon, and then performs a predetermined thermal process without performing a separate junction ion implantation. It is possible to reduce the contact resistance.

In addition, the on-current characteristics of the high-voltage transistor can be improved by maintaining the impurity concentration of the junction at a target level, and the characteristics of the high-voltage transistor can be greatly improved.

1A to 1C are cross-sectional views illustrating a method of manufacturing a NAND flash device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 20 transistor for high voltage device

30 flash memory cell 40 drain select transistor

45: source select transistor 47: source terminal

49: drain terminal 50, 70, 110: interlayer insulating film

60: source line plug 80: junction contact plug

90: drain contact plug 100: etching prevention film

120, 125: metal wiring

Claims (4)

Forming a first interlayer insulating film on a semiconductor substrate having a high voltage device transistor formed in a first region and a flash memory cell formed in a second region; Patterning the first interlayer insulating film to form a source contact hole for opening a source terminal of the flash memory cell, and then filling the first interlayer insulating film with a first conductive material film to form a source line plug; Forming a second interlayer insulating film on the entire structure, and then patterning the first and second interlayer insulating films to open the junction contact hole of the high voltage device transistor in the first region, and the junction of the second region. Forming a drain contact hole for opening a drain terminal of the flash memory cell; Filling the junction contact hole and the drain contact hole with a second conductive material layer doped with a predetermined impurity to form a junction contact plug and a drain contact plug; And And performing a heat treatment process for diffusion of impurities in the junction contact plug and the drain contact plug. The method of claim 1, The second conductive film is a method of manufacturing a NAND flash memory device using a polycrystalline silicon film doped with Phosphorous (P) or Arsenic (As) 1.0E19 to 5.0E20. The method of claim 1, The heat treatment step is a manufacturing method of the NAND flash memory device to be carried out in a temperature range of 700 to 1000 ℃ using a furnace. The method of claim 1, wherein the step of forming the junction contact plug and the drain contact plug and performing the heat treatment process, And sequentially forming an anti-etching film and a third interlayer insulating film on the entire structure.