JPS60234326A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60234326A JPS60234326A JP59090415A JP9041584A JPS60234326A JP S60234326 A JPS60234326 A JP S60234326A JP 59090415 A JP59090415 A JP 59090415A JP 9041584 A JP9041584 A JP 9041584A JP S60234326 A JPS60234326 A JP S60234326A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- insulating film
- pattern
- etching
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims 1
- 238000001020 plasma etching Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 23
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 3
- 238000012856 packing Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- 102000004855 Multi drug resistance-associated proteins Human genes 0.000 description 2
- 108090001099 Multi drug resistance-associated proteins Proteins 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の技術分野）
本発明は半導体装置の製造方法に関し、特に素子間分離
に改良を加えた半導体装置の製造方法に係わる。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device with improved isolation between elements.
周知の如く、素子間分離技術としては、一般に選択酸化
法が知られている。しかし、この方法では、形成される
フィールド酸化膜の端部にいわゆるバーズビークが発生
するため、ホトマスク上の素子領域のパターン寸法と実
際に形成される素子領域の寸法との間の寸法変換差が大
きく、素子の高集積化の障害となっている。このような
ことから、最近、今後の素子の高集積化に対して寸法変
換差の小さい素子分離技術が要望されている。従来、半
導体装置は、例えば第１図（ａ）〜（Ｃ）に示すように
製造されている。As is well known, selective oxidation is generally known as an element isolation technique. However, with this method, so-called bird's beaks occur at the edges of the field oxide film that is formed, resulting in a large dimensional conversion difference between the pattern dimensions of the device region on the photomask and the dimensions of the device region actually formed. , which is an obstacle to higher integration of devices. For these reasons, there has recently been a demand for element isolation technology with small dimensional conversion differences for future higher integration of elements. Conventionally, semiconductor devices have been manufactured, for example, as shown in FIGS. 1(a) to 1(C).
まず、例えばＰ型のシリコン基板１上に厚さ約８０００
人の熱酸化膜２を形成した（第１図（ａ）図示）。つづ
いて、この熱酸化膜２上に素子領域形成予定部に対応す
る部分が開口したレジストパターン３を形成した。次い
で、このレジストパターン３をマスクとして前記熱酸化
膜２を反応性エツチング（ＲＩＥ）により選択的にエツ
チング除去して酸化膜パターン（素子分離領域）２′を
形成し、素子領域４ａ、４ｂを夫々形成したく第１図（
ｂ）図示）。以下、常法により、素子領域４ａ、４ｂ上
にゲートＮ極５ａ、５ｂをゲート絶縁膜６ａ、６ｂを介
して形成し、更に前記ゲート電極５ａ、５ｂをマスクと
して基板１にｎ型不純物を導入してＮ＋型のソース、ド
レイン領域７ａ、７ｂ、８ａ、８ｂを形成し、しかる後
全面に層間絶縁膜９を形成し、ひきつづきこれに適宜コ
ンタクトホール１０・・・、取出し配線１１・・・を形
成して半導体装置を製造する（第１図（Ｃ）図示）。First, for example, on a P-type silicon substrate 1, a film with a thickness of about 8000
A thermal oxide film 2 was formed (as shown in FIG. 1(a)). Subsequently, a resist pattern 3 was formed on the thermal oxide film 2, with openings corresponding to the portions where the element regions were to be formed. Next, using this resist pattern 3 as a mask, the thermal oxide film 2 is selectively etched away by reactive etching (RIE) to form an oxide film pattern (element isolation region) 2', and the element regions 4a and 4b are etched, respectively. Figure 1 (
b) As shown). Thereafter, gate N electrodes 5a and 5b are formed on the element regions 4a and 4b via gate insulating films 6a and 6b by a conventional method, and n-type impurities are introduced into the substrate 1 using the gate electrodes 5a and 5b as masks. Then, N+ type source and drain regions 7a, 7b, 8a, 8b are formed, and then an interlayer insulating film 9 is formed on the entire surface. A semiconductor device is manufactured by forming a semiconductor device (as shown in FIG. 1(C)).
こうした方法（以下、ＭＯＡＴ法と呼ぶ）によれば、前
述した選択酸化法に比べ、バーズビークの発生をなくし
、素子の高集積化を達成できる。According to this method (hereinafter referred to as MOAT method), compared to the aforementioned selective oxidation method, the occurrence of bird's beaks can be eliminated and higher integration of elements can be achieved.
しかしながら、ＭＯＡＴ法では、第１図（ｂ）の工程で
、熱酸化膜２をＲＩＥによりエツチング除去するため、
エツチング後の加工形状が切立った段差構造となり、第
２図に示す如くコンタクトホール１０付近の層間絶縁膜
９上の取出し配線１１に段切れ１２が生じるという問題
があった。However, in the MOAT method, in the step shown in FIG. 1(b), the thermal oxide film 2 is etched away by RIE.
There was a problem in that the processed shape after etching became a steep step structure, and as shown in FIG. 2, a step break 12 was generated in the lead-out wiring 11 on the interlayer insulating film 9 near the contact hole 10.
本発明は、上記事情に鑑みてなされたもので、取出し配
線の段切れを回避するとともに、変換差を小さくして素
子の高集積化をなしえる半導体装置の製造方法を提供す
ることを目的とするものである。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can avoid step breaks in the lead-out wiring, reduce conversion differences, and achieve high integration of elements. It is something to do.
本発明は、半導体基板上に直接あるいは第１の絶縁膜を
介して第２の絶縁膜を堆積した後、この第２の絶縁膜を
パターニングして素子領域形成予定部に対応する部分が
開口した絶縁膜パターンを形成し、更に全面に第３の絶
縁膜を形成し、しかる後この第３の絶縁膜を反応性エツ
チングによりエッチバックして該第３の絶縁膜を前記絶
縁膜パターンの側壁にのみ残存させ、ひきつづき弗酸系
のエツチング液で残存する絶縁膜及び絶縁膜パターンを
エツチング除去して素子領域及び素子分離領域を形成す
ることによって、取出し配線の段切れの防止及び素子の
高集積化を図ったものである。In the present invention, a second insulating film is deposited directly or via a first insulating film on a semiconductor substrate, and then this second insulating film is patterned to form an opening in a portion corresponding to a portion where an element region is to be formed. An insulating film pattern is formed, a third insulating film is further formed on the entire surface, and then this third insulating film is etched back by reactive etching to form the third insulating film on the sidewalls of the insulating film pattern. By etching away the remaining insulating film and insulating film pattern using a hydrofluoric acid-based etching solution to form an element region and an element isolation region, it is possible to prevent disconnection of the lead wiring and increase the integration of the element. The aim is to
〔発明の実施例）
以下、本発明の〜実施例を第３図（ａ）〜（丁）を参照
して説明する。[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to FIGS.
（１）、まず、Ｐ型のシリコン基板２１上に第１の絶縁
膜としての厚さ約２０００人の熱酸化膜２２を形成した
後、この上に第２の絶縁膜としての厚さ約４０００人の
第１のＣＶＤシリコン酸化膜２３を体積した（第３図（
ａ）図示）。つづいて、素子領域形成予定部に対応する
部分が開口した小トレジストパターン２４により、前記
シリコン酸化膜２３をＲＩＥにより、エツチング除去し
、酸化膜パターン２３′を形成したく第３図＜ｂ）図示
）。次いで、ホトレジストパターン２４を除去した後、
全面に第３の絶縁膜としての厚さ２０００人の第２のＣ
ＶＤシリコン酸化膜２５を体積したく第３図（Ｃ）図示
）。しかる後、ＲｒＥにより、このシリコン酸化膜２５
をエッチバックし、該シリコン酸化膜２５′を前記酸化
膜パターン２３′の側壁に幅（、Ｌ ”ＡＩ ）が２０
００人程度８なるように残存さゼた（第３図（Ｃ）図示
）。更に、熱処理を施し、前記酸化膜パターン２３′及
び残存するシリコン醇化膜２５′の分子密度を密にした
（第３図（（ｊ）図示）。この熱処理により、後記弗化
アンモニア液によるエツチングの際のｊｆｆ化膜パター
ン、シリコン酸化膜の夫々のエツチング速度と熱酸化膜
のそれを略同−にすることができる。(1) First, a thermal oxide film 22 with a thickness of about 2000 mm as a first insulating film is formed on a P-type silicon substrate 21, and then a thermal oxide film 22 with a thickness of about 4000 mm as a second insulating film is formed on this. A first CVD silicon oxide film 23 was deposited (see Fig. 3).
a) As shown). Next, the silicon oxide film 23 is etched away by RIE using a small resist pattern 24 which has an opening in a portion corresponding to a portion where an element region is to be formed, to form an oxide film pattern 23' (FIG. 3<b). (Illustrated). Next, after removing the photoresist pattern 24,
A second C layer with a thickness of 2000 as a third insulating film is applied to the entire surface.
The VD silicon oxide film 25 is deposited (as shown in FIG. 3C). After that, this silicon oxide film 25 is removed by RrE.
is etched back, and the silicon oxide film 25' is formed on the side wall of the oxide film pattern 23' with a width (L"AI) of 20
About 8,000 people remained (as shown in Figure 3 (C)). Further, a heat treatment was performed to increase the molecular density of the oxide film pattern 23' and the remaining silicon fused film 25' (as shown in FIG. 3 (J)).This heat treatment made it possible to reduce the etching process using the ammonium fluoride solution described later. The etching rate of the actual JFF film pattern and the silicon oxide film can be made approximately the same as that of the thermal oxide film.
（２）９次に、前記酸化膜パターン２３′ 、残存する
シリコン酸化膜２５′及び熱酸化膜２２を弗化アンモ、
−ア液で基板表面が露出するまでエツチングした。これ
により、酸化膜パターン２３′、シリコン酸化１！！Ｉ
２５’及び熱酸化膜２２を等方向にエツチングでき、第
３図（ｅ）に示すように醇化膜パターン２３′と残存す
る熱酸化１！ ２２からなる膜厚４０００人の素子分離
領域２６、この領域２６に囲まれた素子領域２７ａ、２
７ｂが夫々形成された。なお、前記エツチングにより、
第３図（ｄ）の幅（ＬＷ）が２０００人相当分のシリコ
ン酸化膜２５′がエツチングされた。つづいて、常法に
より、前記素子領域２７ａ、２７ｂ上にゲート電極２８
ａ、２８ｂをゲート絶縁膜２９ａ、２９ｂを介して形成
した後、ゲート電極２８ａ、２８ ｂをマスクとして基
板２１の素子領域２７に例えばヒ素を導入してＮ１型の
ソース、ドレイン領１ｔ３０ａ、３０ｂ、３１ａ、３１
ｂを夫々形成し、更に全面に層間絶縁膜３２を形成し、
しかる後、前記ソース、ドレイン領域３０ａ、３０ｂ、
３１ａ、３１ｂに夫々対応する層間絶縁膜３２にコンタ
クトホール３３・・・を開口し、これらコンタクトホー
ル３３・・・に取出し配置３４・・・を形成して半導体
装置を製造した（第３図（ｆ）図示）。(2) 9 Next, the oxide film pattern 23', the remaining silicon oxide film 25' and the thermal oxide film 22 are treated with ammonium fluoride.
- Etching was performed using a solution until the surface of the substrate was exposed. As a result, the oxide film pattern 23', silicon oxide 1! ! I
25' and the thermal oxide film 22 can be etched in the same direction, and as shown in FIG. 3(e), the fused film pattern 23' and the remaining thermal oxide film 1! An element isolation region 26 with a film thickness of 4000 consisting of
7b were formed respectively. Furthermore, due to the etching,
A silicon oxide film 25' whose width (LW) in FIG. 3(d) corresponds to 2000 people was etched. Next, gate electrodes 28 are formed on the element regions 27a and 27b by a conventional method.
After forming the gate electrodes 28a, 28b via the gate insulating films 29a, 29b, for example, arsenic is introduced into the element region 27 of the substrate 21 using the gate electrodes 28a, 28b as a mask to form N1 type source and drain regions 1t30a, 30b, 31a, 31
b, and further form an interlayer insulating film 32 on the entire surface,
After that, the source and drain regions 30a, 30b,
Contact holes 33 were opened in the interlayer insulating film 32 corresponding to the contact holes 31a and 31b, and lead-out arrangements 34 were formed in these contact holes 33 to manufacture a semiconductor device (see FIG. 3). f) As shown).
しかして、本発明によれば、シリコン基板２１上に熱酸
化１１！２２を介して酸化膜パターン２３′を形成する
とともに、このパターン２３′の側壁にＲＩＥを用いて
シリコン酸化膜２５′をエッチバックにより残存させた
後、熱処理を施すため、前記酸化膜パターン２３′及び
残存するシリコン酸化膜２５′の分子密度を密にでき、
弗化アンモニア液によるエツチングの際、酸化膜パター
ン２３′、シリコン酸化Ｉｔ！ ２５ ’ の夫々のエ
ツチング速度を熱酸化膜２２のそれと略同−にできる。According to the present invention, an oxide film pattern 23' is formed on the silicon substrate 21 through thermal oxidation 11!22, and a silicon oxide film 25' is etched on the sidewall of this pattern 23' using RIE. Since the oxide film pattern 23' and the remaining silicon oxide film 25' are left behind by backing and then subjected to heat treatment, the molecular density of the oxide film pattern 23' and the remaining silicon oxide film 25' can be made dense.
During etching with ammonia fluoride solution, the oxide film pattern 23', silicon oxide It! The etching rate of each of the layers 25' can be made approximately the same as that of the thermal oxide film 22.
従って、第３図（ｅ）に示す如く、酸化膜パターン２３
′の側壁の幅（ＬＷ）が２０００人相当分のシリコン酸
化膜２５′がエツチングされた形状の酸化膜パターン２
３′と熱酸化膜２２からなる素子分離領域２６を形成す
ることができ、素子の高集積化を向上できる。Therefore, as shown in FIG. 3(e), the oxide film pattern 23
Oxide film pattern 2 in which a silicon oxide film 25' whose side wall width (LW) is equivalent to 2000 people is etched.
3' and the thermal oxide film 22 can be formed, and the high degree of integration of the elements can be improved.
また、前述したように第３図（ｄ）の熱処理工程で、酸
化膜パターン２３′及びシリコン酸化膜２５′のエツチ
ング速度を熱酸化膜２２のそれと略同−にできるため、
熱酸化膜２２、酸化膜パターン２３′からなる素子分離
領域２６の側壁を緩やかに傾斜した形状にできる。従っ
て、第３図（ｆ）の工程て、層間絶縁膜３２のコンタク
トホール３３・・・に形成する取出し配線３４・・・の
段切れを回避できる。Furthermore, as described above, in the heat treatment step of FIG. 3(d), the etching rate of the oxide film pattern 23' and the silicon oxide film 25' can be made approximately the same as that of the thermal oxide film 22.
The sidewalls of the element isolation region 26 made up of the thermal oxide film 22 and the oxide film pattern 23' can be formed into a gently sloped shape. Therefore, in the process shown in FIG. 3(f), it is possible to avoid disconnection of the lead-out wirings 34 formed in the contact holes 33 of the interlayer insulating film 32.
なお、上記実施例では、酸化膜パターン２３′の側壁に
シリコン酸化１１１！ ２５ ’ を残存させた後、熱
処理を行なったが、これに限らず、第３図（Ｃ）で全面
にシリコン酸化膜２５を形成した後、熱処理を行なって
も、上記実施例と同様な効果が得られる。In the above embodiment, silicon oxide 111! is formed on the side wall of the oxide film pattern 23'. Although the heat treatment was performed after leaving the silicon oxide film 25', the same effect as in the above embodiment can be obtained even if the heat treatment is performed after forming the silicon oxide film 25 on the entire surface as shown in FIG. 3(C). is obtained.
上記実施例では、熱酸化膜２２と、酸化膜パターン２３
’の側壁に残存させたシリコン酸化膜２５′の夫々の膜
厚を同一したが、これに限定されるものではない。In the above embodiment, the thermal oxide film 22 and the oxide film pattern 23 are
Although the thickness of each silicon oxide film 25' left on the side wall of ' is the same, the thickness is not limited to this.
上記実施例では、素子弁Ｉｎ域の膜厚を４０００人とし
たが、これに限定されるものではない。In the above embodiment, the film thickness of the element valve In region was set to 4000, but it is not limited to this.
上記実施例では、第３図（ｅ）で弗酸系のエツチング液
による処理をおこなったか、酸化膜パターン２３′の側
壁に残存するシリコン酸化膜の幅（ＬＷ）程度許容でき
る構造の半導体装置の製造においては、前記エツチング
処理を工程を省略しても、酸化膜パターン２３′の側壁
のシリコン酸化膜２５′の存在により取出し配線の段切
れを回避できる。In the above embodiment, the process using a hydrofluoric acid-based etching solution as shown in FIG. In manufacturing, even if the etching process is omitted, the presence of the silicon oxide film 25' on the side wall of the oxide film pattern 23' makes it possible to avoid disconnection of the lead-out wiring.
上記実施例では、第１の絶縁膜として熱酸化膜を、第２
、第３の絶縁膜としてＣＶＤシリコン酸化膜を夫々用い
たが、これに限定されるものではない。In the above embodiment, a thermal oxide film is used as the first insulating film, and a thermal oxide film is used as the second insulating film.
, a CVD silicon oxide film is used as the third insulating film, but the present invention is not limited to this.
以上詳述した如く本発明によれば、取出し配線の段切れ
を回避するとともに、素子の高集積化をなしえる半導体
装置の製造方法を提供できるものである。As described in detail above, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device that avoids disconnection of the lead wiring and allows high integration of elements.
第１図（ａ）〜（Ｃ）は従来の半導体装置の製造方法を
工程順に示す断面図、第２図は従来の半導体装置の取出
し配線の段切れを説明するための断面図、第３図（ａ）
〜（ｆ）は本発明の一実施例に係る半導体装置の製造方
法を工程順に示すための断面図である。
２１・・・Ｐ型のシリコン基板、２２・・・熱酸化膜（
第１の絶縁膜）、２３．２５．２５′・・・シリコン酸
化膜、２３′・・・ｎ！ｉ化膜パターン、２４・・・ホ
トレジストパターン、２Ｇ・・・素子分離領域、２７ａ
２７ｂ・・・素子領域、２８ａ、２８ｂ・・・ゲート電
極２９ａ、２９ ｂ−・・グー１〜絶縁膜、３０ａ、３
１ａ・・・Ｎ＋型のソース領域、３０ａ、３１ｂ・・・
ドレイン領域、３２・・・層間絶縁膜、３３・・・コン
タクトホール、３４・・・取出し配線。
出願人代理人 弁理士 鈴江武彦
第１図
＾ ＾ ＾
Ｑ ”０ のFIGS. 1(a) to (C) are cross-sectional views showing a conventional semiconductor device manufacturing method in the order of steps; FIG. 2 is a cross-sectional view illustrating the break in the lead wiring of a conventional semiconductor device; FIG. (a)
-(f) are cross-sectional views for sequentially showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 21...P-type silicon substrate, 22...thermal oxide film (
first insulating film), 23.25.25'...silicon oxide film, 23'...n! i-oxide film pattern, 24... photoresist pattern, 2G... element isolation region, 27a
27b...Element region, 28a, 28b...Gate electrode 29a, 29b-...Goo 1~Insulating film, 30a, 3
1a...N+ type source region, 30a, 31b...
Drain region, 32... interlayer insulating film, 33... contact hole, 34... lead-out wiring. Applicant's agent Patent attorney Takehiko Suzue Figure 1 ^ ^ ^ Q "0"
Claims (1)
して第２の絶縁膜を形成する工程と、この第２の絶縁膜
をパターニングして素子領域形成予定部に対応する部分
が開口した絶縁膜パターンを形成する工程と、全面に第
３の絶縁膜を形成する工程と、この第３の絶縁膜を反応
性イオンエツチングによりエッチバックして該第３の絶
縁膜を前記絶縁膜パターンの側壁にのみ残存させる工程
と、弗酸系のエツチング液で残存する絶縁膜及び絶縁膜
パターンをエツチング除去して素子領域と素子分離領域
を形成する工程とを具備することを特徴とする半導体装
置の製造方法。 （２１，弗酸系のエツチング液で残存する絶縁膜及び絶
縁膜パターンをエツチング除去する前に、熱処理を施す
ことを特徴とする特許請求の範囲第１項記載の半導体装
置の製造方法。 （３）、第１の絶縁膜の膜厚と、絶縁膜パターンの側壁
に残存させた第３の絶縁膜の幅を夫々周一にしたことを
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。[Claims] (1) A step of forming a second insulating film directly or via the first insulating film on the semiconductor substrate, and patterning the second insulating film to form a portion where an element region is to be formed. a step of forming an insulating film pattern with openings corresponding to the pattern, a step of forming a third insulating film on the entire surface, and a step of etching back the third insulating film by reactive ion etching to form the third insulating film. A step of leaving the film only on the side wall of the insulating film pattern, and a step of etching away the remaining insulating film and the insulating film pattern using a hydrofluoric acid-based etching solution to form an element region and an element isolation region. A method for manufacturing a semiconductor device, characterized by: (21. The method for manufacturing a semiconductor device according to claim 1, characterized in that heat treatment is performed before etching away the remaining insulating film and insulating film pattern with a hydrofluoric acid-based etching solution. (3 ), the semiconductor device according to claim 1, characterized in that the thickness of the first insulating film and the width of the third insulating film left on the side wall of the insulating film pattern are made equal to each other. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59090415A JPS60234326A (en) | 1984-05-07 | 1984-05-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59090415A JPS60234326A (en) | 1984-05-07 | 1984-05-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60234326A true JPS60234326A (en) | 1985-11-21 |
Family
ID=13997959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59090415A Pending JPS60234326A (en) | 1984-05-07 | 1984-05-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60234326A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02291166A (en) * | 1989-05-01 | 1990-11-30 | Takehide Shirato | Semiconductor device |
| US5023197A (en) * | 1989-08-16 | 1991-06-11 | French State Represented By The Minister Of Post, Telecommunications And Space | Manufacturing process of mesa SOI MOS transistor |
-
1984
- 1984-05-07 JP JP59090415A patent/JPS60234326A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02291166A (en) * | 1989-05-01 | 1990-11-30 | Takehide Shirato | Semiconductor device |
| JP2608470B2 (en) * | 1989-05-01 | 1997-05-07 | 猛英 白土 | Semiconductor device and manufacturing method thereof |
| US5023197A (en) * | 1989-08-16 | 1991-06-11 | French State Represented By The Minister Of Post, Telecommunications And Space | Manufacturing process of mesa SOI MOS transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04317358A (en) | Manufacture of semiconductor device | |
| JPH02222160A (en) | Manufacture of semiconductor device | |
| JPS60234326A (en) | Manufacture of semiconductor device | |
| JP2001176983A (en) | Semiconductor device and producing method therefor | |
| JP2971085B2 (en) | Method for manufacturing semiconductor device | |
| JPH0426162A (en) | Floating gate semiconductor memory and manufacture thereof | |
| JPH09321233A (en) | Manufacturing semiconductor device | |
| JP2741964B2 (en) | Method for manufacturing semiconductor device | |
| JPS59112656A (en) | Semiconductor device and manufacture thereof | |
| JPH01235269A (en) | Semiconductor device | |
| JPH0210729A (en) | Formation of field insulating film | |
| JPS62219960A (en) | Manufacture of thin film mos structure semiconductor device | |
| JPS5974623A (en) | Manufacture of semiconductor integrated circuit | |
| JPS6345865A (en) | Floating gate type mos semiconductor device | |
| JPH01162358A (en) | Formation of laminar-structure mis semiconductor device | |
| JPH04159725A (en) | Manufacture of semiconductor device | |
| JPH0429318A (en) | Manufacture of semiconductor device | |
| JPH08236608A (en) | Fabrication of semiconductor device | |
| JPS61107747A (en) | Manufacture of semiconductor device | |
| JPH05198571A (en) | Semiconductor device and its manufacture | |
| JPH0370144A (en) | Manufacture of semiconductor device | |
| JPS63252483A (en) | Manufacture of semiconductor device | |
| JPH0458538A (en) | Manufacture of semiconductor device | |
| JPS5944842A (en) | Manufacture of semiconductor device | |
| JPH04107950A (en) | Semiconductor device |