JPH04159725A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04159725A
JPH04159725A JP28486090A JP28486090A JPH04159725A JP H04159725 A JPH04159725 A JP H04159725A JP 28486090 A JP28486090 A JP 28486090A JP 28486090 A JP28486090 A JP 28486090A JP H04159725 A JPH04159725 A JP H04159725A
Authority
JP
Japan
Prior art keywords
film
gate electrode
silicon nitride
nitride film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28486090A
Other languages
Japanese (ja)
Inventor
Yoshitaka Narita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP28486090A priority Critical patent/JPH04159725A/en
Publication of JPH04159725A publication Critical patent/JPH04159725A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize a margin-free process by covering a gate electrode with an insulating film, and depositing silicon oxide as an inner insulating film.
CONSTITUTION: A first silicon nitride film 5 and a gate polysilicon film 10 are patterned to form a mask, through which arsenic ions are implanted to form an n-type diffused layer 6. After a gate oxide 3 is removed with the silicon nitride film 5 and a gate electrode 4 used as mask, a second silicon nitride film 7 is deposited on a substrate 1. Then, the film 7 is removed in such a manner that it stays the side walls of the gate electrode 4. A silicon oxide is deposited as an inner insulating layer 8, and a window for a contact hole 12 is opened in it after a photoresist film 11 is applied. The insulating film 8 is etched with buffered hydrofluoric acid to form a contact hole, before a wiring layer 9 is formed by a conventional process. This realizes a margin-free process.
COPYRIGHT: (C)1992,JPO&Japio
JP28486090A 1990-10-23 1990-10-23 Manufacture of semiconductor device Pending JPH04159725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28486090A JPH04159725A (en) 1990-10-23 1990-10-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28486090A JPH04159725A (en) 1990-10-23 1990-10-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04159725A true JPH04159725A (en) 1992-06-02

Family

ID=17683966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28486090A Pending JPH04159725A (en) 1990-10-23 1990-10-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04159725A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422819B1 (en) * 1997-06-30 2004-05-24 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US6962853B2 (en) 2000-01-20 2005-11-08 Matsushita Electronic Industrial Co., Ltd. Semiconductor device and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422819B1 (en) * 1997-06-30 2004-05-24 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US6962853B2 (en) 2000-01-20 2005-11-08 Matsushita Electronic Industrial Co., Ltd. Semiconductor device and method for fabricating the same

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