JPH04159725A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a margin-free process by covering a gate electrode with an insulating film, and depositing silicon oxide as an inner insulating film. CONSTITUTION:A first silicon nitride film 5 and a gate polysilicon film 10 are patterned to form a mask, through which arsenic ions are implanted to form an n-type diffused layer 6. After a gate oxide 3 is removed with the silicon nitride film 5 and a gate electrode 4 used as mask, a second silicon nitride film 7 is deposited on a substrate 1. Then, the film 7 is removed in such a manner that it stays the side walls of the gate electrode 4. A silicon oxide is deposited as an inner insulating layer 8, and a window for a contact hole 12 is opened in it after a photoresist film 11 is applied. The insulating film 8 is etched with buffered hydrofluoric acid to form a contact hole, before a wiring layer 9 is formed by a conventional process. This realizes a margin-free process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an MO3 semiconductor device having an improved self-line contact.

[Conventional technology]

FIGS. 2(a) to 2(f) are cross-sectional views of a semiconductor chip shown in order of steps to explain a conventional example.

First, as shown in FIG. 2(a), a field oxide film 2 and a gate oxide film 3 are formed on a P-type semiconductor substrate 1 by a known semiconductor device manufacturing method, and then a gate electrode 4, which will become a gate electrode 4, is formed on a P-type semiconductor substrate 1. A polysilicon film 10 is formed with a thickness of 300 nm.
silicon oxide film 13 with a thickness of 1100 nm, each CV
Grow with method D.

Next, as shown in FIG. 2(b), the first silicon oxide film 13 and the gate polysilicon film 10 are sequentially coated by RIE using an ordinary photoresist or lithography technique.
Using this as a mask, As (arsenic) is introduced by ion implantation to form an N-type diffusion layer 6.

Subsequently, as shown in FIG. 2(c), the gate oxide film 3 is removed using the first silicon oxide film 13 and the gate electrode 4 as masks (this removal step is not always necessary).
, a second silicon oxide film is formed on the substrate surface by CVD method]4
Then, as shown in FIG. 2(d), a second layer is deposited on the side wall of the gate electrode by an etch-back method, as shown in FIG. 2(d).
The silicon oxide film 14 is left.

Next, as shown in FIG. 2(e), a silicon oxide film is deposited as the glabella insulating film 8 to a thickness of ], 5
A photoresist film 11 is deposited to a thickness of 0 nm, and a portion that will become a contact hole 12 is opened using a normal exposure technique.

Thereafter, as shown in FIG. 2 (f>), the interlayer insulating film 8 is etched by RIE or wet etching using buffered hydrofluoric acid to form a contact hole. formed by a forming process;
Get a selfie line contact.

[Problems to be Solved by the Invention] In the conventional semiconductor device manufacturing method described above, the insulating film covering the gate electrode and the glabellar insulating film are both silicon oxide films, so it is difficult to open a self-line contact. When forming holes, it is not possible to selectively etch only the glabella insulating film, and if over-etching is performed, the insulating film on the gate electrode will disappear, resulting in a small process margin.

In addition, in order to solve the above-mentioned drawbacks, there is a method in which the silicon oxide film is deposited sufficiently thickly (usually 200 to 300 nm) on the gate electrode, taking into account over-etching in the etching process for forming the contact hole in advance. However, this method has the disadvantage of significantly impairing the flatness of the device.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes depositing a conductive film and a first silicon nitride film on a predetermined region of a semiconductor substrate via a gate insulating film, and then shaping the surface of the semiconductor substrate with the first silicon nitride film. a step of forming a covered gate electrode; a step of performing ion implantation using the gate electrode as a mask to form a source region and a drain region;
a step of depositing a silicon nitride film and etching it back to leave it on the side wall of the gate electrode; a step of depositing a glabella insulating film made of silicon oxide; and a step of selectively etching the interlayer insulating film to form the source region or The method also includes a step of forming a contact hole in the train region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1(a), a field oxide film 2 and a gate oxide film 3 are formed on a P-type semiconductor substrate 1 by a known semiconductor device manufacturing method. The polysilicon film 10 is grown to a thickness of 300 nm, and the first silicon film 5 is grown to a thickness of 1100 nm by CVD.

Next, as shown in FIG. 1(b), the first silicon nitride film 5 and gate polysilicon film 10 are sequentially patterned by RIE using an ordinary photoresist or lithography technique. As a mask, As (arsenic)
is introduced by ion implantation to form an N-type diffusion layer 6.

Subsequently, as shown in FIG. 1(c), the gate oxide film 3 is removed using the first silicon nitride film 5 and the gate electrode 4 as masks (this removal step is not always necessary).
A second silicon nitride film 7 is deposited to a thickness of 1100 nm on the substrate surface by CVD, and then, as shown in FIG. Membrane 7 is left behind.

Next, as shown in FIG. 1(e), a silicon oxide film is deposited to a thickness of 150 mm as the glabellar insulating film 8 by the usual CVD method.
A photoresist film 11 is deposited, and a portion that will become a contact hole 12 is opened using a normal exposure technique. Thereafter, as shown in FIG. 1(f), the glabellar insulating film 8 is etched by wet etching using buffered hydrofluoric acid to form a contact hole. Next, wiring layer 9
is formed by a normal wiring formation process.

Here, the silicon oxide film that is the interlayer insulating film 8 is etched with buffered hydrofluoric acid, but any etching means or method can be used as long as the etching selectivity between the silicon oxide film and the silicon nitride film can be maintained. It is obvious that it can be anything. In this way, field oxide 11 is formed on the P-type semiconductor substrate 1'2 made of Si.
2. It has a gate electrode 4 formed through a gate oxide film 3, the upper part of the gate electrode 4 is covered with a first silicon nitride film 5, and the sidewalls are covered with a second silicon nitride film 7, It is composed of a wiring layer 9 connected to an N-type diffusion layer 6 in a source region or a drain region through a contact hole opened in a glabellar insulating film 8 made of silicon oxide and a contact hole opened in the goo 1 to electrode 4 and self-line. A MO8 semiconductor device is manufactured.

〔Effect of the invention〕

As explained above, according to the present invention, the insulating film covering the gate electrode is formed of a silicon nitride film, and the interlayer insulating film is formed of a silicon oxide film, so that when a self-line contact is formed by hole etching, By using the etching selectivity of silicon nitride film and silicon oxide film,
Since etching can be stopped by the silicon nitride film, a margin-free process can be constructed.

Furthermore, unlike the conventional example, there is no need to deposit a thick insulating film on the gate electrode in advance in consideration of the process margin, so it is effective for flattening the device.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are longitudinal cross-sectional views showing the steps in order to explain an embodiment of the present invention, and FIGS. 2(a) to (f> show the steps in order to explain the conventional example. 1 is a vertical cross-sectional view showing: 1... P-type semiconductor substrate, 2... Field oxide film,
3... Gate oxide film, 4... Gate electrode, 5...
First silicon nitride film, 6... N-type diffusion layer, 7...
Second silicon nitride film, 8... Interlayer insulating film, 9...
Wiring layer, 10...GaI-polysilicon film, 11...
・Photoresist film, 12... Contact hole, 13.
...first silicon oxide film, 14...second silicon oxide film.

Claims (1)

[Claims] forming a gate electrode whose surface is covered with the first silicon nitride film by depositing a conductive film and a first silicon nitride film on a predetermined region of a semiconductor substrate via a gate insulating film, and then shaping the film; , a step of performing ion implantation using the gate electrode as a mask to form a source region and a drain region; a step of depositing a second silicon nitride film and then etching it back to leave it on the side wall of the gate electrode; a step of depositing an interlayer insulating film;
A method for manufacturing a semiconductor device, comprising the step of selectively etching the interlayer insulating film to form a contact hole in the source region or drain region.