JPS63260163A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate the need for alignment accuracy to the size of a cell contact and a trench by forming the cell contact to the upper section of the trench in a self-alignment manner. CONSTITUTION:An element isolation region is shaped, three layer films of oxide films 22, 23/nitride film 25/oxide film 26 are applied, the three layer films are patterned, and a trench in approximately 5000Angstrom depth is formed to a semiconductor substrate through anisotropic etching. A second nitride film 28 is grown, and a side wall 29 afterward functioning as a cell contact region is formed onto the side faces of the three layer films and the trench through anisotropic etching. The trench 30 is further out up to approximately 4mum depth through anisotropic etching, the oxide film 26 as the upper layer of the three layer films is removed and the inside of the trench is oxidized selectively, the side wall 29 is gotten rid of to expose the surface of the semiconductor substrate as a cell contact 32 to the upper section of the trench, and a first conductive film 33 and a diffusion layer 34 in an adjacent transistor are connected in a self-alignment manner. Accordingly, alignment accuracy to the size of the cell contact and the trench can be unnecessitated.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention involves forming a groove in a semiconductor substrate, and depositing a first conductive film, a dielectric film, and a second conductive film in the groove. , relates to a method of manufacturing a semiconductor memory device in which charge is accumulated in a first conductive film, and in particular, MO3 adjacent to the first conductive film.
The present invention relates to a method for forming a contact connected to a diffusion layer of a type transistor.

(Prior Art) Conventionally, as technologies in this field, for example, Japanese Patent Application Laid-Open No. 59-161860, Japanese Patent Application Laid-Open No. 59-222939,
Some of these are described in JP-A No. 60-65559 and the like.

Hereinafter, its structure will be explained in detail with reference to the drawings. FIG. 2 is a sectional view of the manufacturing process of such a conventional semiconductor memory device.

First, as shown in FIG. 2(a), a P-type St substrate l
Element number # by LOCO5 method is shown above! forming I region 2;
As ions are implanted at an acceleration of about 30 KeV to form an N-type diffusion layer 4, and a thermal oxide film 3 of about 500 layers is deposited by low pressure CVD to serve as an etching mask when forming grooves.
Nitride film 5 with a film thickness of 500 to 1000 by the normal pressure CV method
An oxide film 6 having a thickness of 5,000 to 10,000 wafers is sequentially grown using the D method. Note that here, the N-type diffusion N4 is necessary to ensure the connection between the first conductive film and the diffusion layer of the transistor to be formed later.

Next, as shown in FIG. 2(b), photolithography is performed to perform oxide film 6/nitride lI! 5/ S by anisotropic etching of the oxide film 3 and anisotropic etching with chlorine gas
The i-substrate 1 is etched to form a groove 7.

Next, as shown in FIG. 2(e), IIP/llN0. Etching the Si substrate in the groove with the mixed solution, removing the oxide film 6 with the IIF aqueous solution,
Selective oxidation in the groove and removal of nitride 115 using hot phosphoric acid are performed. In this case, the thickness of the oxide film 8 in the groove is 1500 to 30 mm.
Approximately 00 people.

Next, as shown in FIG. 2(d), a contact 9 (hereinafter referred to as a cell contact) for connecting the first conductive film of the capacitor and a diffusion layer of a transistor to be created adjacently later is formed. Opening is performed by photolithography and etching with an IIF aqueous solution.

Next, as shown in FIG. 2(e), a polycrystalline 5ilo film with a film thickness of 1000 to 2000 layers, which will become the first conductive film, is grown by low pressure CVD, and polycrystalline St 5ilo is grown by vapor phase diffusion.
POCl s (4~6 X 10”ell-3)
is diffused and patterned by photolithography and etching.

Here, 11 is a high concentration N-type diffusion layer made of phosphorus which is diffused into the Si substrate through the cell contact 9 when POC1 is diffused into the polycrystalline St.

Next, a film thickness of 120 to 2
Growth of nitride film 12 of 0.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 grown nitride film 12, growth of polycrystalline Si which is the second conductive film 13, growth of 7000 to 1000000000000000000000000000000 polycrystalline oxide film by low pressure CVD method for POCj, diffusion and planarization. A filling material 1''4 is formed by etching back with the crystalline Si as the end point of etching, and as shown in FIG. 2(r), a second conductive film (polycrystalline Si) 13 is formed.
, the nitride film 12 and the oxide P113 are patterned.

After this, as shown in FIG.
, transistor gate oxidation [16, gate electrode 17,
A semiconductor memory device is obtained by forming an N-type diffusion layer 18, an intermediate insulating film 19, and a contact 20 with wiring by ion implantation, and further forming wiring (not shown).

(Problems to be Solved by the Invention) However, in the method for manufacturing the semiconductor memory device described above, since the cell contacts are opened by photolithography and etching, it is necessary to form the cell contact portions on the surface of the Si substrate. As shown in (d), a length corresponding to at least the cell contact dimension (L) and the positional accuracy (alignment accuracy) (ΔL) with respect to the groove is required, which is an obstacle when reducing the element size. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor memory device with a high density by eliminating the above-mentioned obstacles to reduction in element size caused by cell contacts.

(Means for Solving the Problems) In order to solve the above problems, the present invention forms a groove in a semiconductor substrate, and a first conductive film, a dielectric film, and a second conductive film are formed in the groove portion. In a method of manufacturing a semiconductor memory device in which a first conductive film is deposited and charges are accumulated in a first conductive film, a three-layer film of oxide film/nitride film/oxide film is formed as a mask for etching a semiconductor substrate to form a groove. step, after patterning the three-layer film, forming a shallow groove by anisotropic etching, growing a nitride film on the three-layer film and the groove, and forming a nitride film sidewall by anisotropic etching. a step of digging the trench by anisotropic etching using the three-layer film and the nitride film sidewall as a mask to form a deeper trench; and a step of selecting inside the trench using the three-layer film and the nitride film sidewall as a mask. A step of performing oxidation to form an oxide film on the lower part of the trench surface, and after removing the nitride film sidewall, depositing a first conductive film on the upper part of the trench where the nitride film sidewall was present. A step of forming a cell contact on the side surface is provided.

(Function) According to the present invention, as described above, (1) after forming the element isolation region, a three-layer film of oxide film/Ia nitride/oxide film is deposited;
2) After patterning the 3N film, about 5000 (3000 to 600
(3) grow a second nitride film, and form a sidewall that will later become a cell contact region on the 3FJ film and the trench side surfaces by anisotropic etching; 4) Anisotropic etching further deepens the groove by approximately 4
After digging to a depth of μm and removing the CVO oxide film on the top layer of the three-layer film, (5) selectively oxidize the inside of the trench and remove the sidewalls, exposing the semiconductor substrate surface that will become the cell contact above the trench. As a result, the first conductive film and the diffusion layer of the adjacent transistor are connected in a self-aligned manner, which eliminates the need for cell contact dimensions and groove alignment accuracy, which were required in conventional processes, and facilitates manufacturing. Moreover, the dimensions of the semiconductor memory device can be significantly reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor memory device showing an embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type Si substrate 2
After forming an element isolation region on 1 using the LOCO3 method, As
Ions are implanted at an acceleration of about 30 KeV, and N-type diffusion J! Thermal oxide film 23 with a thickness of approximately 500 mm is used as an etching mask when forming grooves, nitride 1925 with a thickness of 500 to 1000 mm is formed by the LPCVD method, and APC.
Oxidation by VD method 1! J26 is grown sequentially, and its three-layer film is patterned for each elemental bone ml fil region.

Next, as shown in FIG. 1(b), a groove 27 approximately 5000 mm deep is formed in the semiconductor substrate by anisotropic etching using chlorine gas.

Next, as shown in FIG. 1(c), the film thickness is about 100 mm.
0 people (500 to 1500 people) (7) Grow the LPCVD nitride film 2B.

Next, anisotropic etching (CIIPs 12SCCM
70Pa1CtFi 48 SCCM O,8H/C
s"), the nitride film 28 is etched except for the inside of the groove, and a side wall 29 of the nitride film is formed as shown in FIG. 1(d).

Next, using the above three-layer WA23.25.26 and the nitride film sidewall 29 as a mask, chlorine-based gas was used again (SiCj 420SCCM 22.5mTor).
r Hz 20SCCMO, 4W/am”), 1st
The semiconductor substrate is etched to form a groove 30 having a depth of approximately 4 μm (3 to 6 μm) as shown in FIG.

Next, as shown in FIG. 1(f), the oxide 1126 is removed.

Next, as shown in FIG. 1(g), the nitrided 111
25 and the nitride film sidewall 29 as a mask, selective oxidation is performed within the trench to form an oxide film 31 with a thickness of 1,000 to 4,000 wafers.

Thereafter, when the nitride film 25 and the nitride film sidewall 29 are removed using hot phosphoric acid, the surface of the semiconductor substrate that will become the cell contact 32 is exposed, and the polycrystalline film 5 formed by the LPCV method is exposed.
Growth of i33, N-type diffusion N34 due to diffusion of POC1
1 (h).
A first conductive film 33 of polycrystalline S+, which will become a capacitor electrode as shown in FIG.

Next, a IIIt00-200 nitride film 35 is formed by the LPCVD method, and a film thickness 1000-200 with a high concentration of phosphorus diffused.
00 Polycrystalline 5i36 (Polycrystalline Si may be grown to diffuse phosphorus (pOc It s))
grow. Spin-on glass (SOG) (After growing thick polycrystalline Si, SiO□, etc.,
Embedded material 3 such as 15,000 people can be used as an etch bank]
After burying the inside of the trench with a polycrystalline silicon nitride film 3136, the polycrystalline 3136 and the nitride film 35 are patterned as shown in FIG. 1(i).

Next, after removing the oxide film 23 with an 11F aqueous solution, the film thickness of the transistor is reduced to 100 to 500 by thermal oxidation.
A gate oxide film 38 is grown. At this time, polycrystalline 5
An oxide film 39 on 136 is also grown at the same time. Also, Lr
'Film thickness 1000mm with high concentration of phosphorus diffused by CVD method
~5000 polycrystalline St is grown and patterned to form gate electrode 40 and polycrystalline Si wiring 1141. Furthermore, As or P impurities are ion-implanted (IXI
OIS ~ 2 ℃ to 1000℃) to activate the impurities.At this time, the gate electrode 40 and the polycrystalline Si
An oxide film 44 is formed on the wiring layer 41.

Then, as shown in FIG. 1(k), APCV[1
An oxide film containing impurities such as n and phosphorus is made by
An oxide film 45 is formed by growing 7,000 layers, and a contact 46 is further patterned, and an A1 alloy 47 is deposited and patterned by sputtering. Thereafter, although not shown, a protective film is applied by 5,000 to 10,000 people to obtain a semiconductor memory device.

Next, another embodiment of the present invention will be described with reference to FIG.

In this example, the same steps as in the first example are performed up to the step shown in FIG. 1(f), and then, as shown in FIG. 3(a), the nitride film on the element isolation region side is removed. The resist 51 is patterned with photorin as much as possible.

This nitride film sidewall 29 on the element isolation region side does not contribute to the formation of cell contacts, and furthermore, since it forms a diffusion layer [see diffusion Ji 34 shown in FIG. 1(h)] directly under the element isolation region, It is better to remove it because it may promote deterioration of element isolation ability.

Next, as shown in FIG. 3(b), the nitride film sidewall 29 on the element bone 1Nlt region side is removed by isotropic dry etching.

Next, as shown in FIG. 3(c), selective oxidation is performed to form an oxide film 52.

Next, as shown in FIG. 3(d), the nitride film 25 and the nitride film sidewall 29 are removed with hot phosphoric acid, and then polycrystalline 5i 54 is grown by L, l' CV D method, poc z , patterning of N-type diffused JI 55 and polycrystalline 5i 54 is performed by diffusion.

After this, steps (1) to (k) in the first embodiment are followed.
), i.e., after growing 1,000 to 2,000 nitride films 56 by the LPC VII method and polycrystalline 5i 57 with high concentration of phosphorus diffused, a filling material such as spin-on glass (SOG) is applied. 5
8, the polycrystalline 5157 and the nitride film 56 are patterned as shown in FIG. 3(e).

Next, after removing the oxide film 23 once with an HP aqueous solution,
Grow a transistor gate oxide [59] with a thickness of 100 to 500 nm by thermal oxidation. At this time, polycrystalline 5i
An oxide film 60 on 57 is also grown at the same time. Also, LPC
Film thickness 1ooo~5 with high concentration of phosphorus diffused by VD method
By growing and patterning 000 polycrystalline St.
A gate electrode 61 and a polycrystalline Si wiring layer 62 are formed, and As or P impurities are ion-implanted (l×101S~
2×1011cII bow) Surukotoni Yosu, Figure 3 (f)
As shown in FIG.
3 and drain region 64 are formed, and further annealing ((
h atmosphere (850°C to 1000°C) to activate impurities. At this time, the gate electrode 61 and the polycrystalline Si wiring 1
Oxide 11965 is formed on 162.

Next, as shown in Fig. 3(g), Si islands containing impurities such as B and P were prepared by the ^pcvo method at 3000~70%
A contact 67 is further patterned, and an A1 alloy 68 is deposited and patterned by the six-puncture method. Thereafter, although not shown, a protective film is applied by 5,000 to 10,000 people to obtain a semiconductor memory device.

In the above embodiment, POC1 is used as the conductive film.

A polycrystalline S1 with diffused N-type impurity (As) was used.

Antimony, etc.), it doesn't matter what you diffuse.
Further, the dielectric material is not limited to a nitride film, and any etching gas for the semiconductor substrate may be used as long as the selectivity to the film serving as a mask is 10 or more.

Furthermore, the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(Effects of the Invention) As described above in detail, according to the present invention, the cell contact is formed in a self-aligned manner on the upper part of the groove, which eliminates the need to change the dimensions of the cell contact, which is necessary in the conventional process. There is no need for alignment precision with respect to the grooves, the manufacturing is easy, and the dimensions of the semiconductor memory device can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor memory device showing one embodiment of the present invention, FIG. 2 is a cross-sectional view of the manufacturing process of a conventional semiconductor memory device, and FIG. 3 is a semiconductor memory device showing another embodiment of the present invention. FIG. 3 is a cross-sectional view of the manufacturing process of the storage device. 21...P-type Si substrate, 22.23.2G, 31.
39.44.45°52, 60.65.66...Oxide film, 24.34.55...N type diffusion layer, 25.2B,
35.5 (i... Nitride film, 27.30... Groove, 2
9... Nitride film side wall, 32... Cell contact, 33°3[i, 54.57... Polycrystalline St,
37.58... Burying material, 38.59... Gate oxide film, 40.61... Gate electrode, 46.67... Contact, 47.68... Affi alloy, 41.62
...Polycrystalline Si wiring layer, 42.63...Source region, 43.64...Drain region, 51...Resist.

Claims (1)

[Claims] A groove is formed in a semiconductor substrate, and a first conductive film,
In a method of manufacturing a semiconductor memory device in which a dielectric film and a second conductive film are deposited and charges are accumulated in the first conductive film, (a) an oxide film/ (b) forming a shallow groove by anisotropic etching after patterning the three-layer film; (c) nitriding the three-layer film and the groove; a step of growing a film and forming a nitride film sidewall by anisotropic etching; (d) masking the three-layer film and the nitride film sidewall;
(e) Performing selective oxidation inside the groove using the three-layer film and nitride film sidewall as a mask to oxidize the lower part of the groove surface. (f) After removing the nitride film sidewall, depositing a first conductive film and forming a cell contact on the upper side surface of the trench where the nitride film sidewall was present. A method of manufacturing a semiconductor memory device, comprising: