JPH01101649A - Element isolation of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration of a semiconductor by selectively forming a groove or a recessed part on the semiconductor substrate, and isolating the elements by forming an oxide film for selective element isolation on the side ends of such groove and recessed part, while using the bottom surface of the groove, etc., as the activated regions. CONSTITUTION:A groove or a recessed part is selectively formed on a semiconductor substrate 1. The semiconductor substrate 1 is oxidized using as the mask first and second nitride films 3, 8 so formed that they cover a region other than the bottom surface 5 of the groove or recessed part, a third oxide film 9 is formed on the lower part of the side ends 6 of the groove or recessed part as well as on the bottom surface 5 of the groove. Then by removing the first and second nitride films 3, 8, the third oxide film 9 is selectively removed, leaving it only on the side ends 6 of the groove. Hence an oxide film for element isolation is obtained on the side ends 6 of the groove, allowing both bottom surface 5 of the groove and the main surface of the semiconductor substrate to be used as activated regions, whereby the degree of integration can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for isolating elements of a semiconductor device, which makes it possible to increase the degree of integration of MO3 type semiconductor devices and the like.

[Prior Art] In the manufacturing process of conventional MO3 type semiconductor devices, the LOCO3 isolation method is widely used for element isolation.

FIGS. 3(a) to 3(f) are cross-sectional views showing a typical LOGO3 separation method in the order of steps.

As shown in FIG. 3(a), on the P-type semiconductor substrate 41,
A thermal oxide film 42 is formed to a thickness of about 100 to 2,000 thick. Next, CVD (chemi) is applied on the thermal oxide film 42.
A nitride film 43 is grown by a cal vapor deposit, ion) method.

Thereafter, a photoresist 44 is selectively formed on the nitride film 43 where the active region is to be formed.

Next, as shown in FIG. 3(b), the photoresist 44
Using as a mask, the CVD nitrided M43 and the thermal oxide film 42 in areas not covered with the photoresist 44 are selectively removed.

Next, as shown in FIG. 3('c), after removing the photoresist 44, the surface of the P-type semiconductor substrate 41 is selectively oxidized using the CVD nitride film 43 as a mask to form a field oxide film 45. Form.

Next, as shown in FIG. 3(d), after removing the CVD nitride film 43, the thermal oxide film 42 is etched and removed until the surface of the P-type semiconductor substrate 41 is exposed in the activated region. .

Next, as shown in FIG. 3(e), a gate insulating film 46 is formed on the surface of the P-type semiconductor substrate 41 in the active region.

Next, as shown in FIG. 3(f), the field oxide film 4
A polycrystalline silicon gate electrode 47 having a predetermined width extending in the direction in which the polycrystalline silicon gate electrodes 5 are arranged is patterned.

Thereafter, an MO3 type semiconductor device is manufactured through normal steps.

[Problems to be Solved by the Invention] However, in the conventional method described above, it is necessary to provide a non-active region of a finite size on the substrate surface as an element isolation region, and this non-active region is A bird's beak is formed around the area defined by the mask No. 44.
The area called k) is formed to be extra wide.

Therefore, the effective channel width of the transistor becomes smaller, and the formation of bird's beak becomes a factor that reduces transistor efficiency.

Furthermore, in order to form an element isolation region on the surface of the substrate, it is necessary to ensure a non-active region on the surface of the substrate, which is a factor that hinders high integration.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a method for isolating elements of a semiconductor device, which can significantly improve the degree of integration without complicating the process.

[Means for Solving the Problems] A device isolation method for a semiconductor device according to the present invention includes a step of laminating a first oxide film and a first nitride film on the surface of a semiconductor substrate, and a step of stacking a first oxide film and a first nitride film on the surface of a semiconductor substrate, and performing the step of laminating the first oxide film and the first nitride film using a photoresist as a mask. selectively removing a first nitride film, a first oxide film, and a region extending to a predetermined depth from the surface of the semiconductor substrate to form a groove or a recess; oxidizing the side and bottom surfaces of the groove or recess to form a second oxide film; forming a second nitride film on the second oxide film on the side surfaces of the groove or recess; oxidizing the semiconductor substrate using a second nitride film as a mask to form a third oxide film on the lower side surfaces and bottom of the groove or recess, and removing the first and second nitride films; The method is characterized by comprising a step of selectively removing the third oxide film while leaving it only on the side surfaces of the groove or recess.

[Operation] In the present invention, a groove or a recess is selectively formed in a semiconductor substrate, and the semiconductor substrate is formed using the first and second nitride films provided as masks to cover areas other than the bottom surface of the groove or recess. oxidizes. As a result, a third oxide film is formed on the lower part of the side surface of the groove or recess and on the bottom surface of the groove. Next, the first and second nitride films are removed, and the third oxide film is selectively removed leaving it only on the side surfaces of the trench. Then,
An oxide film for element isolation is formed on the sidewalls of the trench, and the bottom surface of the trench and the main plane of the semiconductor substrate (the top surface of the convex portion) are used as active regions. Therefore, the element isolation region is formed on the side surface of the groove perpendicular to the main plane of the substrate, and there is no need to reserve a region along the substrate surface as the element isolation region as in the conventional case, so that the degree of integration can be significantly improved.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

First, as shown in FIG. 1(a), a first oxide film 2 is formed on a P-type semiconductor substrate 1, and a carbon dioxide film is formed on this first oxide film 2.
A first nitride film (first CVD nitride film) 3 is grown by the VD method. Next, photoresist 4 is selectively formed on the first nitrided M3 at appropriate intervals.

Thereafter, as shown in FIG. 1(b), the photoresist 4
Using as a mask, the first CVD nitride film 3 and the first oxide II
! 2 is selectively removed, and then the surface of the P-type semiconductor substrate 1 is selectively removed over a predetermined depth. As a result, a groove portion having a groove bottom surface 5 and a groove side surface 6 is formed on the surface of the P-type semiconductor substrate 1.

Next, as shown in FIG. 1(c), after removing the photoresist 4, the bottom surface 5 and side surfaces 6 of the groove of the P-type semiconductor substrate 1 are oxidized using the first CVD nitride film 3 as a mask. A second oxide film 7 is formed on the bottom surface 5 and the trench side surfaces 6.

Furthermore, a second nitride film (second
A CVD nitride film) 8 is grown.

Next, as shown in FIG. 1(d), a second CVD nitride film 8
is etched by anisotropic etching, leaving only the portions forming the side walls of the grooves and etching away the other portions.

Next, as shown in FIG. 1(e), a field oxide film 9 is formed by thermal oxidation using the second CVD nitride film 8 remaining on the first CVD nitride film and the third trench sidewall as a mask. In this case, this field oxide film 9
In this case, due to diffusion growth from the groove bottom surface 5, it is formed to swell into a shape similar to a bird's beak.

Next, as shown in FIG. 1(f), the second CVD nitride film 8 remaining on the side surfaces 6 of the first CVD nitride and third trenches is removed.
remove.

Thereafter, as shown in FIG. 1(g), by anisotropically etching the oxide film 9, the field oxide film 9 remains only on the side surfaces 6 of the trench, and the field oxide film 9 on other parts is selectively etched. to be removed. In this case, first oxide film 2 is also removed at the same time.

Next, as shown in FIG. 1(h), after forming a gate insulator M10 on the substrate surface (the top surface of the protrusion and the bottom surface of the groove), a polycrystalline silicon gate electrode 11 is formed with a predetermined width across the plurality of grooves. Form a pattern so that it extends.

FIG. 1(i) is a perspective view showing a part of the layer structure formed in this manner. The cross-sectional view in FIG. 1(h) is taken along plane A in FIG. 1(i). The subsequent steps will be explained based on a sectional view taken along plane B or plane 0 of FIG. 1(i).

Figures 1 (j) to (() are cross-sectional views cut at plane B of Figure 1 (i), Figure 1 (m> to (0) are cross-sectional views cut at plane 0 of Figure 1 (i) FIG.

First, as shown in FIGS. 1(j) and 1(m), N-type impurities such as arsenic are ion-implanted into the substrate 1 using the selectively formed polycrystalline silicon gate electrode 11 as a mask.
A mold diffusion layer 12 is formed.

Next, as shown in FIG. 1(k) and FIG. 1(n), a glabellar insulating film 13 is formed on the entire surface.

Finally, as shown in Figure 1 (!ri) and Figure 1 (o),
A semiconductor device is manufactured by forming a contact hole 14 in the glabella insulating film 13 and selectively forming an aluminum electrode 15 so as to fill the hole 14.

In this way, in the method of this embodiment, after forming grooves at appropriate intervals on the surface of the semiconductor substrate 1, the substrate is oxidized using the first nitride film 3 and the second nitride film 8 as masks. Then, a field oxide film (
A third oxide film) 9 is formed. After removing the first and second nitride films 3 and 8, a third oxide film 9 is placed on the trench side surface 6.
Only some parts remain and other parts are selectively removed. As a result, an element isolation region is formed by the field oxide film 9 on the side surface of the trench. This element isolation region is not formed extending along the surface of the semiconductor substrate 1 as in the conventional case, but is formed extending along the side surface of the groove, that is, in a direction perpendicular to the surface of the semiconductor substrate 1. Therefore, by utilizing the main plane (upper surface of the convex portion) and the bottom surface of the groove portion of the semiconductor substrate 1 as an active region for forming elements, the degree of integration can be significantly improved. Moreover, in this element isolation method, there is no need to add a photomask process compared to the conventional method, and the process does not become complicated. Furthermore,
The oxide film 9 for element isolation on the sidewalls of the trench thus formed is formed with an appropriate slope with respect to the sidewall of the trench, so it is easy to process in a later process, for example when forming a gate electrode. will improve.

FIGS. 2(a) and 2(b) are a perspective view and a sectional view, respectively, showing a semiconductor device manufactured by the second embodiment method of the present invention.

In this second embodiment, first, a P-type semiconductor substrate 1
An N-type well 16 is formed in the formation region of the N-type well 16, and a recess 1 deeper than the depth of the N-type well 16 is formed in the formation region of the N-type well 16.
form 7. Thereafter, in the same manner as in the first embodiment, field oxidation H9 is formed only on the side surfaces of the recess 17, and the polycrystalline silicon gate electrode 11, diffusion layer 12, interlayer insulating film 1
3 and aluminum electrode 15,
Manufacture semiconductor devices.

In the semiconductor device manufactured in this manner, the aluminum electrode 15 connected to the N-type diffusion layer 12 formed in the N-type well 16 is connected to the train, and the N-type diffusion layer formed at the bottom of the recess of the P-type semiconductor substrate 1 is By using the aluminum electrode 15 connected to the transistor 12 as a source, a high voltage N-type transistor is constructed. On the other hand, the method of this embodiment does not require any additional steps compared to the conventional method.

[Effects of the Invention] As explained above, the present invention selectively forms grooves or recesses in a semiconductor substrate, selectively forms an oxide film for element isolation on the side surfaces of the grooves, and performs element isolation. Since the bottom of the recess and the main plane of the semiconductor substrate are used as active regions, unlike the conventional method of device isolation, there is no need to provide a region for device isolation that extends along the surface of the semiconductor substrate, which increases the degree of integration of semiconductor devices. Significantly improved.

Further, the method according to the present invention has the advantage that there is no need to add a new photomask process, and the oxide film for element isolation is formed in self-alignment with the trench sidewalls.

Furthermore, when an oxide film for element isolation is formed on the trench sidewalls by the method of the present invention, this oxide film is formed with an appropriate slope with respect to the trench sidewalls. It is extremely effective in improving workability.

[Brief explanation of the drawing]

FIGS. 1(a> to (h), FIG. 1(j) to <i>, and FIG. 1(m) to (0) are sectional views showing embodiments of the present invention in the order of steps, and FIG. 1(i). ) is a perspective view showing an intermediate step, FIG. 2(a) is a perspective view showing another embodiment of the present invention, FIG. 2(b) is a sectional view thereof, and FIGS. (f) is a cross-sectional view showing the conventional method in the order of steps. 1.41: p-type semiconductor substrate, 2: first oxide film, 3: first
CVD nitride film, 4.44. Photoresist, 5; trench bottom surface, 6; trench side surface, 7; second oxide film, 8; second CVD nitride film, 9, 45; field oxide film, 10, 46; gate insulating film, 11, 47; polycrystalline silicon gate electrode, 12;
N-type diffusion layer, 13; interlayer insulating film, 14; contact hole, 15; aluminum ti, 16; N-type well, 42
;Thermal oxide film, 43;CVD nitride film

Claims (1)

[Claims] A step of laminating a first oxide film and a first nitride film on the surface of the semiconductor substrate, and using a photoresist as a mask, depositing the first nitride film and the first oxide film and the first nitride film at a predetermined depth from the surface of the semiconductor substrate. forming a groove or recess by selectively removing a region that spans the area; oxidizing the side and bottom surfaces of the groove or recess using the first nitride film as a mask to form a second oxide film; forming a second nitride film on the second oxide film on the side surface of the groove or recess; and oxidizing the semiconductor substrate using the first and second nitride films as masks; and forming a third oxide film on the bottom surface of the first and second oxide films.
1. A method for isolating elements in a semiconductor device, comprising the steps of: removing the nitride film and selectively removing the third oxide film while leaving it only on the side surfaces of the trench or recess.