JPS62219960A - Manufacture of thin film mos structure semiconductor device - Google Patents

Abstract

PURPOSE:To provide the gate electrodes and the Si films of a thin film MOS structure semiconductor device which is composed of an insulating substrate and Si films such as polycrystalline silicon films in a complete parallel arrangement structure in which no difference in level exists by a method wherein the element isolation in the thin film MOS structure semiconductor device is made after gate electrodes, gate insulating films and active regions composed of sources and drains are formed. CONSTITUTION:Gate oxide films covering source and drain forming regions 10 are removed by etching with buffered fluoric acid solution by using a resist pattern 8 as a mask to drill windows in the source and drain regions. Then P<+> ions are activated to form source and drain regions 10. Further, gate electrode patterns are formed. After that, SiO2 gate oxide films 3 are removed and then the Si films 2 immediately under the films 3 are removed by plasma etching with mixed gas of CF4 and H2 and then with CCl2F2 gas respectively by using a composite photoresist pattern as a mask to isolate elements perfectly. After that, the photoresist is removed by ashing and the element isolation process is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a thin film fl1MOS structure semiconductor device.
The present invention relates to an element isolation step in the manufacturing method of i1m Transistor + thin film 2/distano.

Conventional technology Isolation between elements of a thin film type MOS structure semiconductor element (TPT) is basically performed in the following steps. As shown in FIG. 3g, a semiconductor film such as polysilicon is formed on an insulating substrate 1, and the semiconductor film between the active regions consisting of the source, drain, and gate is removed by etching using photolithography technology. After forming the islands 2', the active regions can be separated by forming a gate oxide film 3 by thermal oxidation.

Next, a gate electrode material 4i is formed on the gate oxide film, patterned into a desired shape by photolithography, and then a thin film temperature MOB structure semiconductor device is completed by a normal MOS process.

Although this manufacturing method is characterized by a simple processing method and a small number of steps, it has the following drawbacks.

Part 1 is the side surface of the island-like 84 substrate and the insulated substrate surface 1.
This is because the gate oxide film becomes thinner due to lack of Si in the area where the two surfaces contact each other (A in FIG. 3). Therefore, when using TPT, the electric field strength of the gate oxide film near point A becomes locally strong, increasing the risk of dielectric breakdown.

Second, the level difference on the surface is significantly reduced, which reduces the accuracy of photolithography in subsequent steps and increases the risk of short circuits and disconnections due to the level difference in the wiring.

Therefore, in order to eliminate this drawback, it is manufactured by an element isolation method (coplanar process) based on the LOCO8 method, which is generally adopted in the Si substrate MOSLSI process.

As shown in FIG.
Deposit i-film 2. After forming a thin -8402 film 5 using a thermal oxidation method, a silicon nitride film 61, ! is formed using a CVD method. MO, 7t
-Sequential deposition. The purpose of the underlying St 02 film is to prevent troubles caused by contact between the element substrate S1 film and the silicon nitride film. As shown in FIG. 30, the photoresist 8 is patterned using photolithography, and the upper layer is first patterned! 1t(h 7 is partially removed and the third
Figure g), and then use it as an etch mask for the silicon nitride film 6! The 402 film 5 and polysilico/2T are sequentially removed by etching to obtain the structure shown in FIG. At this time, the substrate Si
The key to this process is to thicken the membrane 2'' by about half its thickness.

Next, the Sio2 film 7t is removed and thermally oxidized, and the portion of the substrate St2' not protected by silicon nitride is completely oxidized to about twice the thickness, as shown in Figure 5I. It becomes a structure.

When the silicon nitride film 6 and its lower layer are removed, a flat device isolation structure is obtained in which the upper surface of the Si film 2' separated from the silicon nitride film 6 is continuous, as shown in FIG. 1g. After that, a gate oxide film 5t is again formed on the separated Si film 2', and then a gate electrode material 4 is deposited (Fig. 3s) and patterned by phosphorography. - (Fig. 5 j, k), after that, the MOB structure element is formed by a normal process, and finally the third
The structure shown in FIG. 9 is completed.

The conventional device isolation method described above requires a large number of steps and takes a long time.Furthermore, the key point is to leave approximately half the thickness of the Fj4 substrate during etching, resulting in poor etching controllability and flatness. It has the disadvantage that it fluctuates from time to time.

The process takes a long time because of the following reasons: (a) It is necessary to deposit silicon nitride as a mask for selective oxidation.

(b) Since this silicon nitride is used, it is necessary to form a sandwich structure with SiO layers.

G-1 deposited! 1i02. It is necessary to remove the silicon nitride film.

It's a weak thing.

Purpose of the Invention The present invention is proposed to solve the above-mentioned drawbacks.
The purpose of this is to achieve high productivity isolation between elements of a thin-g deaf MOB structure semiconductor device, which has a structure that prevents local dielectric breakdown on the side surfaces of the gate electrode and the island-like 84 substrate.
vhThe purpose of the present invention is to provide a method that can be formed in a short manufacturing process time.

Structure of the Invention In order to achieve the above object, the present invention provides a thin film type MOEJ using a Si film such as polysilicon deposited on an expanded insulating substrate.
The gist of the present invention is to perform element isolation of a semiconductor device having a structure after forming an active region consisting of a gate insulating film, a gate electrode, and a source/drain. The present invention
As the gate electrode material, not only high melting point materials such as polysilicore, but also low melting point materials such as μ having high conductivity can be used. In the conventional various element isolation methods, a part of the 84774 is etched away before forming the active region, and a part of the 84774 is made into an insulator to achieve electrical isolation between the active regions. In order to achieve a flattened element surface after the inter-element isolation process, from the viewpoint of improving the yield by preventing defects and improving the precision of the structure of the active region, various complex processes were carried out.
In contrast, the present invention uses a manufacturing method in which the active regions are first formed in an initial shape with a flat surface, and then the active regions are separated. The gate electrode and the film 84 have a completely parallel arrangement structure with no step difference, thereby eliminating the cause of local dielectric breakdown between the gate electrode and the film 84. In addition, a different feature from conventional methods is that the time required for the process can be significantly shortened. When using a low melting point metal for the gate electrode material, it is necessary to use the following process to form a gate insulating film on the polysilicon (O8) film, such as polysilicon, on the insulating substrate, and the process of forming the source layer of the MOS structure element using photolithography.
covering areas other than the drain region with photoresist;
This photoresist is used as an etching mask for the source
A step of etching away some or all of the gate insulating film in the drain region and opening a window in the source/drain region, and forming a source tray 7 by introducing impurities through the window in the source tray 7 region. a step of depositing a gate electrode material on the gate insulating film; a step of patterning this electrode material using photolithography technology; and a step of depositing a photoresist T- m cloth, and source and photolithography.
The drain region and gate electrode pattern are coated with photoresist and this photoresist is used as an etching mask.
& The gate insulating film other than the region where the structural elements are formed and the O8 immediately below it (step 1 to completely remove the film and isolate the elements, and 5i after removing all the photoresist)
The gist of the invention is a method for manufacturing element isolation of a thin film Hgos structure semiconductor device, which is characterized by including a step of depositing on the entire surface.

When using a high-melting point material such as polysilicon for the gate electrode material, the following process involves forming a gate insulating film on polysilicon, etc. Step 1 of depositing a melting point gate electrode material, Step 2 of buttering this gate electrode material using a photo ring 2-fi technique, Step 1 of forming a source/drain using the remaining gate electrode pattern as a mask for impurity introduction. The process of introducing other impurities using Selfa Line.

Subsequently, the entire surface is coated with photoresist again, and the area where the source tray 7 is to be formed and the gate electrode pattern area are covered with T7T resist using photolithography technology. A step of completely etching away the resist-covered gate insulating film and the Si film immediately below it until a different surface of the insulating substrate is exposed.

A process of removing a photoresist used as an etching mask; a heat treatment process for activating impurities introduced into the source/drain; a process of depositing 8402 on the entire surface; and an element of a thin film MOB structure semiconductor device containing gold. The gist of the invention is a method of manufacturing a treasury.

Next, an example will be explained.

[Example 1] Figure 1 shows the thin film II MO! A method for manufacturing a semiconductor device according to the present invention in the case where a low melting point metal, 4Jt-, is used for the gate electrode of an L-structure element is shown in nine embodiments according to the process order. An insulating substrate (made of quartz) shown in FIG. 1 was deposited with a grainy silicon film 2 to a thickness of 20001 L by the VCCVD method. Next, a gate oxide film 5 of 100X was formed by wet thermal oxidation at 900°C for 2G (FIG. 1, 6).
. Subsequently, a photoresist pattern 8t- is formed on the gate oxide film 50 in a region other than the region 10 where the source/drain of the MOS structure element is formed by photolithography.
Formed. (FIG. 1 6) Using the resist pattern 8 as an etching mask, the gate oxide film covering the source/drain forming region 100 is removed by etching with a buffered hydrofluoric acid solution, and as shown in FIG. Form a structure with a window in the area fc.

Next, using the etching resist mask 8 as a mask for ion implantation, the source/drain windows were implanted with 1M ions (CP+)t'' at 130KaV, 5 x 1QVo inert2.
Injected. After removing the photoresist 8 by ashing, 91J
Was it injected by heat treatment at O°C for 20 minutes? Activates ions,
A source/drain 10 was formed as shown in FIG.

Next, AJ was used as a gate electrode material by sputtering.
6,000 λ was deposited and selectively etched using a phosphoric acid etching solution using photolithography to form a row φ gate electrode pattern as shown in 4 in FIG. 1V.

As shown in No. 115, with the photoresist 8f left on the gate electrode pattern, a photoresist is further coated on the entire surface, and by photolithography technology, MO5
Seven otocysts 8' were formed in the active area of the structural element.

From the plan view of Figure 2, Figure 1 H to Rekarutori t), M
The OS structure element area is covered with a composite pattern of photoresists 8 and 8/. As an etching mask on the synthetic photoresist pattern, first 8402 (gate oxide film 3) is removed by plasma etching using a mixed gas of CF4 and H2, and then the Si film 2t immediately below it is removed using 5cx, r, gas. - The elements were completely separated by etching. (FIG. 1) After that, the photoresist is removed by ashing, and the element isolation process is completed.

As can be clearly seen from the three-dimensional view j after the resist is removed in FIG. This completely prevents local dielectric breakdown due to electric field concentration at sidewall steps, resulting in a dangerous structure.

Thereafter, 11ft of St 02 film was deposited using the normal process.
Through holes for contact with the source, tray/gate electrodes were formed in this and connected with An wiring 12 to complete a thin film type MOB structure semiconductor device tIL as shown in FIG. 1k.

In this embodiment, the impurity (phosphorus) for forming the source/drain l- was introduced by ion implantation, but it goes without saying that other methods such as diffusion can also be used. In addition, the manufacturing method allows the use of low melting point metals such as µ, which forms the gate electrode after high-temperature treatment such as activation heat treatment of implanted impurities.

[Embodiment 2] FIG. 2 is an embodiment showing a method for manufacturing a semiconductor device according to the present invention in the order of steps when polysilicon is used for the gate electrode of a thin film 12MOS structure element. A polysilicon film 2 was deposited to a thickness of t-20001 on an insulating substrate (made of quartz) 1 shown in FIG. 2G by the CVD method. followed by 90
A gate oxide film 3T of 1000λ was formed using a wet oxidation method for 9020 minutes. (Fig. 2b) Next, as the gate electrode material 4, polysilico y f with a thickness of 5000
After depositing the polysilicon to a film thickness of , As shown in FIG. 2d, using the gate electrode pattern coated with photoresist as a mask for ion implantation, form source/drain regions with self-alignment lines.
150 KmV (D: L gear 5 x 101s
Next, 101 pieces were implanted into the O84 film except for the gate electrode pattern. Next, without removing the photoresist 8 on the gate electrode pattern, a photoresist is applied to the entire surface, and as shown in FIG. and on the channel region under the gate electrode. Figure 2 f
is a plan view of FIG.

The region where the photoresist patterns 8 and 8' overlap and have φ becomes the channel region of the MOS structure element.

The synthesized photoresist patterns 8 and 8 were first removed by plasma etching using a mixed gas of CF4 and H2 as an etching mask.
Subsequently, using CCjL, JP, and gas, the Si film 2f immediately below it is removed by etching, and as shown in FIG.
l structure The active elements are completely separated.

After removing the photoresist pattern by ashing, heat at 900°C.
Heat treatment was performed for two films, and the implanted nine phosphorus ions were activated to form source/drain regions 10i as shown in FIG. 2-5. Thereafter, after depositing the StO film, the same steps as in Example 1 were carried out to complete the structure shown in Figure 2.Since heat-resistant polysilicon was used as the gate electrode material, the gate electrode was formed. However, the difference from Example 1 is that high temperature treatment is possible and the Selfaline method can be applied, but the structure that prevents local dielectric breakdown is completely the same as Example 1. In the example, s (using polysilicon as the film and using a thermal oxide film as the gate insulating film)
Although ion implantation is used to form source and drain,
Without departing from the spirit of the present invention, 84 films of t-GaAa
In addition, the gate insulating film is made of silicon nitride, or 9(0, f
It goes without saying that various changes and improvements can be made to the T-deposition method, such as changing the source/drain formation to a thermal diffusion method.

In addition, in the above example, the O84 film is removed in all areas other than the region where the source/drain is formed and the gate electrode, but the region where the source/drain region and the gate electrode are formed of different TPTs are removed. If the region O34 film to be formed is discontinuous, part of the film O8 (film may be removed).

Effects of the Invention As described above, according to the present invention, in a semiconductor device with a thin gfJMOSj structure, it is possible to achieve isolation between elements in a structure in which the gate electrode and the Si substrate are completely kept flat through the gate oxide film. Since it can be formed, there is an advantage that local reduction in breakdown voltage of the gate insulating film can be prevented. In addition, the active region consisting of the gate, source, and drain of the Mol structure element is formed at an early stage when the substrate surface is flat, and the processing accuracy is high. , yield]. In addition, the use of a highly conductive metal material for the gate electrode has the advantage of being applicable to high-speed semiconductor devices.

The device isolation method according to the present invention has the above advantages.

Compared to conventional methods, this manufacturing method can greatly reduce the number of steps required, so it is expected to have the effect of increasing productivity.

[Brief explanation of drawings]

FIGS. 1G to 1G are plan views of process lines H and h, respectively, showing process diagrams of a method for manufacturing a thin film FF1MOS structure semiconductor device according to an embodiment of the present invention. FIG. 2 shows a thin film m according to another embodiment of the present invention.
A process diagram of the manufacturing method of a MOS structure semiconductor device 1 Insulating substrate Z Si film (substrate Si film) 2' Separated Si film 3 Gate oxide film 4 Gate electrode (material) 5 Base! 1401 film 6 Silicon nitride film 7 Mask 540. Belly 8 Photoresist 8' Upper layer of double photoresist 9 Oxidation of polysilicon for isolation between elements 540210
Source and drain 11 Interlayer 8402 12 Aj! Electrode patent applicant Nippon Telegraph and Telephone Co., Ltd. agent Patent attorney Tama Mushi Hisa 5 Department (Ref-z%) 0
,Ω
To 0 − “0 Φ &, −■,
C engineering

Claims (3)

[Claims] (1) Thin film type M using a Si film deposited on an insulating substrate
In a method for manufacturing an OS structure semiconductor device, after a process including at least a step of forming a gate insulating film, a step of introducing impurities for forming a source/drain into the Si film, and a step of forming a gate electrode, the source・A method for manufacturing a thin-film MOS structure semiconductor device characterized by performing isolation between elements by removing the Si film other than the region where the drain is formed and the region where the gate electrode is formed. (2) The step of removing the Si film includes the steps of: coating the entire surface of the photoresist again and covering the source/drain region and the gate electrode pattern region with the photoresist using photolithography; and removing the photoresist. Claim 1, characterized in that the step of completely etching away portions of the gate insulating film and the Si film not covered with the photoresist as an etching mask until the surface of the insulating substrate appears is performed in sequence. A method for manufacturing a thin film MOS structure semiconductor device. (3) The step of removing the Si film includes a step of coating the entire surface with photoresist again, and using photolithography to cover the region where the source/drain will be formed and the gate electrode pattern region with photoresist, and removing the photoresist. Claim 1 characterized in that, as an etching mask, a step of completely etching away portions of the gate insulating film and the Si film that are not covered with the photoresist are sequentially performed until the surface of the insulating substrate appears. A method for manufacturing a thin-film MOS structure semiconductor device as described in 1.