JPH0529346A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a contact resistance and a source drain resistance by forming an interlayer insulation film on a TFT and providing a contact hole for the interlayer insulation film after a silicide treatment is given to the surface of the source and drain areas of the TFT. CONSTITUTION:A silicide layer 10 is formed by giving a silicide treatment to the surface of the source and drain areas 6 of a TFT by annealing subsequent to the removal of a resist pattern 11 and a high fusion point metallic film 12 of the resist pattern 11 by a lift-off method after the formation of the high fusion point metallic film 12 by a CVD method or the like. Then, after the annealed high fusion point metallic film 12 is removed by etching, an interlayer insulation film 7 is produced by a CVD method or the like. Subsequently, a contact hole 8 is formed by a lithography and etching method and then an aluminum wiring layer 9 is formed. Thus, good and stabilized characteristics can be obtained in a semiconductor device provided with a TFT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a thin film transistor, and more particularly to an improvement of a method of forming a contact portion between a source and drain portion and a wiring layer.

[0002]

2. Description of the Related Art In recent years, high integration and miniaturization have rapidly progressed in semiconductor devices, and along with that, there have been remarkable advances and improvements in various technologies. The wiring technology is no exception, and further improvement is required especially for the contact hole portion.

FIG. 3 is a sectional view showing the structure of a contact hole portion in a conventional semiconductor device. In the figure, 1
Is a semiconductor substrate made of single crystal silicon or the like, 2 is an interlayer insulating film made of an oxide film formed on the semiconductor substrate 1, 3
Is a gate electrode made of a doped polysilicon film formed on the interlayer insulating film 2, 4 is a gate oxide film formed on the gate electrode 3 and the interlayer insulating film 2, and 5 is a gate oxide film 4 formed on the gate oxide film 4. A channel polysilicon film formed on the channel polysilicon film 6, a source / drain portion formed on the channel polysilicon film 5, an interlayer insulating film 7 made of an oxide film, 8
Is a contact hole selectively provided in the interlayer insulating film 7, and 9 is a wiring layer made of an aluminum film formed on the interlayer insulating film 7.

Next, a method of manufacturing the semiconductor device configured as described above will be sequentially described with reference to FIGS. First, an interlayer insulating film 2 is formed on the semiconductor substrate 1 to a thickness of about 2000 Å, and a doped polysilicon film is deposited on the semiconductor substrate 1 to a thickness of about 1500 to 2500 Å by a CVD method or the like, and photolithography and etching are performed to form the gate electrode 3. It is formed (FIG. 4 (a)). Next, a gate oxide film 4 is formed on the entire surface to a thickness of 150 to 300 Å (FIG. 4 (b)). Next, a polysilicon film is formed on the entire surface.
After depositing about 200 Å, impurities are introduced by, for example, an ion implantation method or the like to form a channel polysilicon film 5. After that, a pattern 5 of a thin film transistor (hereinafter referred to as a TFT) is formed by performing photolithography, etching and the like (FIG. 4 (c)). Next, a resist is applied on the entire surface and photolithography is performed to form a resist pattern 11. Using the resist pattern 11 as a mask, impurities are introduced by, for example, an ion implantation method to form the source and drain portions 6 of the TFT (FIG. 4 (d)). Then, after removing the resist pattern 11, an oxide film of about 2000 Å is deposited on the entire surface by a CVD method or the like to form an interlayer insulating film 7.
Next, a contact hole 8 is formed by photolithography and etching, and then a wiring layer 9 made of aluminum is formed by sputtering (FIG. 3).

[0005]

The conventional semiconductor device is constructed as described above, and since the channel polysilicon film 5 forming the TFT is very thin as shown in FIG. 3, ion implantation or the like is performed. When impurities are introduced by the method, ions penetrate through the polysilicon film 5, and it is difficult to control the ion concentration in the source / drain portion 6 of the TFT, so that the characteristics vary. Furthermore, since the etching rate ratio between the interlayer insulating film 7 and the channel polysilicon film 5 is about 10, when the channel polysilicon film 5 is thin, the interlayer insulating film 7 is not covered with the interlayer insulating film 7 when the contact hole 8 is formed. Not only the film 7, but the source of the TFT,
There is a problem that the gate oxide film 4 is penetrated through the drain portion 6 and the gate oxide film 4 is also etched, resulting in variations in characteristics, and a highly reliable semiconductor device cannot be obtained.

The present invention has been made to solve the above problems, and an object thereof is to obtain a method of manufacturing a semiconductor device having a TFT, which has good and stable characteristics.

[0007]

A method of manufacturing a semiconductor device according to the present invention provides a gate electrode provided on a first interlayer insulating film of a semiconductor substrate and a gate electrode provided on this electrode via a gate insulating film. In a method of manufacturing a semiconductor device including a transistor including a semiconductor thin film having a drain and a source region, a step of siliciding the drain and source regions of the semiconductor thin film, and a second interlayer insulating film covering the semiconductor thin film. It includes a step of providing and a step of providing an opening reaching the drain and source regions of the semiconductor thin film in the second interlayer insulating film by an etching method.

Further, in the method of manufacturing a semiconductor device according to the present invention, the gate electrode provided on the first interlayer insulating film of the semiconductor substrate, and the drain and source provided on the electrode via the gate insulating film. In a method for manufacturing a semiconductor device including a transistor including a semiconductor thin film having a region,
A step of forming a semiconductor film on the gate insulating film and patterning; a step of forming a photosensitive resin on the semiconductor thin film and patterning, and then performing ion implantation using the photosensitive resin as a mask; Of a high melting point metal film on the semiconductor substrate including the entire surface of the photosensitive resin, and then dissolving the photosensitive resin to remove the high melting point metal film on the non-ion-implanted region of the semiconductor thin film. It includes and.

[0009]

In the present invention, since the surface of the source and drain portions of the TFT is silicidized, the contact resistance is reduced, and the difference in etching rate between the interlayer insulating film and the silicide film becomes sufficiently large. When the contact hole is formed in the TFT, the source and drain portions of the TFT and the gate oxide film are not excessively etched.

Further, since the silicide layer is formed on the surface of the source / drain portion of the TFT by the lift-off method using the resist mask for ion implantation to the source / drain portion of the TFT, the pattern shift is prevented.

[0011]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the description of the same parts as those of the conventional technique will be appropriately omitted.

FIG. 1 is a sectional view showing a structure of a contact hole portion of a semiconductor device according to an embodiment of the present invention. In the figure, 1 to 9 are equivalent to those in the conventional example, and 10 is a TFT. The silicide layer formed on the surface of the source / drain portion 6 constitutes the bottom of the contact hole 8.

FIG. 2 is a sectional view showing a manufacturing process in a contact hole portion of the semiconductor device of FIG. This Figure 2
The steps up to (a) are the same as the steps shown in FIGS. 4 (a) to 4 (d), and a detailed description thereof will be omitted. Next, the vapor deposition method,
Refractory metal film by sputtering or CVD method 1
2. Titanium, for example, is formed to about 100Å which is 1/2 of the TFT film thickness (FIG. 2 (a)). Next, after removing the resist pattern 11 and the refractory metal film 12 of the resist pattern 11 by the lift-off method, the surface of the source / drain portion 6 of the TFT is silicidized by the annealing method to form a silicide layer 10, for example, titanium silicide. . At this time, since the silicide layer 10 is patterned using the resist pattern 11 used at the time of forming the source / drain portion 6, the source / drain portion 6 of the TFT and the silicide layer 10 do not cause pattern shift (FIG. 2). (b)). next,
After removing the annealed refractory metal film 12 by an etching method, an interlayer insulating film 7 is formed on the entire surface by a CVD method or the like.
An oxide film of about 2000Å is formed (Fig. 2 (c)). Then, as shown in FIG. 1, a contact hole 8 is formed by photolithography and etching. At this time TF
Since the surface of the source / drain portion 6 of T is the silicide layer 10, the etching rate ratio between the interlayer insulating film 7 and the silicide layer 10 is 20: 1 or more. When providing the above, the contact hole 8 can be stably formed without excessively etching the source / drain portion 6 and the gate oxide film 4 of the TFT. After that, an aluminum film is formed by a sputtering method or the like, and an aluminum wiring layer 9 is formed by a photoengraving method or an etching method. Since the surface of the source / drain portion 6 of the TFT is the silicide layer 10 in this case as well. The contact resistance and the source / drain resistance are reduced, and good electrical connection can be obtained.

Example 2. In the above embodiment, titanium is used as the refractory metal film 12 when forming the silicide layer 10, but any refractory metal such as molybdenum, tantalum, platinum, or tungsten may be used. The same effect as that of the above embodiment is obtained.

[0015]

As described above, after the surface of the source and drain regions of the TFT is silicidized, the interlayer insulating film is formed on the TFT, and the contact hole is formed in this interlayer insulating film. Also, the source / drain resistance can be reduced, the difference in etching rate between the interlayer insulating film and the silicide layer becomes sufficient, the process margin at the time of forming the contact hole can be expanded, and good and stable electrical characteristics can be obtained. There is an effect that a high manufacturing method of a semiconductor device can be obtained.

Further, when impurities are introduced to form the source and drain regions of the TFT, the photosensitive resin used as a mask is used as it is as a mask, and TF is used.
Since the silicide layer is formed on the surface of the source / drain portion of T, the silicide layer and the source / drain region can be formed without causing a pattern deviation, and good and stable electric characteristics can be obtained, so that the semiconductor is highly reliable. There is an effect that the method for manufacturing the device can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a contact hole portion of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts showing a manufacturing process for the semiconductor device shown in FIG.

FIG. 3 is a sectional view showing a structure of a contact hole portion of a conventional semiconductor device.

FIG. 4 is a sectional view of a key portion showing a manufacturing step of the semiconductor device shown in FIG.

[Explanation of symbols]

1 Semiconductor substrate 2 Interlayer insulation film 3 Gate electrode 4 Gate oxide film 5-channel polysilicon film 6 Source and drain 7 Interlayer insulation film 8 contact holes 9 wiring layers 10 Silicide layer 11 Resist pattern 12 Refractory metal film

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[Procedure amendment]

[Submission date] January 10, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction content]

[0001]

BACKGROUND OF THE INVENTION This invention relates to a manufacturing method of a semiconductor device having a thin film transistor is of particular source, to an improved method of forming the contact portion between the drain unit wiring layer.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

[0005]

The conventional semiconductor device is constructed as described above, and since the channel polysilicon film 5 forming the TFT is very thin as shown in FIG. 3, ion implantation or the like is performed. When impurities are introduced by the method, ions penetrate through the polysilicon film 5, and it is difficult to control the ion concentration in the source / drain portion 6 of the TFT, so that the characteristics vary. Furthermore, since the etching rate ratio between the interlayer insulating film 7 and the channel polysilicon film 5 is about 10, when the channel polysilicon film 5 is thin, the interlayer insulating film 7 is not covered with the interlayer insulating film 7 when the contact hole 8 is formed. Not only the film 7, but the source of the TFT,
Only disconnect pokes drain portion 6 causes a variation in characteristics, highly reliable semiconductor device has a problem such not be obtained.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

FIG. 2 is a sectional view showing a manufacturing process in a contact hole portion of the semiconductor device of FIG. This Figure 2
The steps up to (a) are the same as the steps shown in FIGS. 4 (a) to 4 (d), and a detailed description thereof will be omitted. Next, the vapor deposition method,
Refractory metal film by sputtering or CVD method 1
2. Titanium, for example, is formed to a thickness of about 100Å which is 1/2 of the TFT film thickness (FIG. 2 (a)). Next, after removing the high melting <br/> point metal film 12 on the resist pattern 11 and the resist pattern 11 by lift-off method, TFT source, the 6 surfaces of the drain portion silicided by annealing the silicide layer 10, For example, titanium silicide is formed. At this time, since the silicide layer 10 is patterned using the resist pattern 11 used when forming the source / drain portion 6, the source / drain portion 6 and the silicide layer 10 of the TFT are patterned.
And do not cause pattern shift (Fig. 2 (b)). Next, the annealed refractory metal film 12 is removed by an etching method, and then an oxide film to be the interlayer insulating film 7 is formed on the entire surface by a CVD method or the like to a thickness of about 2000 Å (FIG. 2C).
Then, as shown in FIG. 1, a contact hole 8 is formed by photolithography and etching. At this time, the surface of the source / drain portion 6 of the TFT is the silicide layer 10
Therefore, the etching rate ratio between the interlayer insulating film 7 and the silicide layer 10 is 20: 1 or more,
When the contact hole 8 is formed in the interlayer insulating film 7, the TFT
The contact hole 8 can be stably formed without excessively etching the source / drain portion 6 . After that, an aluminum film is formed by a sputtering method or the like, and an aluminum wiring layer 9 is formed by a photoengraving method, an etching method, or the like. Since the surface of the source / drain portion 6 of the TFT is the silicide layer 10 in this case as well. The contact resistance and the source / drain resistance are reduced, and good electrical connection can be obtained.

Claims (2)

[Claims] 1. A transistor comprising a semiconductor thin film having a gate electrode provided on a first interlayer insulating film of a semiconductor substrate, and a drain and a source region provided on the gate electrode via a gate insulating film. In the method for manufacturing a semiconductor device, a step of siliciding the drain and source regions of the semiconductor thin film, a step of providing a second interlayer insulating film to cover the semiconductor thin film, and the semiconductor to the second interlayer insulating film. A method of manufacturing a semiconductor device, comprising a step of forming an opening reaching a drain and a source region of a thin film by an etching method. 2. A transistor comprising a semiconductor thin film having a gate electrode provided on a first interlayer insulating film of a semiconductor substrate, and a drain and a source region provided on the electrode via a gate insulating film. In the method of manufacturing a semiconductor device, a step of forming a semiconductor thin film on the gate insulating film and patterning, and a step of forming a photosensitive resin on the semiconductor thin film and patterning, and then performing ion implantation using the photosensitive resin as a mask And depositing a refractory metal film on the semiconductor substrate including the entire surface of the semiconductor thin film and the photosensitive resin, and then dissolving the photosensitive resin to form the high temperature on the region of the semiconductor thin film where ion implantation is not performed. The method includes a step of removing the melting point metal film and a step of reacting the refractory metal film with the semiconductor thin film to form a silicide layer by heat treatment. The method of manufacturing a semiconductor device according to claim.