JPS61245552A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of gate withstanding voltage by patterning metallic silicide layer in an upper section, completely coating the surface with an insulating film and patterning poly Si in the lower section of the insulating film and a gate insulating film when patterning a polycide gate. CONSTITUTION:A gate oxide film 4, an N-type CVD poly Si layer 5, MoSi2 6 and CVDSiO2 7 are laminated on an element forming region 2 in a P-type Si substrate 1, a resist pattern 8 is executed, and RIE reaching in poly Si 5 selecting an etching gas is executed. The resist 8 is removed, and the whole surface is coated with CVDSiO2 9. RIE by CHF3 gas is conducted, and poly Si 5 is exposed completely and SiO2 9 is left on the side surface of a stepped section. MoSi2 is annealed at approximately 1,000 deg.C, poly Si 5 is removed selectively through plasma etching by a gas mainly comprising CF4, an eave 10 is formed under the film 9 while selecting the conditions of etching, and the gate oxide film 4 is removed through etching by using CF4 gas, thus completing a polycide gate PG. According to the constitution, the end section of a gate insulating film is not contaminated by a high melting-point metal, thus preventing the deterioration of gate with-standing voltage.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a method for patterning polycide gates.
After patterning the upper metal silicide layer and completely covering the surface of the metal silicide layer pattern with an insulating film, the polycrystalline silicon layer and gate insulating film below are patterned to achieve gate isolation. ! This eliminates contamination of the film by metal ions and active metal compounds, and prevents deterioration of gate breakdown voltage.

[Industrial application field]

The present invention relates to a method for manufacturing an MIS type semiconductor device, and more particularly to a method for forming a polycide gate that prevents deterioration of gate breakdown voltage.

In the manufacturing process of a typical MIS type semiconductor device, after a gate electrode is formed, there are many high-temperature treatment steps such as activation of source/drain regions, vapor phase growth of an insulating film, and flow treatment of an insulating film.

Therefore, as the material for the gate electrode, a conductor having heat resistance that can withstand the above-mentioned high-temperature treatment is selected, and polycrystalline silicon has been widely used in the past.

However, polycrystalline silicon has a drawback in that even when it is doped with impurities at the highest possible concentration, it has a resistivity that is nearly an order of magnitude higher than that of metals.

On the other hand, in Mis-type semiconductor integrated circuit devices (MTSIC) and the like, the gate electrode is often formed long and common to multiple transistors, and when such ICs become highly integrated and the width of the gate electrode becomes narrower, The series resistance of the gate electrode using polycrystalline silicon is extremely high, resulting in a significant delay in operating speed.

Therefore, metal silicides, especially silicides of high-melting point metals such as molybdenum silicide, tungsten silicide, and titanium silicide, have been considered as gate electrode materials that are heat resistant, chemically stable, and have low specific resistance. It is a thing.

High melting point metal silicides generally have a resistivity nearly an order of magnitude lower than polycrystalline silicon, and are very effective materials for improving operating speed. During heat treatment to crystallize the formed high melting point metal silicide layer and lower its resistance, there is a problem in that the high melting point metal diffuses into the gate insulating film, leading to deterioration of gate breakdown voltage.

Therefore, a structure was proposed to prevent deterioration of the gate withstand voltage and reduce the series resistance of the gate electrode.The structure was provided between the gate insulating film and the metal silicide layer to prevent the diffusion of metal into the gate insulating film. with a polycrystalline silicon layer interposed,
This is a so-called polycide gate having a gate electrode with a 2N structure of a polycrystalline silicon layer and a high melting point metal silicide layer.

However, even with polycide gates, there is a tendency for the edges of the gate insulating film to become contaminated with high-melting point metals during the etching process during patterning, resulting in a decrease in gate breakdown voltage.
There is a need for a method for forming patterns.

[Conventional technology]

FIG. 2 (al to tc+ are process cross-sectional views showing a conventional manufacturing method.

In the conventional MTSIC manufacturing process, Fig. 2 fa)
As shown in FIG. A resist pattern 8 having a shape corresponding to the gate electrode pattern is formed on the material layer 6, and using this resist pattern 8 as a mask, the high melting point metal silicide layer 6 is etched by reactive ion etching (RIE) processing. By patterning up to the gate insulating film 4 all at once, a polycide gate in which the gate insulating film 4, the polycrystalline silicon layer 5, and the high melting point metal silicide layer 6 are sequentially laminated as shown in FIG. 2 (C1) is formed.・Pattern PG was formed.

[Problem that the invention seeks to solve]

However, in the conventional polycide gate forming method described above, when the RIE process is performed on the gate insulating film 4, the side surfaces of the high melting point metal silicide layer 6 are simultaneously exposed to the etching gas and react with the etching gas. Therefore, etching
The problem is that a small amount of high melting point metal ions and active compounds are mixed into the gas, and these high melting point metal ions and active compounds infiltrate into the edge E of the patterned gate insulating film 4 and deteriorate the gate breakdown voltage. was occurring.

[Means for solving problems]

FIG. 1 is a process sectional view showing an embodiment of the manufacturing method according to the present invention.

As shown in the figure, the above problem arises when forming an insulated gate pattern in which an insulating film, a polycrystalline silicon layer, and a metal silicide layer are sequentially laminated.
An insulating film 4, a polycrystalline silicon layer 5, a metal silicide layer 6, and a second insulating film 7 are sequentially laminated, with all or a portion of the polycrystalline silicon layer 5 remaining in the thickness direction. The second insulating film 7, the metal silicide layer 6, and the polycrystalline silicon layer 5 are patterned to form a step, and a third insulating film 9 is selectively formed on the side surface of the step, and the third insulating film 9 is exposed. This problem is solved by the manufacturing method according to the present invention, which includes a step of selectively removing the polycrystalline silicon layer 5 and the first insulating film 4 below the polycrystalline silicon layer 5.

[Effect]

That is, in the method of the present invention, ethoching is performed when forming an insulated gate pattern in which a first insulating film (gate insulating film) 4, a polycrystalline silicon layer 5, and a metal silicide layer 6 are sequentially laminated. In the process, when the patterning of the metal silicide layer 6 is completed, the surface of the metal silicide layer pattern is selectively and completely covered with an insulating film 7, and the metal silicide layer 6 is exposed to etching gas. The patterning of the polycrystalline silicon layer 5 and the first insulating film 4 is performed in a state where the polycrystalline silicon layer 5 and the first insulating film 4 are not exposed.

This prevents metal ions and active metal compounds from being contained in the etching gas during patterning of the first insulating film 4. Infiltration of the polycide gate is avoided, and deterioration of the breakdown voltage of the polycide gate is prevented.

〔Example〕

Hereinafter, the present invention will be specifically described by way of examples with reference to process cross-sectional views of FIGS.

FIG. 1 (see al. MO3 with polycide gate by the method of the present invention)
When forming a type semiconductor device, for example, a p-type silicon substrate 1 is used as a semiconductor substrate, and an element formation region 2 is formed on this substrate 1 by selective oxidation or the like.
A field oxide film 3 is formed to separate and expose the elements, and a gate silicon dioxide (SiO□) film 4 is formed as a first insulating film (gate insulating film) 4 on the element formation region 2 by, for example, a thermal oxidation method. The entire surface of this substrate is coated with a thickness of, for example, about 2,000 layers by chemical vapor deposition (CVD).
After forming a polycrystalline silicon layer 5 and imparting conductivity to the polycrystalline silicon layer 5 by introducing n-type impurities into the polycrystalline silicon layer 5 at a high concentration, the polycrystalline silicon layer 5 is sputtered using a normal sputtering method using a silicide target or a metal target and a silicon A molybdenum silicide (MoSiz) layer 6 having a thickness of about 2,000 to 3,000 layers is formed as a high melting point metal silicide layer on the polycrystalline silicon layer 5 by simultaneous sputtering using both targets.
The same substrate to be processed as before is used.

Here, a vapor phase grown film is also used as the first insulating film 4, and furthermore, insulating films other than SiO□ are also applicable.

In addition to the above-mentioned Mo5iz, high melting point metal silicides include tungsten silicide (WSig), titanium silicide (TiStt), and platinum silicide (PtSLz).
, tantalum silicide (TaSig), etc. are also used.

In the method of the present invention, first, an insulating film formed by CVD on the MoSiz layer 6 of the substrate to be processed;
For example, a second insulating film 7 made of a CVD-3 film with a thickness of about 1,000 layers is formed, and a shape corresponding to a gate electrode pattern is formed on this second insulating film 7 by a normal photo process. A resist pattern 8 is formed.

Note that if the insulating film 7 mentioned above has etching selectivity with respect to metal silicide and polycrystalline silicon, the above-mentioned SiO
It is not limited to two films.

FIG. 1 (see C1) Next, using the resist pattern 8 as a mask, active ion etching (RIE) is performed using, for example, trifluoromethane (CHF3) as an etching gas.
The second insulating film 7 is patterned by a process, and then an etching gas is used, for example carbon tetrachloride (CC1).
4) Perform RIB treatment by changing to a halogen-based gas such as
The MoSiz layer 6 is patterned to form a laminated pattern consisting of the MoSiz layer 6 and the second insulating film 7.

At this time, the etching is made to reach into the lower polycrystalline silicon layer 5, so that the patterning of Mo5izli6 is completed.

Refer to FIG. 1(d) Next, after removing the resist pattern 8, a laminated pattern consisting of the MoSi2 layer 6, the second insulating film 7, and the upper layer of the polycrystalline silicon layer 5 is formed on the entire surface of the substrate using the CVD method. A third insulating film 9 made of a CVD-3iO□ film with a thickness of about 1,000 to 2,000 layers is formed on the upper surface, the side surfaces of the stepped portions, and the upper surface of the polycrystalline silicon layer 5 exposed to the outside of the laminated pattern. Form.

Note that the third insulating film 9 is not limited to the above-mentioned SiO□ film as long as it has etching selectivity with respect to the silicide layer 6 and the polycrystalline silicon layer 5; is desirable.

Refer to FIG. 1 (tel) Next, the above third etching process is performed by RIB processing using an etching means, for example, CHh gas, which is predominant in the direction perpendicular to the substrate surface.
The entire surface of the insulating film 9 is etched until the surface of the polycrystalline silicon layer 5 outside the laminated pattern is completely exposed.

After this etching is completed, the second insulating film 7 has an apparently thicker thickness in the direction perpendicular to the substrate surface. A third insulating film 9 having a thickness substantially equal to the formed thickness is left on the side surface of the stepped portion, and the surface of the metal silicide layer pattern, that is, Ho5t, and the layer 6 pattern are covered with the second insulating film 7 and It is completely covered with the third insulating film 9.

FIG. 1 (see fl) Next, in order to crystallize MoS i 2 and lower the resistance of the MoSix layer 6 pattern, the 800 to 10
Annealing treatment is performed at a temperature of about 00°C.

This annealing treatment may be performed in a later step after the gate patterning is completely completed.

Then an isotropic etching means, such as carbon tetrafluoride (C
The exposed portion of the polycrystalline silicon layer 5 is selectively removed by plasma etching using an etching gas containing ut) as a main component.

Here, in order to obtain a predetermined gate length, the MoSix layer 6
Etching conditions are selected such that an undercant portion 10 corresponding to the thickness of the third insulating film 9 is formed under the third insulating film 9 on the side surface of the pattern.

Then, by plasma etching with CF gas,
(Ge) The exposed portion of the Sing film 4 is selectively removed and Mo.
A polycide gate pattern PG in which the Si2 layer 6 is covered with the second insulating film 7 and the third insulating film 9 is completed.

Note that the polycrystalline silicon layer 5 and Ga) Sin.

During plasma etching of the film 4, since the surface of the MoSi2 layer 6 is completely covered by the second insulating film 7 and the third insulating film 9, Mo ions and active Mo compounds are not present in the etching gas. will not be mixed in.

Therefore, the end portions of the patterned gate Sin and the film 4 are not contaminated by the flash ions or active Mo compounds, and deterioration of the gate withstand voltage is prevented.

Furthermore, the polycrystalline silicon layer 5 and the gate 5iOz film 4
The same effect can be obtained even when a wet etching method is used as the isotropic etching means.

Thereafter, an MO3 type semiconductor device having a polycide gate PG as shown in FIG. 1(8) is completed by normal steps.

In the figure, 11 is an n-type source region, 12 is an n-type drain region 13 is an interlayer insulating film, 14 is a contact window, 1
5,1. ．． 6 indicates aluminum wiring.

〔Effect of the invention〕

As described above, according to the present invention, when patterning a polycide gate, the edges of the gate insulating film are not contaminated by the high melting point metal or its active compound, and deterioration of the gate breakdown voltage is prevented.

Therefore, the present invention is effective in improving the performance and manufacturing yield of Mis-type LSIs that are extremely highly integrated using polycide gates.

[Brief explanation of drawings]

FIGS. 1A to 1C are process sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2A to 2C are process sectional views of a conventional method. In, 1 is a p-type silicon substrate (semiconductor substrate), 4 is a gate 5i
O7 film (first insulating film), 5 is a polycrystalline silicon layer, 6 is a molybdenum silicide layer (high melting point metal silicide layer), 7 is a second insulating film, 8 is a resist pattern, 9 is a third Insulating film, PG indicates polycide gate. ') AI- Mi V

Claims (1)

[Claims] A first insulating film (4), a polycrystalline silicon layer (5), a metal silicide layer (6), and a second insulating film (7) are sequentially laminated on a semiconductor substrate (1). forming a step, patterning the second insulating film (7) and the metal silicide layer (6) to form a step, and selectively forming a third insulating film (9) on a side surface of the step; and the exposed polycrystalline silicon layer (5) and the first layer below it.
A method for manufacturing a semiconductor device, comprising the step of selectively removing an insulating film (4).