JPH02260639A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To perform an element isolation favorable to a fine formation by a method wherein an SiO2 layer, an Si3N4 mask layer, a polycrystalline silicon stress buffer layer and an Si3N4 mask layer are deposited one after another on an Si substrate, an opening is formed in the above layers and the exposed surface of the substrate is selectively oxidized. CONSTITUTION:An SiO2 layer 2 is formed on a P-type Si substrate 1 and an Si3N4 mask layer 7, a polycrystalline silicon stress buffer layer 3 and an Si3N4 mask layer 4 are deposited one after another by a prescribed CVD method. A resist mask 60 is provided and an opening is formed in the layers 4, 3 and 7. A B implanted layer 5 is formed by a B ion beam 30. subsequently, the mask 60 is taken off, a field oxide film 16 is formed by a long-time thermal oxidation and the layers 4, 3 and 7 are removed. According to this constitution, the layer 3 prevents the generation of a crystal defect due to a stress concentration on the substrate 1, the layers 7 and 4 prevent a soak of an oxidizer, the lateral spread of a selectively oxidized region is eliminated, the area of an element region is secured as designed and the microminiaturization of the region can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to semiconductor devices, particularly LOGO3 (L
ocal Oxidation of 5ilicon
The present invention relates to a method of manufacturing a semiconductor device having a selective oxide film (field oxide film) using the above technology.

Conventional technology Conventionally, semiconductor IC (Integrated C1rc)
The LOCO3 method is widely adopted as an element isolation technology in the UIT). In this method, a semiconductor substrate is selectively oxidized to form a field SiO□ film between elements.

Although element isolation using the LOCO3 method is a commonly used technology, the formed field s
i0! The membrane has a so-called bird's beak.
beak), which inevitably causes lateral expansion, which causes the field Sin and the width of the film to become unnecessarily larger than the designed width. This narrows the element area, so it is necessary to design the element area wider in advance to account for the bird's beak, which prevents miniaturization as elements become more highly integrated. .

On the other hand, there are various names for the above-mentioned LOCO3 method, but one of them is a silicon substrate that is mainly caused by stress generated during selective oxidation (that is, stress is generated because oxidation is accompanied by volumetric expansion). There are ways to avoid crystal defects in (semiconductor materials). That is, for example, a polysilicon layer or the like is provided in order to absorb, disperse, and relieve stress during selective oxidation. Hereinafter, an example of the manufacturing process will be described in detail with reference to FIG. 3.

First, as shown in FIG. 3A, 3i0. FJ2 was grown, and then CVD (Chemical Vapor De
A polysilicon layer (stress buffering material) 3 and a 313Na layer 4 are sequentially formed depending on the position.

Next, as shown in FIG. 3B, after covering with a predetermined pattern of, for example, a photoresist 5G as a mask, the St, N, layer 4 and polysilicon layer 3 in a predetermined region are etched away by, for example, plasma etching technique. Then, as shown in FIG. 3C, using the photoresist 50 as a mask, for example, a boron ion beam 30 for channel bombardment is implanted only into a predetermined region to form a boron implanted layer 5.

Next, as shown in FIG. 30, after removing the photoresist 50, the surface of the substrate 1 in a predetermined area is selectively oxidized by long-term thermal oxidation to form a field Sin for element isolation.
, forming the film 6. Thereafter, 5iz etching using a prescribed etching solution (e.g. phosphoric acid and plasma etching technique)
Na layer 4 and polysilicon layer 3 are sequentially removed by etching as shown in FIG. 3E. If, for example, a gate electrode or the like is to be formed subsequently, the 5-int layer 2 is removed by etching, and then a new gate oxide film is formed.

As a result of various studies conducted by the present inventors regarding the TOCOS method using the above-mentioned manufacturing process, various problems thereof are shown below.

(1), that is, when selective oxidation is performed in FIG. It also oxidizes silicon, so the selective oxidation region W is horizontal! As a result, the element area is narrowed (that is, the extra area such as the above-mentioned spread area must be taken into consideration in advance), which is very disadvantageous for device miniaturization.

(2) Furthermore, since the polysilicon layer 3 is polycrystalline and a very strong stress is applied to the polysilicon layer 3 during selective oxidation, the oxidation may occur in the form of grains, as shown in an enlarged view in FIG. 3D. Further, some silicon grains of the polysilicon N3 may be oxidized from the grain boundary B, and silicon grains L surrounded by an oxide film H may be generated.

On the other hand, as shown in FIG. 3E, Si, N.

When removing the layer 4 and the polysilicon layer 3 by etching, the oxide film grown on the Si3N4 layer 4 during selective oxidation, the natural oxide film on the polysilicon layer 3, and the oxide film H are removed.
It is necessary to remove it by etching. In this oxide film removal process, if the etching progresses through the oxide film H to the oxide film 2, a small hole may be generated from the polysilicon layer 3 to the silicon substrate 1 as a result. If such a narrow area exists, the silicon substrate 1 will be damaged through this narrow area when the polysilicon layer 3 is etched away. And this is very detrimental to the reliability of the device.

Furthermore, when silicon grains L surrounded by grain-shaped non-uniform oxide film portions G and oxide films H are generated, after removing the 5i3Na layer 4 and the polysilicon layer 3 by etching, as shown in an enlarged view in FIG. 3E, Field SiO□ film 6
In the bird's beak portion, an uneven shape C following the shapes of grains G and 1 is generated. The presence of such fine irregularities is extremely disadvantageous to the reliability of the device, such as a breakdown voltage failure of the gate oxide film in the active region.

In addition, as another method, the so-called S
Sealed Interface Lo
As shown in the figure, this method is a method in which a SiN4 layer 7 is directly provided on a silicon substrate 1 in order to avoid the occurrence of bird's beaks, etc. in the above-mentioned LOCO3 method. . Usually, the exposed surface of the silicon substrate 1 in FIG. 4 is selectively oxidized by long-term thermal oxidation, but at this time, the above-mentioned Si, N, and layer 7 can prevent the oxidation from progressing in the lateral direction. Note that 12 in the figure is the silicon substrate 1.
This is a SiO□ layer formed by low-pressure CVD or the like to alleviate stress concentration on the substrate.

However, according to the above-mentioned method, when removing the above-mentioned layers by etching after completion of selective oxidation, in particular, the silicon substrate 1
Etching of the upper 5izNa layer 7 must be performed without damaging the substrate 1, and its control is very difficult. That is, since it is very difficult to control the etching rate, etc., damage to the substrate 1 is likely to occur during etching of the Si, N, and layers 7. This also poses a serious problem for device reliability.

C. 1. Purpose of the Invention An object of the present invention is to provide a highly reliable method of manufacturing a semiconductor device that can perform element isolation that is advantageous for miniaturization of a semiconductor device.

20 Structure of the Invention That is, the present invention includes the step of forming an oxide layer on one main surface of a semiconductor substrate; properties) and a heat-resistant first mask material layer (for example, 5t3N, layer 7 described later).
); Forming a stress buffering material layer (for example, polysilicon layer 3 to be described later) on this first mask material layer (for example, 5j3Na layer 7 to be described later); a step of forming a second mask material layer (for example, Si3N4 layer 4, described below) having oxidation resistance and heat resistance on the polysilicon layer 3 (described later); 7) forming a mask by respectively buttering the stress buffering material layer (for example, polysilicon layer 3 described later) and the second mask material layer (for example, Si3N4 layer 4 described later); selectively oxidizing the surface of the semiconductor substrate existing in areas where the semiconductor substrate is not present.

E, Example The present invention will be explained in detail below.

The method according to this embodiment will be explained with reference to FIG. 1. First, as shown in FIG.
Furthermore, in the same manner as the example shown in FIG. 3, a 5izNs layer 7 (first
mask material layer: for example, thickness of about 50 to 100 people),
Polysilicon layer 3 (stress buffering material layer: for example, thickness 500
The Si3N4 layer 4 (second mask material layer: for example, thickness of about 1000 to 3000 layers) is formed in sequence.

Next, the steps in FIGS. 1B to 1E are as shown in FIGS. 3B to 1E described above.
Since the process is almost the same as that of FIG. 3ε, the explanation will be omitted (however, in the example of FIG. 3, the 5ilN4 layer 7 is not formed, so no etching is required for that purpose).
Note that 60 in the figure is, for example, a photoresist as a mask.

FIG. 2 shows an example in which the method described above is applied to an N-channel MOS transistor.

In this N-channel MOS transistor, each element (in this example, between adjacent N-channel MOS transistors) is isolated on the P-type silicon substrate 1 by the field Si0g film 16 formed as described above. Each N-channel MOS transistor has a substrate 1
N-type diffusion region (source or drain)
10 and a gate electrode 12 formed on the substrate 1 with a gate oxide film 11 interposed therebetween, forming a transfer gate. In the figure, 13 is an insulating layer, 14 is a metal wiring layer such as A1, and 15 is a PSG (Phosphosi
It is an oxide film (protective film) such as licateglass).

As explained above, according to the method of manufacturing a semiconductor device according to this embodiment, as shown in FIG. St, N, as a mask material to sandwich the polysilicon layer 3 as a material to prevent oxidation etc.
T! A and 7 are formed respectively, so that the horizontal spread of the selective oxidation region due to oxidation of the Si layer 2 and the polysilicon layer 3 as shown in FIG.
.

This can be prevented by layer 7. Therefore, the width W, etc. of the selective oxidation region shown in FIG. 3E is changed to the width W! as shown in FIG. 1E. Since it can be made smaller, it is very advantageous for device miniaturization.

Furthermore, since the Si3N4 layer 7 is present under the polysilicon layer 3, non-uniform oxidation of the polysilicon layer 3 during selective oxidation as described above can be prevented.

Therefore, it is possible to prevent unevenness from occurring in the field Sin and the bird's beak portion of the film, and furthermore, when removing the polysilicon layer 3 etc. by etching, it is possible to prevent the substrate 1 etc. from being damaged due to the non-uniform oxidation as described above (i.e. In FIG. 30, the field 5i02 film 6 is non-uniformly oxidized, so that the above-mentioned fine holes are formed in the bird's beak portion, and the etching solution used to remove the polysilicon layer 3 by etching removes the fine holes. Even if a small hole like the one described above were to occur, since there is a 5izNn layer 7, there is no need to pass through the Sin layer 2 and damage the substrate 1. It does not reach the silicon substrate 1. As a result, the polysilicon layer 3 can be easily etched away using the Si, N4 layer 7 as a mask.Also, since the polysilicon N3 is formed as a stress buffering material layer, Crystal defects and the like due to stress concentration on the substrate 1 can be prevented.

Furthermore, as in the example of FIG.
Instead of forming the N43 layer 4, Si and N are formed on the Sing layer z formed on the substrate 1 as in this example.

Since the layer 7 is formed, when etching the S 1ffN4 N1, the etching can be easily performed using the Sin layer 2 as a mask without damaging the substrate 1, as in the example shown in FIG. Furthermore, in this example, the SiO layer 2 on the substrate 1 can be left as a passivation film or the like if necessary.

Further, according to this example, as described above, the S L3N is sandwiched between the polysilicon layer 3 as a stress buffer material
4 [4 and 7], there is no need to consider properties such as oxidation resistance of the stress buffering material itself. Therefore, the degree of freedom in selecting a material as a stress buffering material increases, which is advantageous in the device manufacturing process.

Although the present invention has been illustrated above, the above-described examples can be further modified based on the technical idea of the present invention.

For example, a layer of Sin formed using a gas phase reaction may be used as the above-mentioned stress buffering material, and other materials having an appropriate structure such as amorphous or polycrystalline may also be used. . In addition, the above-mentioned oxide layer, Si, N,
The method of forming the layer and the etching method may be varied in various ways, such as applying CVD instead of thermal oxidation, or selectively employing wet etching or dry etching. Further, the material of each layer, the material structure, the conductivity type of the semiconductor region, etc. are not limited to those described above.

Note that the present invention can be applied to various semiconductor devices other than those described above that have field oxide films.

1. Effects of the Invention As described above, the present invention includes a first mask material layer having oxidation resistance and heat resistance, a stress buffering material layer on an oxide layer,
After sequentially forming a second mask material layer having oxidation resistance and heat resistance, and patterning the first and second mask material layers and the stress buffering material layer, respectively, to form a mask, Since selective oxidation is performed on the surface of the semiconductor substrate existing in the area without a mask, the stress buffering material layer can prevent crystal defects etc. due to concentration of stress on the semiconductor substrate, and Its presence prevents penetration of the oxidizing agent, eliminates unnecessary oxidation (lateral expansion of the selectively oxidized region, etc.), and ensures a sufficient area of the element region as designed.

Therefore, it is possible to realize miniaturization that meets the demand for high integration.

Further, each of the above-mentioned layers serves as a mask during etching, etc., and the etching can be easily performed without damaging the semiconductor substrate.

[Brief explanation of drawings]

1 and 2 show embodiments of the present invention, and FIGS. 1A, 1B, tC, 1D, and 1E show a method for manufacturing a semiconductor device including a field oxide film. 2 is a sectional view showing an example in which the present invention is applied to an N-channel MO3I-transistor, and FIGS. 3 and 4 show a conventional example.
3B, 3C, 3D, and 3E are cross-sectional views showing the main steps of a conventional method for manufacturing a semiconductor device including a field oxide film, and FIG. 4 is a cross-sectional view showing the conventional 5ILO method. It is. In addition, in the reference numerals shown in the drawings, 1. P-type silicon substrate 2.
12-・----S i O, layer-1---
---Polysilicon layer St, N, layer (second mask material layer) 16...--Field 5in2 film Si3N, layer (first mask material layer)

Claims (1)

[Claims] 1. Step of forming an oxide layer on one main surface of the semiconductor substrate; Step of forming a first mask material layer having oxidation resistance and heat resistance on this oxide layer; This first mask forming a stress buffering material layer on the material layer; forming a second mask material layer having oxidation resistance and heat resistance on the stress buffering material layer; Manufacturing a semiconductor device comprising: forming a mask by respectively patterning a stress buffering material layer and the second mask material layer; and selectively oxidizing the surface of the semiconductor substrate existing in a region without the mask. Method.