JPH08316475A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To reduce a junction leakage from impurity diffused layers, to reduce the resistance of a gate electrode wiring and to improve the dielectric strength of a gate insulating film in a semiconductor device of a salicide structure. CONSTITUTION: Titanium silicide layers 12a and 12b are respectively formed on the upper surface of a gate electrode 4 and the surfaces of impurity diffused layers 11 and at the same time, a titanium silicide layer 7 is formed also on the upper parts of the side surfaces of the electrode 4. As this layer 7 does not come into contact with a gate insulating film 3, it is not generated that titanium is diffused in the film 3 and the dielectric strength of the film 3 is deteriorated. Moreover, the electrode 4 is reduced in resistance by the component of the layer 7, the thickness of the layers 12b can be made thin and a junction leakage from the layers 11 is hardly eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a salicide structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In order to increase the degree of integration of LSI, it is necessary not only to reduce the lateral dimension but also the vertical dimension. As one of the means for reducing the vertical dimension, there is a technique of making the junction depth of an impurity diffusion layer such as a source / drain region of a MOS transistor shallow, and therefore, in recent years, impurities deposited on a semiconductor substrate have been used. A method of forming a shallow junction in a semiconductor substrate by thermally diffusing impurities from a containing insulating film or an impurity-containing conductive film is used.

However, if the junction depth of the impurity diffusion layer on the surface of the semiconductor substrate such as the source / drain region is made shallow (thin), the resistance of the impurity diffusion layer becomes high and the operation speed of the semiconductor device is lowered. . Therefore, it has been proposed to form a metal silicide layer on the surface of the impurity diffusion layer to reduce the resistance of the source / drain regions. For example, in order to form this metal silicide layer, after depositing a metal film on the surface of the silicon substrate, heat treatment is performed to react the silicon of the silicon substrate with the metal film, and the metal silicide is formed at the interface between the silicon substrate and the metal film. Grow layers. In particular, in recent years, a so-called salicide process has been performed in which a metal silicide layer is formed on a gate electrode made of a polycrystalline silicon film to reduce the wiring resistance of the gate electrode. A method of manufacturing the salicide structure MOS transistor will be described with reference to FIG.

First, as shown in FIG. 6A, after a thermal oxide film 22 is formed on a P-type silicon substrate 21, a polycrystalline silicon film containing impurities is formed on the thermal oxide film 22 by a CVD method. To do. Then, the polycrystalline silicon film is etched by a photolithography technique to form a gate electrode 23 made of the polycrystalline silicon film. After that, an N-type impurity diffusion layer 27 having a low impurity concentration is formed on the surface of the silicon substrate 21 on both sides of the gate electrode 23.

Next, as shown in FIG. 6B, a silicon oxide film is formed on the entire surface of the silicon substrate 21 by the CVD method and is etched back to form a sidewall oxide film 24 made of a silicon oxide film. To form. At this time, the thermal oxide film 22 existing on the silicon substrate 21 in the region other than under the gate electrode 23 is simultaneously removed by etching. After that, the silicon substrate 2 on both sides of the gate electrode 23
An N-type impurity diffusion layer 28 having a high impurity concentration is formed on the surface 1.

Next, as shown in FIG. 6C, a metal film 25 is formed on the entire surface of the silicon substrate 21.

Next, as shown in FIG. 6D, the silicon substrate 21 is heat-treated to react silicon and metal, and the metal silicide layer 26a is formed on the gate electrode 23.
And the metal silicide layer 26b is formed on the impurity diffusion layer 28 of the silicon substrate 21. Then, the metal film 25 that has not been silicided is removed by wet etching. Through the above steps, a salicide MOS transistor is formed.

In the manufacturing method described above with reference to FIG. 6, the metal silicide layer 26a on the upper portion of the gate electrode 23 is formed.
And the formation of the metal silicide layer 26b on the impurity diffusion layer 28 of the silicon substrate 21 are performed in the same heat treatment step. Therefore, these two metal silicide layers 26a,
The film thicknesses of 26b are equal. On the other hand, the metal silicide layer 26b formed in the impurity diffusion layer 28 of the silicon substrate 21
Must be formed thinner than the junction depth of the impurity diffusion layer 28 in order to suppress the junction leak, and cannot be made thicker than about 0.10 μm due to miniaturization of the semiconductor element. On the other hand, the metal silicide layer 26a formed on the gate electrode 23 is desired to have a film thickness as large as possible in order to reduce the wiring resistance of the gate electrode 23.

In order to satisfy the requirements of both of these, the two metal silicide layers 26a and 26b may be formed in separate steps, and an example thereof will be described with reference to FIG.

First, as shown in FIG. 7A, after forming a thermal oxide film 32 on a P-type silicon substrate 31, a polycrystalline silicon film containing impurities is formed on the thermal oxide film 32 by a CVD method. To do. Then, the polycrystalline silicon film is etched by a photolithography technique to form a gate electrode 33 made of the polycrystalline silicon film. After that, the N-type impurity diffusion layer 36 is formed on the surface of the silicon substrate 31 on both sides of the gate electrode 33.

Next, as shown in FIG. 7B, a metal film 34 is formed on the entire surface of the silicon substrate 31.

Next, as shown in FIG. 7C, the silicon substrate 31 is heat-treated to react the silicon with the metal to form the metal silicide layer 35 on the upper surface and the side surface of the gate electrode 33. . After that, the metal film 34 which has not been silicided is removed by wet etching. Then, by performing the same process as that of FIG. 6 thereafter, a silicide layer having a smaller film thickness than the metal silicide layer 35 is formed on the impurity diffusion layer 36. As a result, the thickness of the metal silicide layer on the gate electrode 33 is relatively large, the resistance of the gate electrode is reduced, and the impurity diffusion layer 3 is formed.
A salicide structure MOS transistor in which the thickness of the metal silicide layer 6 is relatively small and junction leakage does not occur is formed.

In the example shown in FIG. 7, the gate electrode 3
3 and the impurity diffusion layer 36 are prevented from being short-circuited via the silicide layer 35, in the step shown in FIG.
All of the thermal oxide film 32 existing above is not removed by etching, but a part thereof is left.

[0014]

However, according to the method of manufacturing the semiconductor device shown in FIG. 7, as shown in FIG. 7C, the metal silicide layer 35 covering the side surface of the gate electrode 33 is heated at its lower end 35a. In order to make contact with the oxide film 32, a metal silicide layer 35 is formed by heat treatment in a later step.
Therefore, there is a problem that the refractory metal forming this layer diffuses into the thermal oxide film 32, and as a result, the withstand voltage of the thermal oxide film 32, which is the gate insulating film, decreases.

Therefore, an object of the present invention is to use a salicide structure to reduce the resistance of a gate electrode and to suppress junction leakage in an impurity diffusion layer, and in a semiconductor device of high operating speed, from a metal silicide layer to a gate insulating film. It is an object of the present invention to provide a semiconductor device having excellent withstand voltage and high reliability by preventing metal diffusion and a manufacturing method thereof.

[0016]

In order to achieve the above object, a semiconductor device of the present invention comprises a gate insulating film formed on a silicon substrate, a gate electrode formed on the gate insulating film, and In a semiconductor device having an impurity diffusion layer formed on the surface of the silicon substrate on both sides of a gate electrode and at least a part of which is a metal silicide layer,
The gate electrode has a metal silicide layer which is not in contact with the gate insulating film on at least the side surface thereof.

In one aspect of the present invention, a gate insulating film formed on a silicon substrate, a first conductive layer formed on the gate insulating film, and a first conductive layer formed on the first conductive layer. A second conductive layer containing silicon and a metal silicide layer formed on the upper side surface and the upper surface of the second conductive layer are provided.

The semiconductor device manufacturing method of the present invention is
A first step of forming a first insulating film on the surface of a silicon substrate, a second step of forming a polycrystalline silicon film on the first insulating film, and a second step of forming a polycrystalline silicon film on the polycrystalline silicon film. Second step of forming the second insulating film, patterning the second insulating film into a predetermined shape, and upper side of the polycrystalline silicon film in a region other than under the second insulating film left by this patterning. And a fourth step of patterning the polycrystalline silicon film into a convex shape by etching, a fifth step of forming a first metal film on the silicon substrate, and a heat treatment to form the first metal film. A sixth step of converting the surface portion of the polycrystalline silicon film which is in contact with the metal silicide into metal silicide, and removing the first metal film which has not been metal-silicided, and then performing the process in the region other than under the second insulating film. Polycrystalline silicon film And a surface step of removing the metal-silicided portion to form a gate electrode having a metal silicide layer on the upper side surface, and removing the first insulating film, and then forming a gate electrode on the silicon substrate. Eighth step of forming an insulating film of No. 3 and etching the third insulating film and the first insulating film to form a sidewall insulating film made of the third insulating film on the gate electrode. And a ninth step of exposing the silicon substrate on both sides of the gate electrode; and a step of forming a second metal film on the silicon substrate and then performing a heat treatment to contact the second metal film. And a tenth step of converting the surface portion of the silicon substrate into a metal silicide, and an eleventh step of removing the second metal film which has not been converted into a metal silicide.

[0019]

According to the present invention, since the gate electrode and the impurity diffusion layer have the salicide structure provided with the metal silicide layer, the resistance of the gate electrode and the impurity diffusion layer can be made low and the high speed operation is possible. is there. In addition, since the metal silicide layer formed on the upper side surface of the gate electrode contributes to lowering the resistance of the gate electrode, the film thickness of the metal silicide layer of the impurity diffusion layer formed at the same time as the metal silicide layer on the upper surface of the gate electrode. Therefore, even if the semiconductor device is miniaturized by reducing the junction depth of the impurity diffusion layer, a junction leak hardly occurs. Further, since the metal silicide layer is formed on the side surface of the gate electrode so as not to contact the gate oxide film, the metal forming the metal silicide layer does not diffuse from the metal silicide layer to the gate oxide film. Therefore, it is possible to obtain a highly reliable semiconductor device in which the withstand voltage of the gate oxide film does not deteriorate.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

First, a first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1A, a P-type silicon substrate 1 is separated into elements by a LOCOS method, a field oxide film 2 is formed, and then an element formation region surrounded by the field oxide film 2 is formed. 5 to 2 film thickness on the surface of silicon substrate 1
A gate oxide film 3 of about 0 nm is formed by thermal oxidation.
Then, a film thickness of 100 to 300 containing impurities is formed on the entire surface of the gate oxide film 3 by the chemical vapor deposition method (CVD method).
A polycrystalline silicon film 4 having a thickness of about nm is formed. After a while
A film thickness of 15 is formed on the entire surface of the polycrystalline silicon film 4 by the CVD method.
A silicon oxide film 5 having a thickness of 0 to 300 nm is formed.

Next, as shown in FIG. 1B, by photolithography using a photoresist (not shown) as a mask, all the silicon oxide film 5 in the region where the gate electrode is not formed and the polycrystalline silicon in this region are formed. The upper side of the film 4 is removed by etching. As a result, the silicon oxide film 5 and the polycrystalline silicon film 4 in the entire region where the gate electrode is formed, and the film thickness 3 in the region where the gate electrode is not formed are formed.
The polycrystalline silicon film 4 having a thickness of 0 to 100 nm remains, and the polycrystalline silicon film 4 is patterned in a convex shape.

Next, as shown in FIG. 1C, a film thickness of 30 to 50 nm is formed on the entire surface of the silicon substrate 1 by the sputtering method.
A titanium film 6 which is a high melting point metal is formed.

Next, as shown in FIG. 2A, a temperature of 50
Heat treatment is performed at 0 to 900 ° C. for 5 to 60 seconds to form a titanium silicide layer 7 at the interface between the polycrystalline silicon film 4 and the titanium film 6. Then, the titanium film 6 that has not been silicided is removed by wet etching.

Next, as shown in FIG. 2B, anisotropic etching is performed by using the silicon oxide film 5 remaining on the polycrystalline silicon film 4 as a mask, and titanium silicide existing except under the silicon oxide film 5. Layer 7 and polycrystalline silicon film 4 are removed. As a result, the polycrystalline silicon film 4 is processed into the shape of the gate electrode, and the titanium silicide layer 7 remains on the upper left and right side surfaces of the gate electrode 4. Then, after removing the silicon oxide film 5, the gate electrode 4 is removed.
Impurity diffusion layers 10 having a low impurity concentration are formed on the surface of the silicon substrate 1 on both sides of.

Next, as shown in FIG. 2C, a silicon oxide film having a film thickness of about 150 to 300 nm is formed on the entire surface of the silicon substrate 1 by the CVD method, and this silicon oxide film is etched back by anisotropic etching. By doing so, the sidewall oxide film 8 of the gate electrode 4 is formed. By this etch back, the gate oxide film 3 in the region other than under the gate electrode 4 is removed, and the surface of the silicon substrate 1 is exposed in this region. Then, the impurity diffusion layers 11 having a high impurity concentration are formed on the surface of the silicon substrate 1 on both sides of the gate electrode 4.

Next, as shown in FIG. 3A, a film thickness of 30 to 100 n is formed on the entire surface of the silicon substrate 1 by the sputtering method.
A titanium film 9 having a high melting point of about m is formed.

Next, as shown in FIG. 3B, a temperature of 50
Heat treatment is performed at 0 to 900 ° C. for 5 to 60 seconds, and a titanium silicide layer 12a is formed on the interface between the gate electrode 4 and the titanium film 9.
And the titanium silicide layer 12b is formed at the interface between the impurity diffusion layer 11 and the titanium film 9. After that, the titanium film 9 which is not silicided is removed by wet etching.

The MOS transistor obtained by the above steps has a part of the gate electrode 4 and the impurity diffusion layer 11.
Part of which has a salicide structure composed of titanium silicide layers 7, 12a, 12b, the gate electrode 4 and the impurity diffusion layer 11 can have a low resistance and can operate at high speed. Further, the impurity diffusion layer 11 formed at the same time as the titanium silicide layer 12a on the upper surface of the gate electrode 4 by the amount that the titanium silicide layer 7 formed on the upper left and right side surfaces of the gate electrode 4 contributes to the lowering of the resistance of the gate electrode 4. Since it is possible to reduce the film thickness of the titanium silicide layer 12b in the upper part of the above, even if the junction depth of the impurity diffusion layer 11 is reduced to miniaturize the MOS transistor, a junction leak hardly occurs. Further, since the titanium silicide layer 7 is formed only on the upper left and right side surfaces of the gate electrode 4 and is not in contact with the gate oxide film 3, titanium does not diffuse from the titanium silicide layer 7 to the gate oxide film 3. Therefore, it is possible to obtain a highly reliable MOS transistor in which the withstand voltage of the gate oxide film 3 does not deteriorate.

Next, a second embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 4A, the gate oxide film 3 is formed on the surface of the P-type silicon substrate 1 by thermal oxidation. Then, a polycrystalline silicon film containing impurities is formed on the entire surface of the gate oxide film 3 by the CVD method. Then, the polycrystalline silicon film is patterned by photolithography to form the lower portion 4a of the gate electrode.
Then, the impurity diffusion layer 10 having a low impurity concentration is formed on the surface of the silicon substrate 1 on both sides of the lower portion 4a of the gate electrode.

Next, as shown in FIG. 4B, a silicon nitride film is formed on the entire surface of the silicon substrate 1 by the CVD method,
This silicon nitride film is etched back by anisotropic etching to form a sidewall oxide film 8a under the gate electrode lower portion 4a. Note that the gate oxide film 3 in the region other than below the lower portion 4a of the gate electrode is not removed by this etch back.

Next, as shown in FIG. 4C, a polycrystalline silicon film is selectively grown on the lower gate electrode 4a to form a fan-shaped upper gate electrode 4b. After that, an impurity diffusion layer 11 having a high impurity concentration is formed on the surface of the silicon substrate 1 on both sides of the gate electrode lower portion 4a by ion implantation. At this time, N-type impurities are added to the fan-shaped gate electrode upper portion 4b. Then, after removing the gate oxide film 3 in the region other than under the gate electrode lower portion 4a, a titanium film 9 which is a refractory metal is formed on the entire surface of the silicon substrate 1.

Next, as shown in FIG. 4 (d), a temperature of 50
Heat treatment is performed at 0 to 900 ° C. for 5 to 60 seconds to form a titanium silicide layer 12a at the interface between the gate electrode upper portion 4b and the titanium film 9, and at the interface between the impurity diffusion layer 11 and the titanium film 9. 12b is formed.
After that, the titanium film 9 which is not silicided is removed by wet etching.

The MOS transistor obtained by the above steps has a salicide structure in which a part of the gate electrode upper part 4b and a part of the impurity diffusion layer 11 have titanium silicide layers 12a and 12b. The gate electrode 4 including the upper and lower portions 4a and 4b and the impurity diffusion layer 11 can have low resistance and can operate at high speed. Further, the titanium silicide layer 12a formed on the upper surface and the upper side surface of the gate electrode 4 and having a large cross-sectional area contributes to the reduction of the resistance of the gate electrode 4, so that the titanium silicide layer on the impurity diffusion layer 11 formed at the same time is formed. Layer 1
The film thickness of 2b can be reduced, and even if the junction depth of the impurity diffusion layer 11 is reduced to miniaturize the MOS transistor, a junction leak hardly occurs. Further, since the titanium silicide layer 12a is formed only on the surface of the gate electrode upper portion 4b and is not in contact with the gate oxide film 3, titanium does not diffuse from the titanium silicide layer 12a to the gate oxide film 3. Therefore, it is possible to obtain a highly reliable MOS transistor in which the withstand voltage of the gate oxide film 3 does not deteriorate.

Next, a third embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 5A, an insulating film 13 is formed on the surface of the P-type silicon substrate 1, and then a groove 13a reaching the silicon substrate 1 is selectively formed in the insulating film 13. To do. Thereafter, the gate oxide film 3 is formed on the surface of the silicon substrate 1 at the bottom of the groove 13a by thermal oxidation. Further, a polycrystalline silicon film 4c containing impurities is formed on the entire surface of the gate oxide film 3 by the CVD method to fill the groove 13a. After that, the photoresist 14 is patterned into a predetermined shape, and at least the groove 13 is formed by selective etching using the photoresist 14 as a mask.
The polycrystalline silicon film 4c of a is left to form a gate electrode 4c having a T-shaped cross section. As a result, the gate electrode 4c
The insulating film 13 remains below the upper left and right side surfaces. Thereafter, the impurity diffusion layer 11 having a high impurity concentration is formed on the surface of the silicon substrate 1 on both sides of the gate electrode 4c.

Next, as shown in FIG. 5B, the photoresist 14 is removed, and then the titanium film 9 is formed on the entire surface of the silicon substrate 1.

Next, as shown in FIG. 5C, the silicon substrate 1 is heat-treated at a temperature of 500 to 900 ° C. for 5 to 60 seconds, and the titanium silicide layer 12a is formed at the interface between the gate electrode 4c and the titanium film 9. And the titanium silicide layer 12b is formed on the interface between the impurity diffusion layer 11 and the titanium film 9.
To form. At this time, since the gate electrode 4c has a T-shaped cross section, the titanium silicide layer 12a is formed not only on the upper surface of the gate electrode 4c but also on the upper portions of the left and right side surfaces. On one side, the titanium silicide layer 12a is not formed because the insulating film 13 remains below the upper left and right side surfaces of the gate electrode 4c. After that, the titanium film 9 which is not silicided is removed by wet etching.

The MOS transistor obtained by the above steps has a structure including a part of the gate electrode 4c and the impurity diffusion layer 1.
Since part of 1 has a salicide structure composed of titanium silicide layers 12a and 12b, the resistance of the gate electrode 4c and the impurity diffusion layer 11 can be made low, and high-speed operation is possible. Further, the titanium diffusion layer 12a formed in the shape of a side wall on the upper left and right side surfaces of the gate electrode 4c contributes to the reduction of the resistance of the gate electrode 4c.
Since the film thickness of the titanium silicide layer 12b above 1 can be reduced, even if the junction depth of the impurity diffusion layer 11 is reduced to miniaturize the MOS transistor, a junction leak hardly occurs. Further, since the titanium silicide layer 12a is formed on the insulating film 13 having a relatively large thickness and is not in contact with the gate oxide film 3, titanium does not diffuse from the titanium silicide layer 12a to the gate oxide film 3. Therefore, it is possible to obtain a highly reliable MOS transistor in which the withstand voltage of the gate oxide film 3 does not deteriorate.

In the first to third embodiments described above, the titanium film is used to form the titanium silicide layer.
These silicide layers may be formed by forming a film made of a refractory metal such as o, W, Ta, and Co.

As described above, in the MOS transistor of this embodiment, the thermal oxide film formed on the element forming region of the silicon substrate, the polycrystalline silicon film containing impurities formed on the thermal oxide film, and the polycrystalline silicon film Since the gate electrode made of the titanium silicide layer is provided on the upper surface and the upper side surface of the polycrystalline silicon film, the resistance of the wiring of the gate electrode can be reduced regardless of the junction depth of the impurity diffusion layer.

[0044]

According to the present invention, in a semiconductor device having a salicide structure, the junction leak can be reduced and the resistance of the gate electrode wiring can be reduced regardless of the junction depth of the impurity diffusion layer. Speed is improved. Moreover, since the dielectric strength of the gate insulating film is improved, a highly reliable semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a salicide structure MOS according to a first embodiment of the present invention.
It is sectional drawing which shows a transistor in order of a manufacturing process.

FIG. 2 is a salicide structure MOS according to a first embodiment of the present invention.
It is sectional drawing which shows a transistor in order of a manufacturing process.

FIG. 3 is a salicide structure MOS according to a first embodiment of the present invention.
It is sectional drawing which shows a transistor in order of a manufacturing process.

FIG. 4 is a salicide structure MOS according to a second embodiment of the present invention.
It is sectional drawing which shows a transistor in order of a manufacturing process.

FIG. 5 is a salicide structure MOS according to a third embodiment of the present invention.
It is sectional drawing which shows a transistor in order of a manufacturing process.

FIG. 6 is a cross-sectional view showing a conventional salicide structure MOS transistor in the order of manufacturing steps.

FIG. 7 is a cross-sectional view showing a conventional salicide structure MOS transistor in the order of manufacturing steps.

[Explanation of symbols]

 1 Silicon Substrate 3 Gate Oxide Film 4 Polycrystalline Silicon Film (Gate Electrode) 6, 9 Titanium Film 7, 12a, 12b Titanium Silicide Layer 8 Sidewall Oxide Film

Claims (3)

[Claims] 1. A gate insulating film formed on a silicon substrate, a gate electrode formed on the gate insulating film, and formed on the surface of the silicon substrate on both sides of the gate electrode, at least a part of which is metal. A semiconductor device having an impurity diffusion layer formed of a silicide layer, wherein the gate electrode includes a metal silicide layer which is not in contact with the gate insulating film on at least a side surface thereof. 2. A gate insulating film formed on a silicon substrate, a first conductive layer formed on the gate insulating film, and a second silicon-containing film formed on the first conductive layer. And a metal silicide layer formed on the upper side surface and the upper surface of the second conductive layer. 3. A first step of forming a first insulating film on a surface of a silicon substrate, a second step of forming a polycrystalline silicon film on the first insulating film, and the polycrystalline silicon. A third step of forming a second insulating film on the film; patterning the second insulating film into a predetermined shape; A fourth step of etching the upper side of the crystalline silicon film to pattern the polycrystalline silicon film in a convex shape; a fifth step of forming a first metal film on the silicon substrate; A sixth step of converting the surface of the polycrystalline silicon film in contact with the first metal film into a metal silicide, and removing the first metal film which has not been metal-silicided, and then removing the second insulating film Areas other than the above A seventh step of removing the crystalline silicon film and the metal silicided portion of the surface thereof to form a gate electrode having a metal silicide layer on the upper side surface; and the step of removing the first insulating film and then the silicon. An eighth step of forming a third insulating film on a substrate, and a sidewall formed of the third insulating film on the gate electrode by etching the third insulating film and the first insulating film Forming an insulating film and exposing the silicon substrate on both sides of the gate electrode;
And a tenth step of forming a second metal film on the silicon substrate and then subjecting the surface of the gate electrode and the silicon substrate in contact with the second metal film to a metal silicide by heat treatment. And an eleventh step of removing the second metal film that has not been metal-silicided.