JP2008244032A - Semiconductor apparatus and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus wherein an interlayer insulating film and/or a metal film for wiring etc. having tensile stress are formed on a semiconductor substrate, and the warpage of a wafer can be suppressed. <P>SOLUTION: This semiconductor apparatus comprises the semiconductor substrate 10 in which a semiconductor device is formed, and one or a plurality of layers of metal films 16a, 16b and 18 deposited on the semiconductor substrate 10. A stress relaxation film 17 for relaxing a wafer warpage amount is provided on either one side of the lower layer side and the upper layer side of a first wiring metal film 18 which is one wiring metal film from among one or a plurality of layers of wiring metal films whose deposition makes the absolute value of the wafer warpage amount maximum, the stress relaxation film 17 having compressive stress, the first wiring metal film 18 having tensile stress, and the absolute value of the wafer warpage amount generated by the deposition of the stress relaxation film 17 is smaller than the absolute value of the wafer warpage amount generated by the deposition of the first wiring metal film 18. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, a semiconductor device capable of alleviating a warpage of a wafer caused by a tensile stress of a metal film for wiring and reducing defects in the manufacturing process of the semiconductor device due to the warpage of the wafer. And a manufacturing method thereof.

  A conventional method for manufacturing a semiconductor device will be described with reference to FIG. First, a silicon oxide film (not shown) is formed on the surface of the silicon wafer 10 by, eg, thermal oxidation. Next, silicon nitride films (not shown) are respectively formed on the silicon oxide films formed on the front surface and the back surface of the silicon wafer 10 by, for example, thermal CVD using a vertical furnace. Next, a photoresist film (not shown) is formed on the silicon nitride film on the surface of the silicon wafer 10 by exposing the element isolation film formation region and covering the other region by photolithography. Next, the silicon nitride film is etched using the photoresist film as a mask. Thereby, an opening is formed in the silicon nitride film. Next, the silicon oxide film and the silicon wafer 10 are etched from the surface side of the silicon wafer 10 using the photoresist film and the silicon nitride film as a mask, respectively. Thereby, an opening is formed in the silicon oxide film, and a groove is formed in the surface of the silicon wafer 10. After the grooves are formed on the surface of the silicon wafer 10, the photoresist film is removed by, for example, ashing. Next, a silicon oxide film is formed on the entire surface of the silicon wafer 10 by, eg, CVD. Next, the silicon oxide film is polished by CMP, for example, until the surface of the silicon nitride film is exposed, and the silicon oxide film on the silicon nitride film is removed. Thus, the silicon oxide film is embedded in the groove formed in the silicon wafer 10, the opening formed in the silicon oxide film, and the opening formed in the silicon nitride film. Thereby, an element isolation film 11 made of a silicon oxide film is formed. Next, the silicon nitride film on the surface of the silicon wafer 10 is removed by wet etching. At this time, the silicon nitride film on the back surface of the silicon wafer 10 is also removed by etching. Next, the silicon oxide film exposed on the surface of the silicon wafer 10 is removed by wet etching. At this time, the silicon oxide film on the back surface of the silicon wafer 10 is also removed by etching. As described above, a semiconductor element such as a MOSFET is formed on the surface of the silicon wafer 10 in which the element region (active region) is defined by the element isolation film 11 (reference numeral 12 is a gate oxide film, reference numeral 13 is Each gate electrode is shown).

  On the surface of the silicon wafer 10 on which the semiconductor elements are formed, metal wiring layers 16a and 16b embedded in the interlayer insulating films 15a to 15c are repeatedly formed as appropriate using a single damascene method, a dual damascene method, or the like. A multilayer wiring having a plurality of metal wiring layers is formed. In FIG. 19, a power supply wiring having a large line width and film thickness is formed as the uppermost metal wiring. Vias 14a to 14c penetrating the interlayer insulating films 15a to 15c connect the upper and lower layers of the metal wirings 16a, 16b and 18 or the lower metal wiring 16a and the electrode terminals of the semiconductor element to each other.

  Due to the increase in the number of metal wiring layers and the low dielectric constant (low-k) of the interlayer insulating film, a semiconductor substrate having an interlayer insulating film formed on the surface is affected by the tensile stress of the interlayer insulating film. In some cases, the back side is greatly warped convexly. In order to avoid this, as shown in FIG. 19, a substrate 10 made of semiconductor, interlayer insulating films 15a to 15c formed on the surface of the substrate 10, and a multilayer metal wiring embedded in the interlayer insulating films 15a to 15c. In the semiconductor device including 16a, 16b and the uppermost metal wiring 18, a stress relaxation insulating film 20 having a stress that relaxes the stress applied to the substrate by the interlayer insulating film may be formed on the back side of the substrate 10. Is disclosed in Patent Document 1 below.

JP 2006-004982 A

  In recent years, with the demand for higher integration of semiconductor devices, the number of wiring layers constituting a multilayer wiring formed on a semiconductor substrate has increased. Further, with the demand for higher speed and lower voltage for semiconductor devices, low dielectric constant (low-k) insulating films are used as interlayer insulating films in which wiring layers and the like are embedded. Furthermore, it is required that a high-frequency element formed by forming a relatively thick metal film on the upper layer is formed in the same chip. As a result, the warpage of the semiconductor substrate becomes even more pronounced.

  Further, the diameter of a semiconductor substrate (wafer) used for manufacturing a semiconductor device is increasing, and the warpage of the semiconductor substrate tends to be further increased. The warpage of the semiconductor substrate causes, for example, a suction failure in a transport system that sucks and transports the semiconductor substrate with a chuck or the like. Therefore, it is required to suppress such warpage of the semiconductor substrate.

  The present invention has been made in view of the above problems, and an object thereof is to suppress wafer warpage in a semiconductor device in which an interlayer insulating film having a tensile stress or a metal film for wiring is formed on a semiconductor substrate. A semiconductor device and a manufacturing method thereof are provided.

  In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device comprising a semiconductor substrate on which a semiconductor element is formed, and one or more layers of wiring metal films deposited on the semiconductor substrate. Among the one or more layers of wiring metal films, at least one of the lower layer side and the upper layer side of the first wiring metal film where the absolute value of the amount of wafer warpage caused by the deposition of one wiring metal film is maximized. A stress relaxation film for relaxing the amount of warpage of the wafer is provided on one side, the stress relaxation film has a compressive stress, the metal film for first wiring has a tensile stress, and is generated by the deposition of the stress relaxation film. A first feature is that the absolute value of the amount of wafer warpage is smaller than the absolute value of the amount of wafer warpage caused by the deposition of the first metal film for wiring.

  According to the semiconductor device having the first feature, the amount of wafer warpage after depositing both the first wiring metal film and the stress relaxation film is such that the stresses of the first wiring metal film and the stress relaxation film are in opposite directions. Therefore, since the amount of warpage of the wafer after the metal film for the first wiring is deposited without depositing the stress relaxation film is reduced, the wafer is warped during the semiconductor device manufacturing process (wafer processing process). For example, it is possible to prevent problems such as the occurrence of wafer adsorption failure in the transfer system of the wafer processing apparatus.

  In particular, since the stress relaxation film is laminated on the first wiring metal film that induces the maximum amount of wafer warping in one or more layers of wiring metal films, the problems caused by wafer warping are most efficient. Can be prevented or reduced.

  Furthermore, since the absolute value of the amount of wafer warp caused by the deposition of the stress relaxation film is smaller than the absolute value of the amount of wafer warp caused by the deposition of the first wiring metal film, for example, the stress relaxation film is formed on the first wiring metal film. When the film is first formed on the lower layer side, the amount of warpage of the wafer due to the compressive stress of the stress relaxation film is suppressed to such an extent that it does not adversely affect the photoetching step before the deposition of the first wiring metal film. Problems due to the amount of warpage of the wafer due to the tensile stress of the wiring metal film can be prevented.

  Further, since the stress relaxation film is formed on at least one of the lower layer side and the upper layer side of the first wiring metal film, for example, by performing a patterning process similarly to the first wiring metal film, the above-mentioned patent Unlike the conventional substrate stress relaxation film provided on the back surface side of the substrate disclosed in Document 1, it is not necessary to delete the film as an unnecessary film later, so that the manufacturing process can be simplified.

  Further, in addition to the first feature, the semiconductor device according to the present invention has a wafer warpage in which the absolute value of the amount of wafer warpage caused by the deposition of the first wiring metal film causes a problem in the semiconductor device manufacturing process. The second feature is that the amount is equal to or greater than the upper limit value.

  According to the semiconductor device of the second feature, since the first wiring metal film is deposited without depositing the stress relaxation film, it is applied to a case that causes a malfunction in the semiconductor device manufacturing process. It is possible to eliminate the problem and complete the semiconductor device.

  Furthermore, in addition to the first or second feature described above, the semiconductor device according to the present invention has the above-described case where the stress relaxation film is formed as a first stress relaxation film on the lower layer side of the first metal film for wiring. A third feature is that the compressive stress of the first stress relaxation film is in the range of 0.5 GPa or more and 4 GPa or less.

  Furthermore, in addition to any of the above features, the semiconductor device according to the present invention has the first stress when the stress relaxation film is formed as a first stress relaxation film on the lower layer side of the first wiring metal film. A fourth feature is that the thickness of the relaxation film is in the range of 30 nm to 1 μm.

  Furthermore, in addition to the fourth feature, the semiconductor device according to the present invention has the first stress when the stress relaxation film is formed as a first stress relaxation film on a lower layer side of the first wiring metal film. A fifth feature is that the relaxation film is any one of a SiO film, a SiN film, a SiON film, a SiC film, and a SiOC film.

  According to the semiconductor device having the third to fifth features, specifically, the first stress relaxation film having a compressive stress suitable for relaxing the warpage of the wafer caused by the deposition of the first wiring metal film is realized. it can.

  Furthermore, in addition to any of the above features, the semiconductor device according to the present invention has the second stress when the stress relaxation film is formed as a second stress relaxation film on the upper layer side of the first wiring metal film. A sixth feature is that the compressive stress of the relaxation film is in a range of 0.05 GPa to 4 GPa.

  Furthermore, in addition to any of the above features, the semiconductor device according to the present invention has the second stress when the stress relaxation film is formed as a second stress relaxation film on the upper layer side of the first wiring metal film. A seventh feature is that the thickness of the relaxation film is in the range of 30 nm to 4 μm.

  Furthermore, in addition to any of the above features, the semiconductor device according to the present invention has the second stress when the stress relaxation film is formed as a second stress relaxation film on the upper layer side of the first wiring metal film. The eighth feature is that the relaxation film is any one of a SiO film, a SiN film, a SiON film, a SiC film, a SiOC film, and an amorphous carbon film.

  According to the semiconductor devices having the sixth to eighth features, specifically, the second stress relaxation film having a compressive stress suitable for relaxing the warpage of the wafer caused by the deposition of the first wiring metal film is realized. it can.

  Furthermore, the semiconductor device according to the present invention has, in addition to any one of the above features, a ninth feature that the thickness of the first wiring metal film is in the range of 0.75 μm to 10 μm. .

  According to the semiconductor device having the ninth feature, the first wiring metal film is deposited without depositing the stress relaxation film because the wafer warp amount increases as the thickness of the first wiring metal film increases. In this case, the present invention is applied to a case in which a problem occurs in the semiconductor device manufacturing process, so that the problem can be solved and a semiconductor device can be completed. Further, by providing a restriction that the film thickness of the first wiring metal film is 10 μm or less, it is possible to prevent wafer cracking and peeling of the first wiring metal film.

  Furthermore, in addition to any of the above features, the semiconductor device according to the present invention may be any one of Al, W, Ti, Cu, Au, Ag, and Mo as a material for the first wiring metal film. A tenth feature is that the metal contains an element.

  According to the semiconductor device having the tenth feature, all of Al, W, Ti, Cu, Au, Ag, and Mo exhibit tensile stress. The trouble in the process of manufacturing the semiconductor device due to the tensile stress of the metal film can be prevented.

  Furthermore, in addition to any of the above features, the semiconductor device according to the present invention has the first stress when the stress relaxation film is formed as a first stress relaxation film on the lower layer side of the first wiring metal film. An eleventh feature is that the relaxation film and the first wiring metal film are patterned in the same planar shape.

  Furthermore, in addition to any of the above features, the semiconductor device according to the present invention has the second stress when the stress relaxation film is formed as a second stress relaxation film on the upper layer side of the first wiring metal film. A twelfth feature is that the relaxation film and the first wiring metal film are patterned in the same planar shape.

  According to the semiconductor device having the eleventh or twelfth feature, the amount of wafer warpage due to the tensile stress of the patterned first wiring metal film is reduced in accordance with the pattern density from the value immediately after the deposition, and therefore a large compressive stress. By similarly patterning the stress relaxation film having, the influence of the stress relaxation film on the subsequent process can be reduced in the manufacturing process of the semiconductor device.

  Furthermore, in addition to any of the above features, the semiconductor device according to the present invention has a thirteenth feature in that the first wiring metal film is the uppermost layer of the one or more wiring metal films. To do.

  According to the semiconductor device having the thirteenth feature, the uppermost wiring metal film used as power supply wiring or inductor wiring is usually thicker than 1 μm, and the amount of wafer warpage is large accordingly. Since the stress relaxation film is laminated on the first metal film for wiring to be induced, it is possible to most effectively prevent or reduce the trouble caused by the warpage of the wafer.

  In order to achieve the above object, a semiconductor device manufacturing method according to the present invention comprises a semiconductor substrate on which a semiconductor element is formed, and one or more layers of wiring metal films deposited on the semiconductor substrate. A method of manufacturing an apparatus, comprising: a lower layer of a first wiring metal film that has a maximum absolute value of the amount of wafer warpage caused by the deposition of one wiring metal film among the one or more layers of wiring metal films A stress relieving film forming step of depositing a stress relieving film for relieving the amount of warpage of the wafer on at least one of the side and the upper layer side. In the stress relieving film forming step, the stress relieving film has a compressive stress. And forming the stress relaxation film so that the absolute value of the amount of wafer warpage caused by the deposition of the stress relaxation film is smaller than the absolute value of the amount of wafer warpage caused by the deposition of the metal film for the first wiring. A first said Rukoto.

  According to the semiconductor device manufacturing method of the first feature, the amount of wafer warpage after depositing both the first wiring metal film and the stress relaxation film is such that the stress of the first wiring metal film and the stress relaxation film is the same. Due to the reverse direction, the amount of warpage of the wafer after the metal film for the first wiring is deposited without depositing the stress relaxation film is reduced, so that the wafer is warped during the semiconductor device manufacturing process (wafer processing process). For example, it is possible to prevent problems such as occurrence of defective wafer adsorption in the transfer system of the wafer processing apparatus.

  In particular, since the stress relaxation film is laminated on the first wiring metal film that induces the maximum amount of wafer warping in one or more layers of wiring metal films, the problems caused by wafer warping are most efficient. Can be prevented or reduced.

  Furthermore, since the absolute value of the amount of wafer warp caused by the deposition of the stress relaxation film is smaller than the absolute value of the amount of wafer warp caused by the deposition of the first wiring metal film, for example, the stress relaxation film is formed on the first wiring metal film. When the film is first formed on the lower layer side, the amount of warpage of the wafer due to the compressive stress of the stress relaxation film is suppressed to such an extent that it does not adversely affect the photoetching step before the deposition of the first wiring metal film. Problems due to the amount of warpage of the wafer due to the tensile stress of the wiring metal film can be prevented.

  Further, since the stress relaxation film is formed on at least one of the lower layer side and the upper layer side of the first wiring metal film, for example, by performing a patterning process similarly to the first wiring metal film, the above-mentioned patent Unlike the conventional substrate stress relaxation film provided on the back surface side of the substrate disclosed in Document 1, it is not necessary to delete the film as an unnecessary film later, so that the manufacturing process can be simplified.

  Further, in the semiconductor device manufacturing method according to the present invention, in addition to the first feature, the absolute value of the amount of wafer warpage caused by the deposition of the first wiring metal film causes a problem in the semiconductor device manufacturing process. The second feature is that the stress relaxation film forming step is executed when the wafer warpage amount is equal to or greater than the upper limit value of the wafer warpage.

  Furthermore, in addition to the first feature, the method of manufacturing a semiconductor device according to the present invention provides the stress relaxation when the absolute value of the amount of wafer warp caused by the deposition of the first wiring metal film is 100 μm or more. The third feature is to execute the film forming step.

  The method for manufacturing a semiconductor device according to the second or third feature is applied to a case in which a defect is caused in the semiconductor device manufacturing process when the first wiring metal film is deposited without depositing the stress relaxation film. Therefore, it becomes possible to solve the problem and complete the semiconductor device.

  Furthermore, in addition to any one of the above features, the method of manufacturing a semiconductor device according to the present invention includes forming the stress relaxation film using a plasma CVD method in the stress relaxation film formation step. Features.

  According to the semiconductor device manufacturing method of the fourth feature, the stress of the stress relaxation film can be adjusted to an appropriate value of compressive stress by controlling the film formation conditions by the plasma CVD method. The effect of the said characteristic can be show | played concretely.

  Furthermore, in addition to any one of the above features, the method for manufacturing a semiconductor device according to the present invention provides a first stress relaxation layer on the lower layer side of the first wiring metal film in the stress relaxation film forming step. When formed as a film, a fifth feature is that it includes a patterning step of patterning the first stress relaxation film and the first wiring metal film in the same planar shape.

  Further, in the semiconductor device manufacturing method according to the present invention, in addition to any of the first to fourth features, in the stress relaxation film forming step, the stress relaxation film is an upper layer of the first metal film for wiring. In the case where the second stress relaxation film is formed on the side, it has a patterning step of patterning the second stress relaxation film and the first wiring metal film in the same plane shape.

  Further, in the semiconductor device manufacturing method according to the present invention, in addition to any of the first to fourth features, in the stress relaxation film forming step, the stress relaxation film is a lower layer of the metal film for the first wiring. When the first stress relaxation film and the second stress relaxation film are formed on the side and the upper layer side, respectively, the first stress relaxation film, the second stress relaxation film, and the first wiring metal film have the same planar shape. A seventh feature is that a patterning step of patterning is provided.

  According to the semiconductor device manufacturing method of the fifth to seventh features, the amount of wafer warpage due to the tensile stress of the patterned first wiring metal film decreases according to the pattern density from the value immediately after deposition. By similarly patterning the stress relaxation film having a large compressive stress, it is possible to reduce the influence of the stress relaxation film on the subsequent process in the manufacturing process of the semiconductor device.

  Furthermore, since the first wiring metal film and the stress relaxation film are patterned in the same process, the amount of warpage of the wafer can be reduced without increasing the number of processes for patterning the stress relaxation film. In the sixth or seventh feature, the second stress relaxation film can be used as an antireflection film during exposure during patterning and as a hard mask during etching during etching.

  Furthermore, in addition to the sixth or seventh feature, the method for manufacturing a semiconductor device according to the present invention is characterized in that the second stress relaxation film is removed after the patterning step.

  According to the semiconductor device manufacturing method of the eighth feature, the amount of wafer warpage due to the tensile stress of the patterned first wiring metal film decreases according to the pattern density from the value immediately after the deposition, and thus a large compressive stress. By removing the second stress relaxation film having, it is possible to reduce the influence of the second stress relaxation film on the subsequent process in the manufacturing process of the semiconductor device.

  Furthermore, in addition to any of the above features, the method for manufacturing a semiconductor device according to the present invention forms the stress relaxation film using the uppermost layer of the one or more wiring metal films as the first metal film for wiring. The ninth feature is to execute the process.

  According to the semiconductor device manufacturing method of the ninth feature, the uppermost wiring metal film used as power supply wiring or inductor wiring is usually thicker than 1 μm, and the amount of warpage of the wafer is large correspondingly. Since the stress relaxation film is laminated on the first wiring metal film that induces the amount of warpage of the wafer, it is possible to most effectively prevent or alleviate the problems caused by the warpage of the wafer.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device according to the present invention and a method for manufacturing the same (hereinafter referred to as “device of the present invention” and “method of the present invention” as appropriate) will be described below with reference to the drawings.

  First, the relationship between the amount of warpage of a silicon wafer having a wiring metal film formed on the surface and the film thickness of the wiring metal film will be described with reference to FIG. FIG. 18 shows an example of the relationship between the amount of wafer warpage and the thickness of the wiring metal film when the base is a silicon wafer having a diameter of 200 mm and 300 mm, and the horizontal axis shows the thickness of the wiring metal film, The vertical axis represents the amount of warpage of the silicon wafer. In the transport mechanism of the semiconductor manufacturing equipment used by the inventors of the present application, it has been confirmed that when the amount of warpage of the silicon wafer is 100 μm or more, a transport error due to poor suction occurs. When the diameter is 200 mm, the film thickness is about 1.5 μm or more, and when the diameter is 300 mm, the film thickness is about 0.75 μm or more.

  The underlying structure of the wiring metal film is not limited to a silicon wafer, but is usually a semiconductor substrate on which a semiconductor element such as a MOSFET or other wiring metal film has already been formed. In the case of the structure, since the base structure itself is usually warped, the warpage amount of the entire wafer is the sum of the warpage amount of the base structure and the warpage amount due to the wiring metal film (the direction of the warp is reverse). The case is a difference). In this embodiment, the amount of wafer warpage is measured by interference of coherent light (single wavelength laser).

<First Embodiment>
1st Embodiment of this invention apparatus and this invention method is described with reference to FIGS. FIG. 1 is a schematic cross-sectional view schematically showing a cross-sectional structure of a main part of the device of the present invention. 2-6 is process sectional drawing which shows typically the process of the method of this invention in this embodiment.

  First, the structure of the semiconductor substrate according to the present embodiment will be explained with reference to FIG. As shown in FIG. 1, the device of the present invention includes a silicon wafer (semiconductor substrate) 10 having MOSFETs as semiconductor elements formed on its surface, interlayer insulating films 15a to 15c formed on the upper surface side of the silicon wafer 10, and a plurality of insulating films. A multilayer wiring structure composed of the metal wiring layers 16a and 16b, a first stress relaxation film 17 composed of a silicon nitride film sequentially stacked on the upper surface of the multilayer wiring structure and patterned in the same plane, and the uppermost metal wiring The first wiring metal film 18 as a layer is provided. Vias 14a to 14c penetrating the interlayer insulating films 15a to 15c, the metal wiring layers 16a and 16b, the upper and lower layers of the first wiring metal film 18, or the lower metal wiring layer 16a and the electrode terminals of the semiconductor element are mutually connected. It is connected to the.

  The first wiring metal film 18 is formed to be thicker than the other metal wiring layers 16a and 16b on the lower layer side, for example, for use as a power supply wiring or an inductor forming wiring. The absolute value of the amount of wafer warp caused by the deposition is larger than that of the metal wiring layers 16a and 16b.

  Next, the method of the present invention will be described in detail with reference to FIGS. In the following description, a silicon wafer 10 having a diameter of 200 mm was used.

  As shown in FIG. 2, an element isolation region 11 for defining an element region is formed on the surface of the silicon wafer 10 by using a known method, for example, in the same manner as the conventional method for manufacturing a semiconductor device illustrated in FIG. Form. A semiconductor element such as a MOSFET is formed in the active region defined by the element isolation region 11 on the surface of the silicon wafer 10.

  Further, as shown in FIG. 2, a gate electrode 13 is formed in the active region on the surface of the silicon wafer 10 via a gate insulating film 12. A sidewall insulating film is formed on the sidewall portion of the gate electrode 13. Source / drain diffusion layers are formed on the surface of the silicon wafer 10 on both sides of the gate electrode 13. The source / drain diffusion layer includes a shallow and low-concentration impurity diffusion region whose end on the gate electrode 13 side extends to the bottom of the sidewall insulating film, and a deep portion whose end on the gate electrode 13 side extends to the end of the sidewall insulating film. And a high concentration impurity diffusion region. A pocket region is formed on the channel region side of the source / drain diffusion layer. Metal silicide films (not shown) are formed on the gate electrode 13 and the source / drain diffusion layers, respectively. In this way, a MOSFET having the gate electrode 13 and the source / drain diffusion layers is formed.

  Further, as shown in FIG. 2, interlayer insulating films 15a, 15b and 15c formed by sequentially laminating a silicon nitride film and a silicon oxide film are formed on the silicon wafer 10 on which the MOSFET is formed. Metal wirings 16a and 16b are embedded in 15b and 15c by using a single damascene method, a dual damascene method, or the like. Vias 14a and 14b are formed in the interlayer insulating films 15a to 15c, respectively, and between the electrode terminals of the MOSFETs such as the source / drain diffusion layers and the gate electrode 13 and the metal wiring 16a and the upper and lower metal wirings 16a and 16b are electrically connected. Metal for contact plugs to be connected is embedded. In the manner described above, as shown in FIG. 2, a multilayer wiring structure in which MOSFETs are formed is formed on the silicon wafer 10, and the multilayer wiring structure is composed of the first stress relaxation film 17 and the first wiring metal film 18. The underlying structure.

Next, as shown in FIG. 3, a first stress relaxation film 17 having a compressive stress which is an opposite stress to the first wiring metal film 18 to be formed in a later step is deposited. In this embodiment, a silicon nitride film having a compressive stress of 2 GPa is formed with a thickness of 300 nm by plasma CVD. The processing conditions during the formation were such that a mixed gas of SiH ₄ gas and NH ₃ gas was used as a raw material gas and a film forming temperature range of 350 to 480 ° C. was used. In addition, the plasma CVD method is used for the deposition of the first stress relaxation film 17, and the stress of the first stress relaxation film 17 is adjusted to compressive stress (about 3 GPa) and tensile stress (by adjusting the pressure and high frequency power during film formation). In this embodiment, the first stress relaxation film 17 is adjusted to a compressive stress of 2 GPa.

  The compressive stress and the film thickness required for the first stress relaxation film 17 are determined by the tensile stress and the film thickness of the first wiring metal film 18, but the film thickness is 30 nm or more from the accuracy of the thin film formation and processing. The dimension that can be processed by etching or the like is preferably 1 μm or less. Further, the value of the compressive stress is preferably 0.5 GPa or more in order to control the wafer warp, and 4 GPa or less is preferable in consideration of film peeling.

  Next, as shown in FIG. 4, the first wiring metal film 18 and the lower-layer side metal wiring 16b are formed on the first stress relaxation film 17 and the underlying interlayer insulating film 15c by a known photolithography technique and etching technique. Vias 14c are formed for electrical connection therebetween.

  Next, as shown in FIG. 5, the via 14c is filled with a metal for contact plug. In the present embodiment, after depositing tungsten on the entire exposed surface of the first stress relaxation film 17 and the via 14c, unnecessary metal on the surface is removed by an etch back method, and a contact plug is filled in the via 14c.

  Next, as shown in FIG. 6, a first wiring metal film 18 is formed. In this embodiment, an Al film (containing 0 to 1% of Cu) having a tensile stress of 0.2 GPa is deposited with a film thickness of 4 μm by a sputtering method.

  Generally, the thickness of the first wiring metal film 18 is about 0.75 μm for a 300 mm wafer and about 1.5 μm for a 200 mm wafer, as shown in FIG. In this embodiment using the first stress relaxation film 17, the stress relaxation effect is substantially effective when the thickness of the first wiring metal film 18 is 1.5 μm or more. The film thickness of the first wiring metal film 18 is preferably 10 μm or less from the viewpoint of wafer cracking and film peeling.

  Next, the first stress relaxation film 17 and the first wiring metal film 18 are patterned into the same planar shape by a known photolithography technique and etching technique, and the device of the present invention shown in FIG. 1 is manufactured. Here, the first stress relaxation film 17 can be used as an etching stopper when the first wiring metal film 18 is etched, and the controllability of the etching of the first wiring metal film 18 can be improved. In the device of the present invention shown in FIG. 1, illustration of a protective film and the like formed on the first wiring metal film 18 after patterning is omitted.

  As described above, the device of the present invention is manufactured through the steps shown in FIGS. According to the present embodiment, since the first wiring metal film 18 having tensile stress is formed on the first stress relaxation film 17 having compressive stress, the warpage of the wafer due to the compressive stress on the first stress relaxation film 17. Since the warpage of the wafer due to the tensile stress of the first wiring metal film 18 is reversed and cancels out, the warpage of the wafer is suppressed. In the present embodiment, the amount of wafer warpage can be suppressed to 60 μm or less. As a result, it is possible to prevent the occurrence of adsorption failure in the wafer transfer system.

  Next, a method for measuring the stress of the first stress relaxation film 17 and the first wiring metal film 18 in this embodiment will be briefly described.

In the present embodiment, the amount of wafer warpage is measured using a wafer warpage measuring device using light interference, and the stress S (dyn / cm ² =) is calculated based on the following formulas 1 and ^2. 0.1 Pa). Here, E the Young's modulus of ^{Si <100> (dyn / cm} 2), ν is Poisson's ratio of the silicon, b is the thickness of the wafer (μm), _{r a} is the wafer warp after the measured film deposition radius of curvature ( cm), _{r b} is the radius of curvature of wafer warpage before the measured film deposition (cm), d is the thickness of the measured film (μm), R is the wafer radius (cm), after _{W a} is the measured film deposition amount of wafer warpage (μm), W _b is the wafer warp amount before the measured film deposition ([mu] m).

[Equation 1]
S = E × b ² × (1 / r _a −1 / r _b ) / (6 (1-ν) × d)

[Equation 2]
r _{a, b} = (2R) ² / 8W _{a, b}

Therefore, if the wafer warp amount W _a after deposition of the film to be measured, W _b before deposition of the film to be measured, and the film thickness d of the film to be measured are known from Equations 1 and 2, the stress S can be expressed as It is given by the number 3.

[Equation 3]
S = A × (W _a −W _b ) / d

From Equation 3, if the product of the compressive stress and the film thickness of the first stress relaxation film 17 is the same, the same effect of suppressing the amount of wafer warp will be exhibited. However, the wafer warp after the deposition of the first stress relaxation film 17 is achieved. the amount W _a, before the first wiring metal film 18 is deposited, so as not to large wafer warpage exceeding 100 [mu] m, the upper limit of the product of the compressive stress and the film thickness is limited. That is, when a wafer warp amount exceeding 100 μm occurs after the first stress relaxation film 17 is deposited, the original purpose of providing the first stress relaxation film 17 on the lower layer side of the first wiring metal film 18 is the first stress relaxation film. This is because 17 itself is damaged.

  In the present embodiment, one of the reasons for using the silicon nitride film as the first stress relaxation film 17 is that the silicon nitride film can obtain a relatively large compressive stress and has a large adjustment range. The film thickness can be reduced, and the cost required for etching the first stress relaxation film 17 can be reduced.

Second Embodiment
A second embodiment of the device of the present invention and the method of the present invention will be described with reference to FIGS. FIG. 7 is a schematic cross-sectional view schematically showing a main-part cross-sectional structure of the device of the present invention. 8 to 13 are process cross-sectional views schematically showing the process of the method of the present invention in the present embodiment. 8 to 13, the same components as those in the first embodiment will be described with the same reference numerals for easy understanding.

  As shown in FIG. 7, the device according to the second embodiment includes a silicon wafer (semiconductor substrate) 10 on which a MOSFET as a semiconductor element is formed, and an interlayer insulating film formed on the upper surface side of the silicon wafer 10. A multilayer wiring structure comprising 15a to 15c and a plurality of metal wiring layers 16a and 16b, and a first stress relaxation film 17 comprising a silicon nitride film sequentially laminated on the upper surface of the multilayer wiring structure and patterned in the same planar shape; The first wiring metal film 18 that is the uppermost metal wiring layer and the second stress relaxation film 19 made of an amorphous carbon film are provided. Vias 14a to 14c penetrating the interlayer insulating films 15a to 15c, the metal wiring layers 16a and 16b, the upper and lower layers of the first wiring metal film 18, or the lower metal wiring layer 16a and the electrode terminals of the semiconductor element are mutually connected. It is connected to the.

  The first wiring metal film 18 is formed to be thicker than the other metal wiring layers 16a and 16b on the lower layer side, for example, for use as a power supply wiring or an inductor forming wiring. The absolute value of the amount of wafer warp caused by the deposition is larger than that of the metal wiring layers 16a and 16b.

  Next, the method of the present invention will be described in detail with reference to FIGS. In the following description, a silicon wafer 10 having a diameter of 200 mm was used.

  As shown in FIG. 7, the device of the present invention of the second embodiment has a first stress relaxation film 17, a first wiring metal film 18 and a second stress relaxation on the upper surface of the same multilayer wiring structure as that of the first embodiment. Since the films 19 are formed in order, the formation process of the multilayer wiring structure shown in FIG. 8 is the same as that in the first embodiment, and a duplicate description is omitted.

Next, as shown in FIG. 9, a first stress relaxation film 17 having a compressive stress which is an opposite stress to the first wiring metal film 18 to be formed in a later step is deposited. In this embodiment, a silicon nitride film having a compressive stress of 2 GPa is formed with a thickness of 200 nm by plasma CVD. The processing conditions during the formation were such that a mixed gas of SiH ₄ gas and NH ₃ gas was used as a raw material gas and a film forming temperature range of 350 to 480 ° C. was used. In addition, the plasma CVD method is used for the deposition of the first stress relaxation film 17, and the stress of the first stress relaxation film 17 is adjusted to compressive stress (about 3 GPa) and tensile stress (by adjusting the pressure and high frequency power during film formation). In this embodiment, the first stress relaxation film 17 is adjusted to a compressive stress of 2 GPa.

  The compressive stress and film thickness required for the first stress relaxation film 17 are determined by the tensile stress and film thickness of the first wiring metal film 18 and the compression stress and film thickness of the second stress relaxation film 19. The film thickness is preferably 30 nm or more from the precision of thin film formation and processing, and the dimension that can be processed by etching or the like is preferably 1 μm or less. Further, the value of the compressive stress is preferably 0.5 GPa or more in order to control the wafer warp, and 4 GPa or less is preferable in consideration of film peeling.

  Next, as shown in FIG. 10, the first wiring metal film 18 and the lower-layer side metal wiring 16b are formed on the first stress relaxation film 17 and the underlying interlayer insulating film 15c by a known photolithography technique and etching technique. Vias 14c are formed for electrical connection therebetween.

  Next, as shown in FIG. 11, the via 14c is filled with a metal for contact plug. In the present embodiment, after depositing tungsten on the entire exposed surface of the first stress relaxation film 17 and the via 14c, unnecessary metal on the surface is removed by an etch back method, and a contact plug is filled in the via 14c.

  Next, as shown in FIG. 12, a first wiring metal film 18 is formed. In this embodiment, an Al film (containing 0 to 1% of Cu) having a tensile stress of 0.2 GPa is deposited with a film thickness of 4 μm by a sputtering method.

  Generally, the thickness of the first wiring metal film 18 is about 0.75 μm for a 300 mm wafer and about 1.5 μm for a 200 mm wafer, as shown in FIG. In this embodiment using the first stress relaxation film 17, the stress relaxation effect is substantially effective when the thickness of the first wiring metal film 18 is 1.5 μm or more. The film thickness of the first wiring metal film 18 is preferably 10 μm or less from the viewpoint of wafer cracking and film peeling.

Next, as shown in FIG. 13, a second stress relaxation film 19 having a compressive stress which is the opposite stress to the first wiring metal film 18 is deposited. In this embodiment, an amorphous carbon film having a compressive stress of 0.3 GPa is formed with a film thickness of 400 nm by plasma CVD. The processing conditions during the formation were such that a mixed gas of C ₂ H ₂ gas, He gas, and N ₂ was used as a source gas, and a film forming temperature range of 350 to 480 ° C. was used.

  The compressive stress and film thickness required for the second stress relaxation film 19 are determined by the compression stress and film thickness of the first stress relaxation film 17 and the tensile stress and film thickness of the first wiring metal film 18. The film thickness is preferably 30 nm or more from the accuracy of film formation and processing, and the dimension that can be processed by etching or the like is preferably 4 μm or less. Further, the value of the compressive stress is preferably 0.05 GPa or more in order to control the wafer warp, and 4 GPa or less is preferable in consideration of film peeling. Since the second stress relaxation film 19 is deposited on the upper surface side of the first wiring metal film 18, in the case of an insulating film having a relatively small compressive stress such as an amorphous carbon film, the film thickness is increased. By doing so, the effect of suppressing the amount of warpage of the wafer can be obtained.

  In this embodiment, the second stress relaxation film 19 has a thickness of the first stress relaxation film 17 in order to reduce the amount of warpage of the wafer with two layers of the first stress relaxation film 17 and the second stress relaxation film 19. It is added for the purpose of compensating for the thinning.

Next, the first stress relaxation film 17, the first wiring metal film 18 and the second stress relaxation film 19 are patterned into the same planar shape by a known photolithography technique and etching technique, and the present invention shown in FIG. A device is made. Here, the first stress relaxation film 17 can be used as an etching stopper when the first wiring metal film 18 is etched, and the controllability of the etching of the first wiring metal film 18 can be improved. Further, the second stress relaxation film 19 can be used as a hard mask when the first wiring metal film 18 is etched. Further, the second stress relaxation film 19 of the amorphous carbon film can be removed at the same time as the resist removal by O ₂ ashing. In the device of the present invention shown in FIG. 7, the illustration of a protective film or the like formed on the first wiring metal film 18 after patterning is omitted.

  As described above, the device of the present invention is manufactured through the steps shown in FIGS. According to this embodiment, the first wiring metal film 18 having tensile stress is formed on the first stress relaxation film 17 having compressive stress, and the first wiring metal film 18 having compressive stress is formed on the first wiring metal film 18. Since the two stress relaxation films 19 are formed, the warpage of the wafer due to the compressive stress of the first stress relaxation film 17 and the second stress relaxation film 19 and the warpage of the wafer due to the tensile stress of the first wiring metal film 18 are opposite. Therefore, the warpage of the wafer is suppressed. In the present embodiment, the amount of wafer warpage can be suppressed to 70 μm or less. As a result, it is possible to prevent the occurrence of adsorption failure in the wafer transfer system.

<Third Embodiment>
A third embodiment of the device and the method of the present invention will be described with reference to FIGS. FIG. 14 is a schematic cross-sectional view schematically showing a main-part cross-sectional structure of the device of the present invention. 15 to 17 are process cross-sectional views schematically showing the process of the method of the present invention in the present embodiment. 15 to 17, the same components as those in the first and second embodiments will be described with the same reference numerals for easy understanding.

  As shown in FIG. 14, the device according to the third embodiment includes a silicon wafer (semiconductor substrate) 10 on which a MOSFET as a semiconductor element is formed, and an interlayer insulating film formed on the upper surface side of the silicon wafer 10. For a first wiring, which is a multilayer wiring structure composed of 15a to 15c and a plurality of metal wiring layers 16a and 16b, and an uppermost metal wiring layer that is sequentially stacked on the upper surface of the multilayer wiring structure and patterned in the same plane shape A metal film 18 and a second stress relaxation film 19 made of an amorphous carbon film are provided. Vias 14a to 14c penetrating the interlayer insulating films 15a to 15c, the metal wiring layers 16a and 16b, the upper and lower layers of the first wiring metal film 18, or the lower metal wiring layer 16a and the electrode terminals of the semiconductor element are mutually connected. It is connected to the.

  The first wiring metal film 18 is formed to be thicker than the other metal wiring layers 16a and 16b on the lower layer side, for example, for use as a power supply wiring or an inductor forming wiring. The absolute value of the amount of wafer warp caused by the deposition is larger than that of the metal wiring layers 16a and 16b.

  Next, the method of the present invention will be described in detail with reference to FIGS. In the following description, a silicon wafer 10 having a diameter of 200 mm was used.

  As shown in FIG. 14, the device according to the third embodiment of the present invention has a first wiring metal film 18 and a second stress relaxation film 19 in order on the upper surface of the same multilayer wiring structure as in the first and second embodiments. Therefore, the formation process of the multilayer wiring structure shown in FIG. 15 is basically the same as that of the first and second embodiments, and a duplicate description is omitted.

  Next, as shown in FIG. 15, vias 14c for electrical connection between the first wiring metal film 18 and the lower metal wiring 16b are formed in the interlayer insulating film 15c by a known photolithography technique and etching technique. The via 14c is filled with a metal for contact plug. In this embodiment, after depositing tungsten on the entire exposed surfaces of the interlayer insulating film 15c and the via 14c, unnecessary metal on the surface is removed by an etch back method, and a contact plug is filled in the via 14c.

  Next, as shown in FIG. 16, a first wiring metal film 18 is formed. In this embodiment, an Al film (containing 0 to 1% of Cu) having a tensile stress of 0.2 GPa is deposited with a film thickness of 4 μm by a sputtering method.

  Generally, the thickness of the first wiring metal film 18 is about 0.75 μm for a 300 mm wafer and about 1.5 μm for a 200 mm wafer, as shown in FIG. In this embodiment using the second stress relaxation film 19, the stress relaxation effect is substantially effective when the thickness of the first wiring metal film 18 is 1.5 μm or more. The film thickness of the first wiring metal film 18 is preferably 10 μm or less from the viewpoint of wafer cracking and film peeling.

Next, as shown in FIG. 17, a second stress relaxation film 19 having a compressive stress which is an opposite stress to the first wiring metal film 18 is deposited. In this embodiment, an amorphous carbon film having a compressive stress of 0.3 GPa is formed with a thickness of 2 μm by plasma CVD. The processing conditions during the formation were such that a mixed gas of C ₂ H ₂ gas, He gas, and N ₂ was used as a source gas, and a film forming temperature range of 350 to 480 ° C. was used.

  The compressive stress and the film thickness required for the second stress relaxation film 19 are determined by the tensile stress and the film thickness of the first wiring metal film 18, but the film thickness is 30 nm or more due to the thin film formation and processing accuracy. The dimension that can be processed by etching or the like is preferably 4 μm or less. Further, the value of the compressive stress is preferably 0.05 GPa or more in order to control the wafer warp, and 4 GPa or less is preferable in consideration of film peeling. Since the second stress relaxation film 19 is deposited on the upper surface side of the first wiring metal film 18, in the case of an insulating film having a relatively small compressive stress such as an amorphous carbon film, the film thickness is increased. By doing so, the effect of suppressing the amount of warpage of the wafer can be obtained. In this embodiment, since the wafer warp amount is reduced by only one layer of the second stress relaxation film 19, the second stress relaxation film 19 is formed with a film thickness larger than that of the second embodiment. Yes.

Next, the first wiring metal film 18 and the second stress relaxation film 19 are patterned into the same planar shape by a known photolithography technique and etching technique, and the device of the present invention shown in FIG. 14 is manufactured. Here, the second stress relaxation film 19 can be used as a hard mask during the etching of the first wiring metal film 18. Further, the second stress relaxation film 19 of the amorphous carbon film can be removed at the same time as the resist removal by O ₂ ashing. In the device of the present invention shown in FIG. 14, illustration of a protective film and the like formed on the first wiring metal film 18 after patterning is omitted.

  As described above, the device of the present invention is manufactured through the steps shown in FIGS. According to the present embodiment, since the second stress relaxation film 19 having a compressive stress is formed on the first wiring metal film 18 having a tensile stress, the warpage of the wafer due to the compressive stress of the second stress relaxation film 19 is reduced. Since the warpage of the wafer due to the tensile stress of the first wiring metal film 18 is reversed and cancels out, the warpage of the wafer is suppressed. In the present embodiment, the amount of wafer warpage can be suppressed to 60 μm or less. As a result, it is possible to prevent the occurrence of adsorption failure in the wafer transfer system.

  Next, another embodiment of the device of the present invention will be described.

  <1> In the first and second embodiments, the case where a silicon nitride film (SiN film) is used as the first stress relaxation film 17 has been described. However, the first stress relaxation film 17 is not limited to a silicon nitride film. Alternatively, a SiO film, a SiC film, a SiON film, or a SiCN film that can develop a compressive stress may be used. Further, the film forming conditions of the first stress relaxation film 17 are not limited to the conditions of the above embodiment.

  In the second and third embodiments, the case where an amorphous carbon film is used as the second stress relaxation film 19 has been described. However, the second stress relaxation film 19 expresses compressive stress in addition to the amorphous carbon film. A SiN film, a SiO film, a SiC film, a SiON film, or a SiCN film may be used. Further, the conditions for forming the second stress relaxation film 19 are not limited to the conditions of the above embodiment.

  Furthermore, the film thicknesses of the first stress relaxation film 17 and the second stress relaxation film 19 in each of the above embodiments are not limited to the conditions of the above embodiments.

  <2> In each of the embodiments described above, the case where the first wiring metal film 18 is formed by depositing an Al film (containing 0 to 1% of Cu) by the sputtering method has been described. The film 18 is not limited to the Al film, but is selected according to the electrical characteristics and physical characteristics required for the apparatus of the present invention. For example, W, Ti, Cu, Au, Ag, Mo, etc. It doesn't matter. Since all of these wiring materials have tensile stress, the warpage of the wafer is suppressed in each of the embodiments as in the case of the Al film.

  <3> In each of the above embodiments, the silicon wafer 10 having a diameter of 200 mm is used. However, even when a large silicon wafer having a diameter of 300 mm or more is used, for example, according to each of the above embodiments, the silicon wafer is warped. It is possible to suppress the occurrence of adsorption failure in the wafer transfer system.

  <4> In the above embodiments, the underlying structure of the first wiring metal film 18 and the first or second stress relaxation films 17 and 19 is formed on the surface of the silicon wafer 10 shown in FIGS. Although a multilayer wiring structure in which MOSFETs as semiconductor elements are formed is assumed, the underlying structure is not limited to the above embodiments, and various modifications are possible.

  For example, the semiconductor element formed on the silicon wafer 10 is not limited to the MOSFET. Further, the number of wiring layers of the multilayer wiring structure is not limited to the above embodiments.

  INDUSTRIAL APPLICABILITY The semiconductor device according to the present invention is used in a semiconductor device and a manufacturing method thereof that can alleviate the warpage of the wafer caused by the tensile stress of the wiring metal film and reduce the problems in the manufacturing process of the semiconductor device due to the warpage of the wafer. Is possible.

Schematic cross-sectional view schematically showing a cross-sectional structure of a main part in the first embodiment of the semiconductor device according to the present invention. Process sectional drawing which shows typically the principal part sectional structure in the middle of the process in 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically the principal part sectional structure in the middle of the process in 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically the principal part sectional structure in the middle of the process in 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically the principal part sectional structure in the middle of the process in 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically the principal part sectional structure in the middle of the process in 1st Embodiment of the manufacturing method of the semiconductor device which concerns on this invention The schematic sectional drawing which shows typically the principal part sectional structure in 2nd Embodiment of the semiconductor device which concerns on this invention. Process sectional drawing which shows typically the principal part cross-section in the middle of the process in 2nd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically the principal part cross-section in the middle of the process in 2nd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically the principal part cross-section in the middle of the process in 2nd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically the principal part cross-section in the middle of the process in 2nd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically the principal part cross-section in the middle of the process in 2nd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically the principal part cross-section in the middle of the process in 2nd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention The schematic sectional drawing which shows typically the principal part sectional structure in 3rd Embodiment of the semiconductor device which concerns on this invention. Process sectional drawing which shows typically the principal part sectional structure in the middle of the process in 3rd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. Process sectional drawing which shows typically the principal part sectional structure in the middle of the process in 3rd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. Process sectional drawing which shows typically the principal part sectional structure in the middle of the process in 3rd Embodiment of the manufacturing method of the semiconductor device which concerns on this invention. Diagram showing the relationship between the amount of warpage of the silicon wafer and the thickness of the metal film for wiring Schematic sectional view schematically showing an example of a sectional structure of a main part of a conventional semiconductor device

Explanation of symbols

10: Silicon wafer (semiconductor substrate)
11: Device isolation film 12: Gate oxide film 13: Gate electrodes 14a to 14c: Vias 15a to 15c: Interlayer insulating films 16a and 16b: Metal wiring layer 17: First stress relaxation film 18: Metal film for first wiring 19: Second stress relaxation film 20: Insulating film for stress relaxation (substrate stress relaxation film)

Claims (22)

A semiconductor device comprising a semiconductor substrate on which a semiconductor element is formed, and one or a plurality of wiring metal films deposited on the semiconductor substrate,
Among the one or more layers of wiring metal films, at least one of the lower layer side and the upper layer side of the first wiring metal film in which the absolute value of the amount of wafer warpage caused by the deposition of one wiring metal film is maximized. On the side, provided with a stress relaxation film that relaxes the amount of warpage of the wafer,
The stress relaxation film has a compressive stress, and the first wiring metal film has a tensile stress;
2. A semiconductor device according to claim 1, wherein an absolute value of a wafer warp amount caused by the deposition of the stress relaxation film is smaller than an absolute value of a wafer warp amount caused by the deposition of the first wiring metal film.   2. The semiconductor according to claim 1, wherein an absolute value of a wafer warp amount caused by the deposition of the first wiring metal film is equal to or greater than an upper limit value of a wafer warp amount causing a problem in a semiconductor device manufacturing process. apparatus.   When the stress relaxation film is formed as a first stress relaxation film on the lower layer side of the first wiring metal film, the compressive stress of the first stress relaxation film is in a range of 0.5 GPa or more and 4 GPa or less. The semiconductor device according to claim 1 or 2.   When the stress relaxation film is formed as a first stress relaxation film on the lower layer side of the first wiring metal film, the thickness of the first stress relaxation film is in the range of 30 nm to 1 μm. The semiconductor device according to claim 1.   When the stress relaxation film is formed as a first stress relaxation film on the lower layer side of the first wiring metal film, the first stress relaxation film is composed of a SiO film, a SiN film, a SiON film, a SiC film, and a SiOC. The semiconductor device according to claim 1, wherein the semiconductor device is any one of the films.   When the stress relaxation film is formed as a second stress relaxation film on the upper layer side of the first wiring metal film, the compressive stress of the second stress relaxation film is in a range of 0.05 GPa or more and 4 GPa or less. The semiconductor device according to claim 1, wherein:   When the stress relaxation film is formed as a second stress relaxation film on the upper layer side of the first wiring metal film, the thickness of the second stress relaxation film is in the range of 30 nm to 4 μm. The semiconductor device according to any one of claims 1 to 6.   When the stress relaxation film is formed as a second stress relaxation film on the upper layer side of the first wiring metal film, the second stress relaxation film is an SiO film, an SiN film, an SiON film, an SiC film, an SiOC film, The semiconductor device according to claim 1, wherein the semiconductor device is any one of amorphous carbon films.   9. The semiconductor device according to claim 1, wherein a film thickness of the metal film for the first wiring is in a range of 0.75 μm to 10 μm.   The material for the first wiring metal film is a metal containing any one element of Al, W, Ti, Cu, Au, Ag, and Mo. 2. A semiconductor device according to item 1.   When the stress relaxation film is formed as a first stress relaxation film on the lower layer side of the first wiring metal film, the first stress relaxation film and the first wiring metal film are patterned in the same planar shape. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.   When the stress relaxation film is formed as a second stress relaxation film on the upper layer side of the first wiring metal film, the second stress relaxation film and the first wiring metal film are patterned in the same planar shape. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.   13. The semiconductor device according to claim 1, wherein the first wiring metal film is an uppermost layer of the one or more wiring metal films. A method of manufacturing a semiconductor device comprising a semiconductor substrate on which a semiconductor element is formed, and one or more layers of wiring metal films deposited on the semiconductor substrate,
Of the one or more wiring metal films, at least one of the lower layer side and the upper layer side of the first wiring metal film that maximizes the absolute value of the amount of wafer warp caused by the deposition of one wiring metal film. On one side, a stress relaxation film forming step of depositing a stress relaxation film that relaxes the amount of warpage of the wafer,
In the stress relaxation film forming step, the stress relaxation film has a compressive stress, and an absolute value of a wafer warpage amount caused by the deposition of the stress relaxation film is a wafer warpage amount caused by the deposition of the metal film for the first wiring. A method of manufacturing a semiconductor device, comprising forming the stress relaxation film so as to be smaller than an absolute value.   The stress relaxation film forming step is executed when the absolute value of the amount of wafer warp caused by the deposition of the first wiring metal film is equal to or greater than the upper limit of the amount of wafer warp that causes a problem in the semiconductor device manufacturing process. The method of manufacturing a semiconductor device according to claim 14.   The method of manufacturing a semiconductor device according to claim 14, wherein the stress relaxation film forming step is executed when an absolute value of a wafer warp amount caused by the deposition of the first wiring metal film is 100 μm or more. .   17. The method of manufacturing a semiconductor device according to claim 14, wherein in the stress relaxation film forming step, the stress relaxation film is formed using a plasma CVD method. In the stress relaxation film forming step, when the stress relaxation film is formed as a first stress relaxation film on the lower layer side of the first metal film for wiring,
18. The method of manufacturing a semiconductor device according to claim 14, further comprising a patterning step of patterning the first stress relaxation film and the first wiring metal film in the same planar shape. In the stress relaxation film forming step, when the stress relaxation film is formed as a second stress relaxation film on the upper layer side of the first wiring metal film,
18. The method of manufacturing a semiconductor device according to claim 14, further comprising a patterning step of patterning the second stress relaxation film and the first wiring metal film in the same planar shape. In the stress relaxation film forming step, when the stress relaxation film is formed as a first stress relaxation film and a second stress relaxation film on the lower layer side and the upper layer side of the first wiring metal film,
18. The method according to claim 14, further comprising a patterning step of patterning the first stress relaxation film, the second stress relaxation film, and the first metal film for wiring into the same planar shape. Semiconductor device manufacturing method.   21. The method of manufacturing a semiconductor device according to claim 19, wherein the second stress relaxation film is removed after the patterning step.   The stress relaxation film forming step is performed using the uppermost layer of the one or more wiring metal films as the first wiring metal film. A method for manufacturing a semiconductor device.

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