JP2013074017A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress warp of a semiconductor device and aging variation of the warp.SOLUTION: A semiconductor device comprises a substrate and multilayer wiring layers formed on the substrate. The multilayer wiring layers include a plurality of wiring layers each having wiring and an interlayer insulation film covering the wiring. At least one of the interlayer insulation films (ex., interlayer insulation films 27, 30) has a first insulation film 41 and a second insulation film 42. The first insulation film 41 applies to the substrate, a stress causing the substrate to warp in a first direction (ex., projecting downward). The second insulation film 42 is formed on a surface layer side than the first insulation film 41 and has hygroscopicity lower than that of the first insulation film 41. The second insulation film 42 applies to the substrate, a stress causing the substrate to warp in an opposite direction (ex., projecting upward) to the first direction.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  The semiconductor device includes a substrate and a multilayer wiring layer formed on the substrate. The multilayer wiring layer has an interlayer insulating film. The semiconductor device may warp due to stress caused by the interlayer insulating film.

  Patent Document 1 describes a semiconductor device in which a laminated film of an atmospheric pressure CVD oxide film and a P-SiON (plasma oxynitride film) is provided as an interlayer insulating film to relieve stress caused by the interlayer insulating film. Yes.

Japanese Patent Laid-Open No. 5-109909

The inventor of the present application has recognized the following.
By making the density of the interlayer insulating film sparse, the direction of warpage of the semiconductor device can be controlled. However, when the interlayer insulating film is a sparse film, the interlayer insulating film absorbs moisture, so that the stress changes with time, and the warpage of the semiconductor device also changes with time.

  As described above, it is difficult to suppress the warpage of the semiconductor device and to suppress the change with time of the warpage.

The present invention comprises a substrate;
A multilayer wiring layer formed on the substrate;
Have
The multilayer wiring layer has a plurality of wiring layers each having a wiring and an interlayer insulating film covering the wiring,
At least one of the interlayer insulating films is
A first insulating film that applies stress to the substrate to warp the substrate in a first direction;
A second insulating film formed on a surface layer side of the first insulating film, having a lower hygroscopicity than the first insulating film, and applying a stress to the substrate in a direction opposite to the first direction;
A semiconductor device is provided.

According to this semiconductor device, at least one of the interlayer insulating films is formed on the surface layer side of the first insulating film and the first insulating film that gives the substrate a stress that warps the substrate in the first direction. And a second insulating film that applies stress to the substrate in a direction opposite to the one direction. Therefore, warpage of the semiconductor device can be suppressed by canceling out the stress caused by the first insulating film and the stress caused by the second insulating film.
Further, since the second insulating film has lower hygroscopicity than the first insulating film, it is possible to suppress moisture absorption of the second insulating film. Moreover, since the second insulating film is formed on the surface layer side of the first insulating film, the second insulating film can also suppress moisture absorption of the first insulating film. For this reason, it can suppress that the stress resulting from a 2nd insulating film changes with time, and can also suppress that the stress resulting from a 1st insulating film changes with time. Therefore, it is possible to suppress the change with time of the warpage of the semiconductor device.
As described above, the warpage of the semiconductor device can be suppressed, and the change with time of the warpage can be suppressed.

Further, the present invention includes a step of forming a multilayer wiring layer including a plurality of wiring layers each having a wiring and an interlayer insulating film covering the wiring on a substrate,
Forming at least one of the interlayer insulating films,
Forming a first insulating film that imparts stress to the substrate to warp the substrate in a first direction;
Forming a second insulating film on the surface layer side of the first insulating film, the second insulating film being less hygroscopic than the first insulating film and applying stress to the substrate in a direction opposite to the first direction; ,
A method for manufacturing a semiconductor device is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the curvature of a semiconductor device can be suppressed and the time-dependent change of the curvature can be suppressed.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is a figure which shows a series of processes of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows a series of processes of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows a series of processes of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing of the semiconductor device which concerns on 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

[First Embodiment]
1 and 2 are cross-sectional views of the semiconductor device according to the first embodiment. FIG. 1 is a diagram showing the structure of at least one wiring layer of the multilayer wiring layer 4 shown in FIG.

  As described above, the semiconductor device may warp due to the stress caused by the interlayer insulating film. In this case, the warp becomes more prominent as the interlayer insulating film is thicker.

  Here, it has been found by the inventors that even if the insulating film is formed thick, the warp of the semiconductor device can be controlled by reducing the film quality. However, it has also been found that when the insulating film is made sparse, the change with time of the warp appears remarkably due to moisture absorption of the insulating film. Therefore, the present inventor has conceived that the change with time of the warpage of the semiconductor device can be suppressed by suppressing the moisture absorption of the sparse insulating film.

  The semiconductor device according to the present embodiment includes a substrate (semiconductor substrate 1 (hereinafter simply referred to as substrate 1)) and a multilayer wiring layer 4 formed on the substrate 1. The multilayer wiring layer 4 has a plurality of wiring layers each having a wiring and an interlayer insulating film covering the wiring. At least one of the interlayer insulating films (for example, the interlayer insulating films 27 and 30) includes a first insulating film 41 and a second insulating film 42. The first insulating film 41 gives the substrate 1 a stress that warps the substrate 1 in a first direction (for example, convex downward). The second insulating film 42 is formed on the surface layer side of the first insulating film 41, has a lower hygroscopicity than the first insulating film 41, and stresses the substrate 1 to warp in the opposite direction to the first direction (for example, convex upward). Is applied to the substrate 1. Details will be described below.

  As shown in FIG. 2, the semiconductor device according to this embodiment includes a semiconductor substrate (substrate) 1 on which an element isolation film 2 is formed, a MOS transistor 3 formed in an element formation region of the semiconductor substrate 1, and an element isolation. A multilayer wiring layer 4 formed on the film 2 and the MOS transistor 3 and a protective insulating film 5 formed on the multilayer wiring layer 4 are included.

  The element isolation film 2 may be formed using the STI method, or may be formed using the LOCOS method.

  The MOS transistor 3 includes a gate insulating film, a gate electrode, a sidewall formed on the sidewall of the gate electrode, an impurity region (source and drain) formed in the semiconductor substrate 1, an extension region of the source and drain, Have

  The multilayer wiring layer 4 is configured by stacking a plurality of wiring layers. Although the number of wiring layers included in the multilayer wiring layer 4 is arbitrary, FIG. 2 shows an example in which there are seven wiring layers.

  The lowermost layer of the multilayer wiring layer 4 is a contact layer. The contact layer has a contact interlayer insulating film 11 formed on the element isolation film 2 and the MOS transistor 3 and a contact 12 formed on the contact interlayer insulating film 11. The contact 12 is made of a metal such as tungsten, for example.

  A first wiring layer is formed on the contact interlayer insulating film 11 and the contact 12. The first wiring layer includes a wiring interlayer insulating film 13 formed on the contact interlayer insulating film 11 and the contact 12, and a first wiring 14 embedded in the wiring interlayer insulating film 13. . The first wiring 14 is made of a metal such as copper, for example.

  An interlayer insulating film 15 is formed on the wiring interlayer insulating film 13 and the first wiring 14. A via 16 is embedded in the interlayer insulating film 15.

  The second wiring layer includes a second wiring 17 formed on the interlayer insulating film 15 and the via 16, an interlayer insulating film 18 covering the second wiring 17, and a via 19 formed in the interlayer insulating film 18. ,have.

  The third wiring layer includes a third wiring 20 formed on the second wiring layer, an interlayer insulating film 21 covering the third wiring 20, and a via 22 formed in the interlayer insulating film 21. Have.

  The fourth wiring layer includes a fourth wiring 23 formed on the third wiring layer, an interlayer insulating film 24 covering the fourth wiring 23, and a via 25 formed in the interlayer insulating film 24. Have.

  The fifth wiring layer includes a fifth wiring 26 formed on the fourth wiring layer, an interlayer insulating film 27 covering the fifth wiring 26, and a via 28 formed in the interlayer insulating film 27. Have.

  The sixth wiring layer includes a sixth wiring 29 formed on the fifth wiring layer, an interlayer insulating film 30 covering the sixth wiring 29, and a via 31 formed in the interlayer insulating film 30. Have.

  The uppermost wiring layer has a seventh wiring 32 formed on the sixth wiring layer. A part of the seventh wiring 32 functions as an electrode pad.

The second to seventh wirings 17, 20, 23, 26, 29, and 32 are each configured by patterning a metal film such as AlCu.
The vias 16, 19, 22, 25, 28, and 31 are each made of a metal such as tungsten.
However, the via may be integrally formed of the same material as the wiring.

  The protective insulating film 5 is a laminated film of, for example, a SiN / SiO film 6 and a polyimide film 7. The protective insulating film 5 has an opening 5a that exposes the electrode pad.

  The semiconductor device has, for example, an IC unit 51 and a transformer unit 52. The transformer unit 52 includes a primary coil 53 and a secondary coil 54. For example, the primary coil 53 is configured by a part of the seventh wiring 32, and the secondary coil 54 is configured by a part of the third wiring 20.

  In the semiconductor device according to the present embodiment, for example, each of the upper fifth wiring layer and the sixth wiring layer in the multilayer wiring layer 4 of FIG. 2 has a layer structure as shown in FIG. Yes. With such a layer structure, as will be described in detail below, it is possible to suppress the warpage of the semiconductor device and to suppress the change with time of the warpage.

As shown in FIG. 1, each of the wiring layers of the fifth layer and the sixth layer includes, for example, a wiring 44, a first insulating film 41 that covers the wiring 44, and a moisture absorption preventing film 43 that covers the first insulating film 41. And a second insulating film 42 that covers the moisture absorption preventing film 43.
Here, the fifth wiring 26 in FIG. 2 corresponds to the wiring 44 in FIG. 1. The sixth wiring 29 in FIG. 2 also corresponds to the wiring 44 in FIG.
The interlayer insulating film 27 in FIG. 2 corresponds to a three-layered film of the first insulating film 41, the moisture absorption preventing film 43, and the second insulating film 42 in FIG. The interlayer insulating film 30 in FIG. 2 also corresponds to the three-layered film of the first insulating film 41, the moisture absorption preventing film 43, and the second insulating film 42 in FIG.

  The first insulating film 41 is a sparse film having a lower density than the second insulating film 42. The first insulating film 41 gives the substrate 1 a stress that warps the substrate 1 downward.

  The second insulating film 42 is a dense film having a higher density than the first insulating film 41 and has a lower hygroscopic property than the first insulating film 41. The second insulating film 42 is located closer to the surface layer side of the semiconductor device than the first insulating film 41. The second insulating film 42 gives the substrate 1 a stress that causes the substrate 1 to warp upward.

  As described above, the stress applied to the substrate 1 by the first insulating film 41 and the stress applied to the substrate 1 by the second insulating film 42 are opposite to each other. Therefore, the stress applied to the substrate 1 by the first insulating film 41 and the stress applied to the substrate 1 by the second insulating film 42 can be offset to suppress the warpage of the substrate 1 and thus the warp of the entire semiconductor device.

  The film thickness of the first insulating film 41 and the film thickness of the second insulating film 42 are set so that the warpage of the substrate 1 and thus the warpage of the entire semiconductor device is minimized.

  In addition, since the second insulating film 42 having a lower hygroscopicity than the first insulating film 41 is formed on the surface layer side of the first insulating film 41, the second insulating film 42 has the second insulating film 42 itself. Not only can moisture absorption be suppressed, but the second insulating film 42 can also suppress moisture absorption of the first insulating film 41. For this reason, it can suppress that the stress resulting from the 2nd insulating film 42 changes with time by moisture absorption, and can also suppress that the stress resulting from the 1st insulating film 41 changes with time by moisture absorption. Therefore, it is possible to suppress the change with time of the warpage of the semiconductor device.

The first and second insulating films 41 and 42 each have the same dielectric constant as that of SiO ₂ or less.

The first insulating film 41 is, for example, a SiO ₂ based film. More specifically, the first insulating film 41 is, for example, any one of SiO ₂ , SiO, SiOF, PSG (Phospho Silicate Glass), and BPSG (Boro-Phospho Silicate Glass).
Similarly, the second insulating film 42 is, for example, a SiO ₂ -based film, and more specifically, for example, any one of SiO ₂ , SiO, SiOF, PSG, and BPSG.
Specifically, for example, the first insulating film 41 and the second insulating film 42 can be SiO ₂ films, respectively.

  For example, in order for a semiconductor device to perform non-contact communication between two different voltages, a thick interlayer insulating film is required. For this reason, for example, the total film thickness of the first insulating film 41 and the second insulating film 42 is set to an appropriate film thickness that enables such non-contact communication.

The moisture absorption preventing film 43 is a SiON film (oxynitride film) well known as a moisture absorption preventing film. More specifically, the moisture absorption preventing film 43 is, for example, a P-SiON film (plasma oxynitride film).
The moisture absorption preventing film 43 is not limited to a SiON film, but may be a SiN film (for example, a P—SiN film) or a SiC film (for example, a P—SiC film).

Note that the interlayer insulating film having the layer structure shown in FIG. 1 may be formed on any one of a local layer, an intermediate layer, a semi-global layer, and a global layer. However, the interlayer insulating film of the relatively thick global layer (for example, the above-described fifth and sixth wiring layers) or the semi-global layer of the interlayer insulating film has the layer structure shown in FIG. Therefore, the warp of the semiconductor device can be more effectively suppressed.
Here, the global layer means a layer in which wirings for connecting elements are not arranged, and power lines, GND lines, wirings for connecting circuits and electrode pads, or the like are arranged.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. 3 to 5 are diagrams showing a series of steps of this manufacturing method. 3A to 5A, FIG. 3A is a cross-sectional view of a semiconductor device, and FIG. 3B is a schematic diagram illustrating a warped shape of a wafer in each process.

  The method for manufacturing a semiconductor device according to the present embodiment includes a step of forming a multilayer wiring layer 4 including a plurality of wiring layers each having a wiring and an interlayer insulating film covering the wiring on the substrate 1. The step of forming at least one interlayer insulating film includes a step of forming a first insulating film 41 that applies stress to the substrate 1 to warp the substrate 1 in the first direction, and a surface layer side of the first insulating film 41. Forming a second insulating film 42 that has lower hygroscopicity than the first insulating film 41 and applies a stress to the substrate 1 that causes the substrate 1 to warp in a direction opposite to the first direction. Details will be described below.

  First, as shown in FIG. 2, an element isolation film 2 is formed on a semiconductor substrate 1. Thereby, the element formation region is separated. The element isolation film 2 is formed using, for example, the STI method, but may be formed using the LOCOS method.

  Next, a gate insulating film and a gate electrode are formed on the semiconductor substrate 1 located in the element formation region. The gate insulating film may be a silicon oxide film or a high dielectric constant film (for example, a hafnium silicate film) having a higher dielectric constant than that of the silicon oxide film. When the gate insulating film is a silicon oxide film, the gate electrode is formed of a polysilicon film. When the gate insulating film is a high dielectric constant film, the gate electrode is formed of a laminated film of a metal film (for example, TiN) and a polysilicon film. When the gate electrode is formed of polysilicon, a polysilicon resistor may be formed on the element isolation film in the step of forming the gate electrode.

  Next, source and drain extension regions are formed in the semiconductor substrate located in the element formation region. Next, sidewalls are formed on the sidewalls of the gate electrode. Next, impurity regions serving as a source and a drain are formed in a semiconductor substrate located in the element formation region. In this way, the MOS transistor 3 is formed on the semiconductor substrate.

  Next, the multilayer wiring layer 4 is formed on the element isolation film 2 and the MOS transistor 3.

  First, a contact interlayer insulating film 11 is formed on the element isolation film 2 and the MOS transistor 3, and a contact 12 is embedded in the contact interlayer insulating film 11.

  Next, a wiring interlayer insulating film 13 is formed on the contact interlayer insulating film 11 and the contact 12. Next, a wiring groove is formed in the wiring interlayer insulating film 13, a metal such as copper is embedded in the wiring groove, and excess metal is removed by CMP (Chemical Mechanical Polishing) or the like. Thereby, the first wiring 14 can be embedded in the wiring trench.

  Next, an interlayer insulating film 15 is formed on the wiring interlayer insulating film 13 and the first wiring 14. Next, a via hole is formed in the interlayer insulating film 15, and a metal such as tungsten is embedded in the via hole. Next, excess metal is removed by CMP or etchback. Thereby, the via 16 can be embedded in the via hole.

  Next, a metal film such as AlCu is formed on the interlayer insulating film 15 and the via 16 by sputtering on the entire surface, and then a mask pattern is formed by photolithography. Next, the metal film is etched into the second wiring 17 having a desired pattern shape by etching the metal film using this mask pattern as a mask.

  Next, an interlayer insulating film 18 is formed on the interlayer insulating film 15 so as to cover the side surface and the upper surface of the second wiring 17. Next, a via hole is formed in the interlayer insulating film 18, a metal such as tungsten is embedded in the via hole, and excess metal is removed by CMP or etchback, thereby forming a via 19 in the via hole.

  Thereafter, like the second wiring layer, the third wiring layer (third wiring 20, interlayer insulating film 21 and via 22) and the fourth wiring layer (fourth wiring 23, interlayer insulating film 24 and Vias 25) are formed sequentially.

  Next, after a metal film such as AlCu is formed on the fourth wiring layer by sputtering or the like, a mask pattern is formed by photolithography, and the metal film is etched using the mask pattern as a mask. The metal film is processed into the fifth wiring 26 having a desired pattern shape.

Next, an interlayer insulating film 27 is formed on the interlayer insulating film 24 so as to cover the side surfaces and the upper surface of the fifth wiring 26. Next, a via hole is formed in the interlayer insulating film 27.
Next, after a metal film such as AlCu is formed by whole surface sputtering or the like, a mask pattern is formed by photolithography, and the metal film is etched using the mask pattern as a mask. Thus, the sixth wiring 29 and the via 28 having a desired pattern shape are collectively formed.

  Next, an interlayer insulating film 30 is formed on the interlayer insulating film 27 so as to cover the vias 28 and the side surfaces and the upper surface of the sixth wiring 26. Next, after forming a via hole in the interlayer insulating film 30, the seventh wiring 32 and the via 31 are formed by the same method as that for forming the sixth wiring 29 and the via 28.

  In this way, the multilayer wiring layer 4 can be formed.

Next, a protective insulating film (passivation film) 5 is formed on the multilayer wiring layer 4. First, the SiN / SiO film 6 is formed so as to cover the seventh wiring 32, and the polyimide film 7 is further formed so as to cover the SiN / SiO film 6.
A part of the seventh wiring 32 constitutes an electrode pad. In the protective insulating film 5, an opening 5 a located on the electrode pad is formed.

  Here, the interlayer insulating films (for example, the interlayer insulating film 27 and the interlayer insulating film 30 of the fifth and sixth wiring layers) of at least a part of the wiring layers of the multilayer wiring layer 4 are respectively described below. It is formed by the process of.

  First, the manufacturing process of the fifth wiring layer will be described with reference to FIGS.

After the fifth wiring 26 is formed as described above, the SiO ₂ -based first layer is formed on the fifth wiring 26 and the fourth wiring layer so as to cover the side surface and the upper surface of the fifth wiring 26 (wiring 44). 1 Insulating film 41 is formed.

  As described above, the first insulating film 41 gives the substrate 1 a stress that causes the substrate 1 to warp downward. For this reason, at this stage, the wafer is in a state along a downward projection (not shown).

  Next, a moisture absorption preventing film 43 is formed so as to cover the first insulating film 41.

Next, a second insulating film lower portion 42a that is a lower portion (lower layer) of the SiO ₂ -based second insulating film 42 is formed so as to cover the moisture absorption preventing film 43 (FIG. 3A).

In the SiO ₂ film, the stress changes depending on the film density, and when the dense film is formed on the wafer, the wafer warps upward, and when the sparse film is formed, the wafer warps concavely (convex downward).

  As shown in FIG. 3A, immediately after the second insulating film lower portion 42a is formed, the influence of the stress caused by the second insulating film lower portion 42a is strong. Therefore, as shown in FIG. Slightly warps upwards.

  As shown in FIG. 3A, the first insulating film 41, the moisture absorption preventing film 43, and the second insulating film lower part 42a are formed with raised portions 45 reflecting the shape of the fifth wiring 26. Yes.

Next, as shown in FIG. 4A, the upper surface of the second insulating film lower portion 42a is planarized by CMP. At this time, the moisture absorption preventing film 43 in the raised portion 45 functions as a stopper film. For example, CMP is performed until the moisture absorption preventing film 43 in the raised portion 45 is exposed on the surface. That is, the upper surface of the lower layer of the second insulating film is planarized by CMP using the moisture absorption preventing film 43 as a stopper film.
Since the moisture absorption preventing film 43 functions as a stopper film, exposure of the first insulating film 41 due to over polishing can be suppressed.
By performing CMP in this way, the second insulating film lower part 42a is removed in the formation region of the fifth wiring 26 and its edge (that is, on the raised portion 45), and the region excluding the fifth wiring 26 and its edge. In other words, the second insulating film lower portion 42a remains in the region other than the raised portion 45.

  At this stage, since the film thickness of the second insulating film lower part 42a is reduced as compared with the state of FIG. 3A, the wafer is slightly concave (convex downward) as shown in FIG. 4B. Warp.

Next, as shown in FIG. 5A, a second insulating film upper portion 42 b that is an upper portion (upper layer) of the second insulating film 42 is formed on the second insulating film lower portion 42 a and the raised portion 45. Note that the purpose of forming the second insulating film upper portion 42b includes anti-scratch measures (filling holes formed by CMP) and film thickness adjustment of the interlayer insulating film.
By forming the second insulating film upper part 42b, the second insulating film 42 composed of the second insulating film lower part 42a and the second insulating film upper part 42b is formed.

  Here, the total film thickness of the first insulating film 41 and the second insulating film 42 is set to a desired film thickness of the interlayer insulating film. Moreover, each of the first insulating film 41 and the second insulating film 42 is such that the stress of the first insulating film 41 and the stress of the second insulating film 42 cancel each other and the warpage of the wafer becomes substantially zero. Adjust the thickness.

  At this stage, the stress between the first insulating film 41 and the second insulating film 42 is canceled out, so that the warpage of the wafer becomes substantially zero as shown in FIG.

  The manufacturing process of the sixth wiring layer is the same as the manufacturing process of the fifth wiring layer.

According to the first embodiment as described above, at least one of the interlayer insulating films of the semiconductor device includes the first insulating film 41 that applies stress to the substrate 1 to warp the substrate 1 in the first direction, and the first insulating film. A second insulating film that is formed on the surface layer side of the film 41 and applies a stress to the substrate 1 to warp the substrate 1 in a direction opposite to the first direction. Therefore, the warpage of the semiconductor device can be suppressed by canceling out the stress caused by the first insulating film 41 and the stress caused by the second insulating film 42.
Further, since the second insulating film 42 has lower hygroscopicity than the first insulating film 41, the second insulating film 42 can suppress moisture absorption. In addition, since the second insulating film 42 is formed on the surface layer side of the first insulating film 41, the second insulating film 42 can also suppress moisture absorption of the first insulating film 41. For this reason, it can suppress that the stress resulting from the 2nd insulating film 42 changes with time, and can also suppress that the stress resulting from the 1st insulating film 41 changes with time. Therefore, it is possible to suppress the change with time of the warpage of the semiconductor device.
As described above, the warpage of the semiconductor device can be suppressed, and the change with time of the warpage can be suppressed.

  Since the warpage of the semiconductor device can be suppressed, for example, when the semiconductor device is transported in the device, it is possible to reduce the occurrence of a problem that the warpage is hindered due to the warpage.

By the way, as a method for suppressing the warpage of the wafer, after forming a film on the front surface of the wafer, a uniform film is also formed on the back surface. A method of keeping the wafer flat by canceling out the above can be considered. However, in this method, since it is necessary to finally remove the film on the back surface, warpage is exhibited at the stage of completion of the wafer.
On the other hand, in the present embodiment, since film formation for suppressing the warpage of the wafer is performed on the wafer surface, film formation on the back surface for canceling stress is not required. It is not necessary to remove the film, and it is possible to prevent the wafer from being warped.

  By making the second insulating film 42 a film having a higher density than the first insulating film 41, the hygroscopicity of the second insulating film 42 can be made lower than that of the first insulating film 41.

Further, the moisture absorption preventing film 43 is formed between the first insulation film 41 and the second insulation film 42, that is, the first insulation film 41 is covered with the moisture absorption prevention film 43, thereby the first insulation film. The contact between 41 and the outside air can be suppressed, and the first insulating film 41 can be prevented from absorbing moisture. Thereby, since the time-dependent change of the stress resulting from the 1st insulating film 41 can be suppressed further, the time-dependent change of the curvature of a semiconductor device can also be suppressed further.
Thus, by covering the first insulating film 41 with the moisture absorption preventing film 43, even if a highly hygroscopic film is used as the first insulating film 41, moisture absorption by the first insulating film 41 can be suppressed. The choice of the material of the insulating film 41 can be expanded.

  Alternatively, the semiconductor device is formed on the surface layer side with respect to the first insulating film 41 that gives stress to warp the substrate 1 in the first direction and the moisture absorption preventing film 43 (that is, formed on the surface layer side with respect to the first insulating film 41). And a second insulating film 42 that applies stress to the substrate 1 to warp the substrate 1 in the opposite direction to the first direction. Therefore, the warpage of the semiconductor device can be suppressed by canceling out the stress caused by the first insulating film 41 and the stress caused by the second insulating film 42.

[Second Embodiment]
FIG. 6 is a cross-sectional view of a semiconductor device according to the second embodiment. The semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment only in the points described below, and is otherwise configured in the same manner as the semiconductor device according to the first embodiment. Yes. The semiconductor device manufacturing method according to the present embodiment is different from the semiconductor device manufacturing method according to the first embodiment only in the points described below, and the other points are related to the first embodiment. This is the same as the semiconductor device manufacturing method.

  As shown in FIG. 6, in the case of the present embodiment, before the first insulating film 41 is formed, a third insulating film 46, which is a dense thin film having a lower hygroscopic property than the first insulating film 41, is formed. The wiring 44 and the first insulating film 41 are not in contact with each other. The third insulating film 46 is formed so as to cover the wiring 44 and a base of the wiring 44 (for example, a wiring layer located under the wiring 44). The material of the third insulating film 46 is the same as the material of the second insulating film 42, for example.

  That is, in the present embodiment, at least one of the interlayer insulating films (for example, the interlayer insulating films 27 and 30) is further less hygroscopic than the first insulating film 41, and the wiring 44 (for example, the fifth wiring) 26, the sixth wiring 29), and the first insulating film 41 is formed on the surface layer side of the third insulating film 46.

With this structure, even if the first insulating film 41 absorbs moisture for some reason, it is possible to prevent water molecules in the first insulating film 41 from coming into contact with the wiring 44, so that the corrosion of the wiring 44 can be suppressed. it can.
Therefore, the reliability of the semiconductor device can be improved as compared with the structure of the first embodiment.

1 Semiconductor substrate (substrate)
2 element isolation film 3 MOS transistor 4 multilayer wiring layer 5 protective insulating film 5a opening 6 SiN / SiO film 7 polyimide film 11 contact interlayer insulating film 12 contact 13 wiring interlayer insulating film 14 first wiring 15 interlayer insulating film 16 via 17 second Wiring 18 Interlayer insulating film 19 Via 20 Third wiring 21 Interlayer insulating film 22 Via 23 Fourth wiring 24 Interlayer insulating film 25 Via 26 Fifth wiring 27 Interlayer insulating film 28 Via 29 Sixth wiring 30 Interlayer insulating film 31 Via 32 7th Wiring 41 1st insulating film 42 2nd insulating film 42a 2nd insulating film lower part 42b 2nd insulating film upper part 43 Moisture absorption prevention film 44 Wiring 45 Raised part 46 3rd insulating film 51 IC part 52 Transformer 53 Primary coil 54 Secondary coil

Claims (12)

A substrate,
A multilayer wiring layer formed on the substrate;
Have
The multilayer wiring layer has a plurality of wiring layers each having a wiring and an interlayer insulating film covering the wiring,
At least one of the interlayer insulating films is
A first insulating film that applies stress to the substrate to warp the substrate in a first direction;
A second insulating film formed on a surface layer side of the first insulating film, having a lower hygroscopicity than the first insulating film, and applying a stress to the substrate in a direction opposite to the first direction;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the second insulating film is a film having a higher density than the first insulating film. 3. The semiconductor device according to claim 1, wherein the first and second insulating films have a dielectric constant equal to or lower than that of SiO ₂ . 4. The semiconductor according to claim 1, wherein each of the first and second insulating films is any one of SiO ₂ , SiO, SiOF, PSG, and BPSG. 5. apparatus.   5. The semiconductor device according to claim 1, wherein a moisture absorption preventing film is formed between the first insulating film and the second insulating film. 6.   The semiconductor device according to claim 5, wherein the moisture absorption prevention film is any one of SiON, SiN, and SiC.   The semiconductor device according to claim 6, wherein the SiON is P-SiON, the SiN is P-SiN, and the SiC is P-SiC. The at least one of the interlayer insulating films further includes:
A third insulating film that is less hygroscopic than the first insulating film and covers the wiring;
The semiconductor device according to claim 1, wherein the first insulating film is formed on a surface layer side with respect to the third insulating film.   The semiconductor device according to claim 1, wherein the at least one interlayer insulating film is located in a global layer. Forming a multilayer wiring layer including a plurality of wiring layers each having a wiring and an interlayer insulating film covering the wiring on the substrate;
Forming at least one of the interlayer insulating films,
Forming a first insulating film that imparts stress to the substrate to warp the substrate in a first direction;
Forming a second insulating film on the surface layer side of the first insulating film, the second insulating film being less hygroscopic than the first insulating film and applying stress to the substrate in a direction opposite to the first direction; ,
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming a moisture absorption preventing film between the first insulating film and the second insulating film.   The step of forming the second insulating film includes a step of forming a lower layer of the second insulating film, a step of flattening an upper surface of the lower layer of the second insulating film, and a step of forming an upper layer of the second insulating film. Forming an upper layer of the second insulating film, and in the step of flattening the upper surface of the lower layer of the second insulating film, the lower layer of the second insulating film using the moisture absorption preventing film as a stopper film. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the upper surface of the lower layer of the second insulating film is planarized by CMP.

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