KR20090047130A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20090047130A
KR20090047130A KR1020070113152A KR20070113152A KR20090047130A KR 20090047130 A KR20090047130 A KR 20090047130A KR 1020070113152 A KR1020070113152 A KR 1020070113152A KR 20070113152 A KR20070113152 A KR 20070113152A KR 20090047130 A KR20090047130 A KR 20090047130A
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KR
South Korea
Prior art keywords
fuse
semiconductor device
forming
interlayer insulating
protective film
Prior art date
Application number
KR1020070113152A
Other languages
Korean (ko)
Inventor
윤희용
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070113152A priority Critical patent/KR20090047130A/en
Publication of KR20090047130A publication Critical patent/KR20090047130A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive

Abstract

The present invention relates to a method of manufacturing a semiconductor device that can prevent the warpage of the substrate during the packaging process, the method for manufacturing a semiconductor device of the present invention, a substrate having a die region and a scribe lane region Forming a stress relaxation layer thereon; Forming a fuse on the stress relaxation layer; Forming an interlayer insulating film on the fuse; Forming a protective film on the interlayer insulating film; A repair etching step of selectively etching the passivation layer on the fuse; Removing the protective film remaining on the scribe lane region and performing the backgrounding process while etching the interlayer insulating film to a predetermined thickness on the fuse. By removing the protective film causing the crack in the rain region, and remaining the stress relaxation layer, it is possible to alleviate the tensile stress of the substrate generated during the background grounding, thereby reducing the phenomenon that the substrate is bent.

Scriberain, die, warping, backgrounding

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of preventing substrate warpage from occurring during a packaging process.

Packaging technology for integrated circuit chips continues to evolve in the semiconductor industry. In particular, with the development of information and communication in recent years, efforts have been made to develop small and lightweight multi-functional packages. As part of this effort, a multi chip package (MCP) has been proposed.

Multi-chip package is to increase the memory capacity by stacking memory chips of the same function, or to maximize the performance and efficiency of the product by assembling different types of semiconductor chips with different functions into one package. To reduce, a package is fabricated using a method of packaging two or more semiconductor chips in a stacked structure.

In order to further reduce the mounting area of such a multi-chip package, that is, to stack more chips in a limited space, a method of reducing the thickness of the chip by grinding the back side of the substrate on which the structure is not formed is called back grinding. I'm using technology. Here, as the thickness of the substrate becomes thin through the background, warpage may occur due to stresses applied to the substrate, in particular, tensile stress.

FIG. 1A is a plan view illustrating a die area and a scribe lane area on a substrate according to the prior art, and FIG. 1B is a cross-sectional view taken along line AA ′, BB ′, CC ′ and DD ′ shown in FIG. 1A. .

Referring to FIGS. 1A and 1B, a method of fabricating a semiconductor device according to the related art may include a plurality of die areas having a fuse area and a pad area, and a scribe lane area having a test pattern area between the die areas. After the predetermined structure is formed on the substrate 11 according to the semiconductor device, the first insulating layer 12 is formed on the substrate 11.

Next, after the fuse 13 is formed on the first insulating film 12 in the fuse region, the second insulating film 14 is formed on the entire surface of the resultant including the fuse 13.

Next, the pad 15 and the test pattern 16 are formed on the second insulating film 14 of the pad region and the test pattern region, respectively. In this case, the test pattern includes an overlay mask for pattern alignment during an exposure process or a structure for measuring an electric parameter monitor (EPM).

Next, after the passivation layer 17 is formed on the entire surface of the resultant including the pad 15 and the test pattern 16, the second insulating layer 14 on the fuse 13 may be left as a target. Repair / pad etching is performed to leave the second insulating layer 14 on the fuse 13 at a predetermined thickness and to expose the surface of the pad 15 and the test pattern 16.

In the above-described conventional technique, when the repair / pad etching process is performed, the scribe lane region may be removed in the process of removing the protective film 17 causing crack in the scribe lane region during die swaing to separate the die region. All of the passivation layer 17, the second insulating layer 14, and the first insulating layer 12 in the remaining regions except for the region where the test pattern 16 is formed are removed. At this time, when backgrounding is performed while the protective film 17, the second insulating film 14, and the first insulating film 12 are all removed, the stress applied to the substrate 11, in particular, the tensile stress is increased. There is a problem that the phenomenon in which the bent 11 is further intensified.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can alleviate the tensile stress of the substrate generated during the background.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a stress relaxation layer on an upper surface of a substrate having a die region and a scribe lane region; Forming a fuse on the stress relaxation layer; Forming an interlayer insulating film on the fuse; Forming a protective film on the interlayer insulating film; A repair etching step of selectively etching the passivation layer on the fuse; Removing the protective film remaining on the scribe lane region and performing a backgrounding process while etching the remaining interlayer insulating film to a predetermined thickness on the fuse.

The repair etching may be performed by using a mask pattern covering the passivation layer on the scribe lane region, and may be performed as a target exposing the surface of the interlayer insulating layer.

 The removing of the passivation layer remaining on the scribe lane region may be performed by using a mask pattern that opens the passivation layer on the scribe lane region, and the mask pattern may include a PIQ.

The stress relaxation layer may be formed of a material having a compressive stress.

The method may further include forming a test pattern on the interlayer insulating layer of the scribe lane region before forming the passivation layer, wherein the mask is designed to expose the surface of the test pattern during etching to the repair layer. Patterns can be used.

The present invention removes the protective film causing cracks in the scribe area, and the stress relaxation layer remains, thereby reducing the tensile stress of the substrate generated during the background grounding, thereby reducing the bending of the substrate has an effect have.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, taken along line A-A ', B-B', C-C ', and D-D'.

As shown in FIG. 2A, a region in which a test pattern is to be formed between a plurality of die regions where a fuse is to be formed (hereinafter referred to as a fuse region) and a region where a pad is to be formed (hereinafter referred to as a pad region) is formed. Hereinafter, a scribe lane region having a test pattern region) is defined, and a substrate 21 having a predetermined structure is prepared according to a semiconductor device. In this case, the structure may include a transistor, a bit line, a capacitor, or a metal wiring.

Next, a stress relaxation layer 22 is formed on the substrate 21 on which the predetermined structure is formed. At this time, the stress relaxation layer 22 is to relieve tensile stress generated in the substrate during the subsequent backgrinding, an insulating material having a force acting in a direction opposite to the tensile stress, that is, a compressive stress. It is preferable to form using. For example, a spin on insulating layer (SOD) may be used as an insulating material having a compressive stress.

Next, a fuse 23 is formed on the stress relaxation layer 22 of the fuse region. In this case, the fuse 23 is for repairing a defective portion in the case of a defect in the semiconductor device. The fuse 23 is not formed separately through an additional process, but is a plate line of a bit line, a word line, or a capacitor. It can be formed using a conductive layer forming a).

Next, an interlayer insulating film 24 is formed on the entire surface of the resultant including the fuse 22. In this case, the second insulating layer 24 may be an oxide layer, for example, a silicon oxide layer (SiO 2 ), boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), tetra-ethoxy ortho-silicate (TEOS), or un-doped silicate glass (USG). , Any one selected from the group consisting of SOG (Spin On Glass), High Density Plasma (HDP) and SOD (Spin On Dielectric), or may be formed as a laminated film laminated them, preferably stress relaxation Like the layer 22, it is preferable to form a material having a compressive stress.

Next, the pad 25 is formed on the interlayer insulating film 24 of the pad region, and the test pattern 26 is formed in the test pattern region of the scribe lane region. In this case, the test pattern may include an overlay mask for pattern alignment during an exposure process or a structure for measuring an electric parameter monitor (EPM).

Next, the passivation layer 27 is formed on the entire surface of the resultant including the pad 25 and the test pattern 26. At this time, the protective film 27 may be formed of a single film composed of an oxide film or a nitride film, or may be formed of a laminated film in which an oxide film and a nitride film are laminated. For example, the oxide film may be a silicon oxide film (SiO 2 ), BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), USG (Un-doped Silicate Glass), SOG (Spin On Glass) , High Density Plasma Oxide (HDP) or Spin On Dielectric (SOD) may be used, and a silicon nitride film (Si 3 N 4 ) may be used as the nitride film.

Next, after forming the first mask pattern 28 having openings corresponding to the fuse 23, the pad 25, and the test pattern pad 26 on the passivation layer 27, the first mask pattern 28 is formed. Repair / pad etching using an etch barrier to form a fuse open part 29, a pad open part 30, and a test pattern open part 31. In this case, the repair / pad etching of the present invention may be performed as an etching target exposing the surface of the interlayer insulating layer 24. That is, unlike the conventional repair / pad etching, only the protective layer 27 is removed during the repair / pad etching.

As shown in FIG. 2B, a photosensitive insulating film is formed on the entire surface of the resultant product including the fuse open part 29, the pad open part 30, and the test pattern open part 31. In this case, the photosensitive insulating film may be formed of a polyimide isoindroquinazoline (PIQ) film. Here, the PIQ film can be easily formed through an exposure process, and has a characteristic of absorbing alpha particles (α-particles) and preventing soft errors, thereby serving as a top passivation layer of a semiconductor device. It is a widely used material.

Next, a second mask pattern 32 for opening the fuse opening 29, the pad opening 30, and the scribe lane region is formed through the exposure process.

As illustrated in FIG. 2C, the entire surface of the substrate 21 is etched with a target for leaving a predetermined thickness of the interlayer insulating layer 24A on the fuse 23 using the second mask pattern 32 as an etch barrier. As a result, the protective film 27 causing the crack in the die sawing process for separating subsequent die regions from the scribe lane region can be removed, and the tensile stress generated in the substrate 21 during the backgrounding process for the packaging process is alleviated. The stress relaxation layer 22 can be left. At this time, since the stress relaxation layer 22 is formed of a material having a compressive stress, it is possible to alleviate the tensile stress generated in the substrate 21 during the background grounding.

Next, after performing a backgrounding process for reducing the thickness of the substrate 21A, a die sawing process of cutting a portion of the scribe lane region is performed to separate the die region.

As described above, the present invention removes the protective film 27 causing the crack on the substrate 21A of the scribe-lane region, and the stress relaxation layer 22 having the compressive stress is left, so that the substrate 21A is subjected to subsequent backgrounding. It is possible to alleviate the tensile stress generated in the through, it can alleviate the phenomenon that the substrate is bent.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A is a plan view showing a die area and a scribe lane area on a substrate according to the prior art;

1B is a cross-sectional view of a semiconductor device according to the prior art along the line A-A ', B-B', C-C 'and D-D' shown in FIG. 1A;

2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, taken along the line A-A ', B-B', C-C 'and D-D'.

* Description of symbols on the main parts of the drawings *

21 substrate 22 stress relaxation layer

23 fuse 24 interlayer insulating film

25 pad 26 test pattern

27: protective film 28: the first mask pattern

29: fuse open portion 30: pad open portion

31: test pattern opening portion 32: second mask pattern

Claims (8)

Forming a stress relaxation layer on the substrate having the die region and the scribe lane region; Forming a fuse on the stress relaxation layer; Forming an interlayer insulating film on the fuse; Forming a protective film on the interlayer insulating film; A repair etching step of selectively etching the passivation layer on the fuse; Removing the protective film remaining on the scribe lane region while performing an etching process to leave the interlayer insulating layer at a predetermined thickness on the fuse; And Steps to perform the backgrounding process Method of manufacturing a semiconductor device comprising a. The method of claim 1, The repair etching step, A manufacturing method of a semiconductor device by using a mask pattern covering the protective film on the scribe lane region. The method of claim 1, The repair etching is performed as a target for exposing the surface of the interlayer insulating film. The method of claim 1,  Removing the protective film remaining on the scribe lane region, A manufacturing method of a semiconductor device by using a mask pattern for opening a protective film on the scribe lane region. The method of claim 4, wherein The mask pattern manufacturing method of a semiconductor device comprising a PIQ. The method of claim 1, The stress relaxation layer is a semiconductor device manufacturing method of forming a material having a compressive stress. The method of claim 1, Before forming the protective film, And forming a test pattern on the interlayer insulating film of the scribe lane region. The method of claim 7, wherein The method of manufacturing a semiconductor device using a mask pattern designed to expose the surface of the test pattern when etching to the repair.
KR1020070113152A 2007-11-07 2007-11-07 Method for fabricating semiconductor device KR20090047130A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9530741B2 (en) 2014-07-07 2016-12-27 Samsung Electronics Co., Ltd. Semiconductor packages having residual stress layers and methods of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9530741B2 (en) 2014-07-07 2016-12-27 Samsung Electronics Co., Ltd. Semiconductor packages having residual stress layers and methods of fabricating the same

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