JP2007214178A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having openings formed depending on respective each of portions, and to provide a manufacturing method thereof. <P>SOLUTION: This semiconductor device includes a semiconductor layer 10; first interlayer insulating layer 20 provided on the upper part of the semiconductor layer; fuse 22 provided on the upper part of the first interlayer insulating layer; second interlayer insulating layer 30 provided on the upper part of the first interlayer insulating layer and the fuse, and having an insulating layer 30a and an etching stopper layer 30b laminated thereon; electrode pad 32 provided on the upper part of the second interlayer insulating layer and the part other than the upper part of the fuse; passivation layer 40 provided above the electrode pad and the second interlayer insulating layer; first opening 50 provided on the passivation layer and exposing at least one part of the electrode pad; and second opening 60 provided on the upper part of the fuse, piercing the passivation layer and allowing one part of the second interlayer insulating layer to form the bottom surface. The etching stopper layer is made of a material, having etching rate that is smaller than that of the insulating layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

A fuse element blown by a laser may have an opening in which a thin insulating layer remains on the fuse element to suppress corrosion and improve the efficiency of the laser for fusing. One of the methods for forming the opening is a method that is performed in the same process as the formation of the opening for exposing the electrode pad (bonding pad).
JP-A-8-213469

  However, in forming the opening above the electrode pad, it is desired to completely remove the insulating layer, so that good etching may not be performed in the same process.

  An object of the present invention is to provide a semiconductor device in which an opening is formed according to each location and a method for manufacturing the same.

(1) A semiconductor device according to the present invention includes:
A semiconductor layer;
A first interlayer insulating layer provided above the semiconductor layer;
A fuse provided above the first interlayer insulating layer;
A second interlayer insulating layer provided above the first interlayer insulating layer and the fuse and having an insulating layer and an etching stopper layer laminated;
An electrode pad provided above the second interlayer insulating layer and other than above the fuse;
A passivation layer provided above the electrode pad and the second interlayer insulating layer;
A first opening provided in the passivation layer and exposing at least a part of the electrode pad;
The second opening provided above the fuse, penetrating the passivation layer, and a portion of the second interlayer insulating layer forming a bottom surface;
The etching stopper layer is a material having an etching rate smaller than that of the insulating layer.

  According to the semiconductor device of the present invention, there is provided a semiconductor device having a first opening in which an electrode pad is reliably exposed, and a second opening in a state where the fuse is covered with a second interlayer insulating layer. Can do. When forming the first opening and the second opening at the same time, in the first opening, in order to reliably expose the electrode pad, the etching condition is excessive as compared with the etching condition sufficient to remove the passivation layer. Thus, the first opening and the second opening are formed. Therefore, depending on the etching conditions, the fuse may be exposed in the second opening. However, in the semiconductor device according to the present invention, the second interlayer insulating layer located on the fuse is formed by stacking two types of layers having different etching rates. Therefore, for example, the acceleration of etching can be suppressed as compared with the case where the second interlayer insulating layer is formed only of the silicon oxide layer. As a result, it is possible to provide a semiconductor device in which the fuse is protected while the electrode pad is reliably exposed.

  In the present invention, when a specific B layer (hereinafter referred to as “B layer”) provided above a specific A layer (hereinafter referred to as “A layer”) is referred to as “B” directly on the A layer. This includes the case where the layer is provided and the case where the B layer is provided on the A layer via another layer.

  The semiconductor device according to the present invention can further take the following aspects.

(2) In the semiconductor device according to the present invention,
The insulating layer may be silicon oxide, and the etching stopper layer may be silicon nitride or silicon oxynitride.

(3) In the semiconductor device according to the present invention,
The etching stopper layer may be stacked on the insulating layer.

(4) In the method for manufacturing a semiconductor device according to the present invention,
Forming a first interlayer insulating layer above the semiconductor layer;
Forming a fuse above the first interlayer insulating layer;
Forming a second interlayer insulating layer in which an insulating layer and an etching stopper layer are stacked above the first interlayer insulating layer and the fuse;
Forming an electrode pad above the second interlayer insulating layer and other than above the fuse;
Forming a passivation layer above the electrode pad and the second interlayer insulating layer;
Forming a mask layer having an opening above the electrode pad and above the fuse;
Removing the passivation layer above the electrode pad to form a first opening, and removing a portion of the passivation layer above the fuse and the second interlayer insulating layer to form a second opening; including.

  According to the method for manufacturing a semiconductor device of the present invention, the second interlayer insulating layer is formed by laminating an insulating layer and an etching stopper layer. Thereby, when forming the first opening and the second opening at the same time, control is performed so that the second interlayer insulating layer is not completely removed by penetrating the passivation layer on the second opening side. Can do. As a result, a semiconductor device in which the fuse is protected while the electrode pad is reliably exposed can be manufactured.

(5) In the method for manufacturing a semiconductor device according to the present invention,
The formation of the first opening and the second opening can be performed by etching under the same conditions.

  Hereinafter, embodiments of the present invention will be described.

1. 1. First embodiment 1.1. Semiconductor Device First, the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing the semiconductor device according to the present embodiment.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a semiconductor layer 10, a first interlayer insulating layer 20, a fuse 22, a second interlayer insulating layer 30, an electrode pad 32, and a passivation layer 40. The first opening 50 and the second opening 60 are included.

  The semiconductor layer 10 can be made of, for example, a silicon substrate. The semiconductor layer 10 is provided with an element isolation insulating layer (not shown), and a semiconductor element such as a MIS transistor (not shown) is formed in a defined element region.

  The first interlayer insulating layer 20 is formed above the semiconductor layer 10. Specifically, the first interlayer insulating layer 20 is formed so as to cover the transistor. As the first interlayer insulating layer 20, a silicon oxide film, a silicon oxynitride film, a TEOS film, an ozone-TEOS film, a USG film, an FSG film, an SOG film, or a stacked film thereof can be used.

  The fuse 22 is provided on the first interlayer insulating layer 20. Although not shown in FIG. 1, a wiring layer formed in the same process as the fuse 22 can be provided on the first interlayer insulating layer 20.

  A second interlayer insulating layer 30 is provided on the first interlayer insulating layer 20 and the fuse 22. The second interlayer insulating layer 30 is configured by laminating an insulating layer 30a and an etching stopper layer 30b. The etching stopper layer 30b is a material that is less likely to be etched when etched under the same conditions as compared with the insulating layer 30a. That is, when etching under the same conditions is performed, the etching rate of the etching stopper layer 30b is smaller than the etching rate of the insulating layer 30a.

  When a silicon oxide film is applied as the insulating layer 30a, silicon nitride or silicon oxynitride can be applied as the etching stopper layer 30b.

  An electrode pad 32 is formed on the second interlayer insulating layer 30. A passivation layer 40 is formed on the electrode pad 32 and the second interlayer insulating layer 30. The passivation layer 40 can be configured by laminating a silicon oxide layer 42 and a silicon nitride layer 44 provided on the silicon oxide layer 42.

  In the passivation layer 40, a first opening 50 and a part of the second opening 60 are formed. First, the first opening 50 will be described. The first opening 50 is provided on the electrode pad 32, and at least a part of the upper surface of the electrode pad 32 is exposed. That is, the bottom surface of the first opening 50 is the top surface of the electrode pad 32. The planar shape of the first opening 50 is included in the planar shape of the electrode pad 32.

  The second opening 60 is provided above the fuse 22. In the present embodiment, a case where one opening is provided in the opening region 62 located above the plurality of fuses 22 group will be described. In other words, the planar pattern of the first opening 60 overlaps with the same pattern as the opening region 62. The second opening 60 penetrates the passivation layer 40 and is formed by removing a part of the second interlayer insulating layer 30. Specifically, the etching stopper layer 30b and the insulating layer 30a are partially removed from the second interlayer insulating layer 30. That is, the bottom surface of the second opening 60 is the insulating layer 30a so that the fuse 22 is not exposed. The film thickness of the insulating layer 30 a located in the opening region 62 is smaller than that of the insulating layer 30 a located below the electrode pad 32.

  According to the semiconductor device of the present embodiment, the semiconductor device having the first opening 50 in which the electrode pad 32 is reliably exposed and the second opening 60 in which the fuse 22 is covered with the second interlayer insulating layer 30. Can be provided. In the semiconductor device according to the present embodiment, when the first opening 50 and the second opening 60 are simultaneously formed, the etching conditions corresponding to the removal of the passivation layer 40 are compared with each other so that the electrode pad 32 is reliably exposed. Thus, the first opening 50 and the second opening 60 are formed under excessive etching conditions. Therefore, depending on the etching conditions, the fuse 22 may be exposed at the second opening 60. However, in the semiconductor device according to the present embodiment, two types of layers having different etching rates are stacked as the second interlayer insulating layer 30 located on the fuse 22. Therefore, the acceleration of etching can be suppressed as compared with the case where the second interlayer insulating layer 30 is formed only of the silicon oxide layer. As a result, it is possible to provide a semiconductor device in which the electrode pad 32 is reliably exposed and the fuse 22 is protected.

1.2. Semiconductor Device Manufacturing Method A semiconductor device manufacturing method according to the present embodiment will be described below with reference to FIGS. 2 and 3 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the present embodiment. 2 and 3 are cross-sectional views corresponding to FIG.

  (1) As shown in FIG. 2, various semiconductor elements such as transistors (not shown) are appropriately formed in the semiconductor layer 10 (including the formation of an element isolation insulating layer). Thereafter, a first interlayer insulating layer 20 is formed on the entire surface of the semiconductor layer 10. Next, a fuse 22 and a wiring layer (not shown) are formed on the first interlayer insulating layer 20. The fuse 22 and the wiring layer are formed by forming a conductive layer (not shown) on the entire upper surface of the first interlayer insulating layer 20 and then patterning by a known lithography and etching technique. Needless to say, a step of forming a plug (not shown) in the first interlayer insulating layer 20 is included before the fuse 22 and the wiring layer are formed.

  Next, a second interlayer insulating layer 30 is formed on the fuse 22 and the first interlayer insulating layer 20. In forming the second interlayer insulating layer 30, first, the insulating layer 30 a is formed on the fuse 22 and the first interlayer insulating layer 20. For example, silicon oxide is formed as the insulating layer 30a. The insulating layer 30a becomes an uneven upper surface along the shape of the fuse 22 or the wiring layer. In this case, it is preferable to perform a planarization process on the insulating layer 30a as necessary. The planarization can be performed by, for example, a CMP method.

  Next, an etching stopper layer 30b is formed on the insulating layer 30a. For the etching stopper layer 30b, a material having a lower etching rate is selected when etching is performed under the same conditions as compared with the insulating layer 30a. For example, silicon nitride can be used. In this way, the second interlayer insulating layer 30 in which the insulating layer 30a and the etching stopper layer 30b are stacked can be formed.

  (2) Next, as shown in FIG. 3, an electrode pad 32 and, if necessary, a wiring layer (not shown) are formed on the second interlayer insulating layer 30. The electrode pad 32 and the wiring layer can be formed by forming a conductive layer (not shown) on the entire upper surface of the second interlayer insulating layer 30 and patterning the conductive layer by known lithography and etching techniques. Needless to say, a step of forming a plug (not shown) in the second interlayer insulating layer 30 is included before the electrode pad 32 and the wiring layer are formed.

  Next, for example, a silicon oxide layer 42 is formed on the electrode pad 32 and the first interlayer insulating layer 30. The silicon oxide layer 42 can be formed by, for example, a CVD method. Next, a silicon nitride layer 44 is formed on the silicon oxide layer 42. The silicon nitride layer 44 can be formed by, for example, a CVD method. In this way, the passivation layer 40 is formed.

  Next, a mask layer is formed on the passivation layer 40. FIG. 3 illustrates a case where a resist layer R1 is formed as a mask layer. The resist layer R1 has an opening 51 above the electrode pad 32 and an opening 61 above the fuse 22.

  (3) Next, as shown in FIG. 1, the fuse 22 is not exposed above the first opening 50 where the upper surface of the electrode pad 32 is exposed using the resist layer R <b> 1 as a mask and the fuse 22. The second opening 60 is formed under the same etching conditions (process). In this way, by forming under the same etching conditions, the process can be simplified and the manufacturing cost can be reduced. The first opening 50 and the second opening 60 can be formed by dry etching, for example.

  Through the above steps, the semiconductor device according to the first embodiment can be manufactured.

  Advantages of the semiconductor device manufacturing method according to the present embodiment will be described with reference to FIG. FIG. 4A and FIG. 4B are diagrams showing a process of forming the first opening and the second opening. First, as shown in FIG. 4A, the exposed passivation layer 40 is removed from the openings 51 and 61. However, in this etching, over the electrode pad 32, the upper surface of the electrode pad 32 is partially removed in order to ensure conductivity after being mounted on the wiring board and to improve the flatness of the surface. Etched. At this time, as shown in FIG. 4B, a part of the second interlayer insulating layer 30 is removed and the second opening 60 is formed above the fuse 22. However, when the electrode pad 32 and the second interlayer insulating layer 30 are etched under the same conditions, the etching rate of the second interlayer insulating layer 30 is high. Therefore, if desired overetching is performed, the second interlayer insulating layer 30 may be removed to the extent that the fuse 22 is exposed. However, in this embodiment, the etching stopper layer 30 b is formed as a part of the second interlayer insulating layer 30. For this reason, etching can be delayed above the fuse 22 as compared with the case where it is formed only of silicon oxide. As a result, a desired opening can be formed even when the first opening 50 and the second opening 60 are formed in the same process. Thus, a semiconductor device in which the fuse 22 is protected while the electrode pad 32 is reliably exposed can be manufactured.

2. Second Embodiment 2.1. Semiconductor Device Next, a semiconductor device according to a second embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view schematically showing the semiconductor device according to the present embodiment. The second embodiment is an example in which the configurations of the electrode pad 32 and the passivation layer 40 are different. In the following description, detailed description of components and members common to the first embodiment will be omitted.

  In the semiconductor device according to the second embodiment, as shown in FIG. 5, the electrode pad 32 includes a refractory metal nitride layer 32a, a metal layer 32b, and a refractory metal nitride layer 32c. Configured. The refractory metal nitride layers 32a and 32c may be TiN layers, for example. The metal layer 32b can be, for example, an Al layer. The nitride layer 32 c on the uppermost side of the electrode pad 32 is not provided on the bottom surface of the first opening 50. A metal layer 32 b is provided on the bottom surface of the first opening 50. That is, the nitride layer 32c is provided only in a region where the passivation layer 40 and the metal layer 32b overlap.

  In the semiconductor device according to the second embodiment, the passivation layer 40 has a flat upper surface. In particular, the silicon oxide layer 42 has a flat upper surface.

2.2. Semiconductor Device Manufacturing Method A semiconductor device manufacturing method according to the second embodiment will be described with reference to FIG. In the following description, differences from the method for manufacturing the semiconductor device according to the first embodiment will be described.

  First, as shown in FIG. 3, a silicon oxide layer is formed on the electrode pad 32 and the second interlayer insulating layer 30 in the same manner as the steps (1) and (2) of the manufacturing method according to the first embodiment. 42a is formed. Note that the silicon oxide layer 42 shown in FIG. 3 corresponds to the silicon oxide layer 42a of the manufacturing method according to the present embodiment. Next, as shown in FIG. 6, the silicon oxide layer 42 a is planarized to form the silicon oxide layer 42. The planarization of the silicon oxide layer 42a can be performed by, for example, a CMP method. Thus, by flattening the silicon oxide layer 42, the film thickness Y located above the fuse 22 can be made larger than the film thickness X located on the electrode pad 32. Thereafter, a silicon nitride layer 44 is formed on the silicon oxide layer 42. Next, as in the manufacturing method according to the first embodiment, the resist layer R1 is formed, and the first opening 50 and the second opening 60 are formed.

  Advantages of the semiconductor device manufacturing method according to the second embodiment will be described with reference to FIG. FIG. 7 is a cross-sectional view showing a process of forming the first opening 50 and the second opening 60. As shown in FIG. 7A, the opening 51 passivation layer 40 is removed, and the nitride layer 32c is exposed. On the other hand, in the opening 61, the silicon oxide layer 42 having a thickness of YX remains. Subsequently, as shown in FIG. 7B, the nitride layer 32c is removed in the opening 51, and the silicon oxide layer 42, the etching stopper layer 30b, and the insulating layer 30a are partially removed in the opening 61. Done. In the opening 51, since the nitride layer 32c remains, bonding adhesiveness may be deteriorated. Therefore, it is desirable to remove it reliably. In the present embodiment, an etching stopper layer 30b is provided above the fuse 22, and the etching stopper layer 30b is a material that is harder to be etched than the silicon oxide layer 30a. Therefore, it is possible to prevent the fuse 22 from being exposed in the process of removing the nitride layer 32c, as compared with the case where the second interlayer insulating layer 30 is formed using only silicon oxide. is there. In the present embodiment, the etching of the second opening 60 can withstand overetching by the difference in film thickness (Y−X) of the silicon oxide layer 42. Therefore, the effect of suppressing the exposure of the fuse 22 can be further enhanced. As a result, it is possible to manufacture a semiconductor device in which the fuse 22 is protected while the electrode pad 32 is reliably exposed.

  In forming the second opening 60, a method of reducing the opening pattern may be applied in order to reliably leave the insulating layer on the fuse 22. That is, the pattern of the openings 61 in the resist layer R1 is reduced. In this case, the acceleration of etching is suppressed according to the opening pattern, and the insulating layer on the fuse can be left. However, depending on the opening pattern of the second opening 60, the fusing efficiency of the fuse may be deteriorated. is there. However, according to the present embodiment, since the etching stopper layer 30b is provided, the insulating layer can easily remain on the fuse, and a desired opening can be secured. As a result, it is possible to provide a semiconductor device in which deterioration in fusing efficiency is suppressed and reliability is improved.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor layer, 20 ... 1st interlayer insulation layer, 22 ... Fuse, 30 ... 2nd interlayer insulation layer, 30a ... Insulation layer, 30b ... Etching stopper layer, 32 ... Electrode pad, 40 ... Passivation layer, 42, 42a ... Silicon oxide layer, 44 ... Silicon nitride layer, 50 ... First opening, 51, 61 ... Opening, 60 ... Second opening, 62 ... Opening region, R1 ... Resist layer

Claims (5)

A semiconductor layer;
A first interlayer insulating layer provided above the semiconductor layer;
A fuse provided above the first interlayer insulating layer;
A second interlayer insulating layer provided above the first interlayer insulating layer and the fuse and having an insulating layer and an etching stopper layer laminated;
An electrode pad provided above the second interlayer insulating layer and other than above the fuse;
A passivation layer provided above the electrode pad and the second interlayer insulating layer;
A first opening provided in the passivation layer and exposing at least a part of the electrode pad;
The second opening provided above the fuse, penetrating the passivation layer, and a portion of the second interlayer insulating layer forming a bottom surface;
The said etching stopper layer is a semiconductor device which is a material with a small etching rate compared with the said insulating layer. In claim 1,
The semiconductor device, wherein the insulating layer is silicon oxide, and the etching stopper layer is silicon nitride or silicon oxynitride. In claim 1 or 2,
A semiconductor device, wherein the etching stopper layer is laminated on the insulating layer. Forming a first interlayer insulating layer above the semiconductor layer;
Forming a fuse above the first interlayer insulating layer;
Forming a second interlayer insulating layer in which an insulating layer and an etching stopper layer are stacked above the first interlayer insulating layer and the fuse;
Forming an electrode pad above the second interlayer insulating layer and other than above the fuse;
Forming a passivation layer above the electrode pad and the second interlayer insulating layer;
Forming a mask layer having an opening above the electrode pad and above the fuse;
Removing the passivation layer above the electrode pad to form a first opening, and removing a portion of the passivation layer above the fuse and the second interlayer insulating layer to form a second opening; A method for manufacturing a semiconductor device, comprising: In claim 4,
The method for manufacturing a semiconductor device, wherein the first opening and the second opening are formed by etching under the same conditions.

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