JP5088700B2 - Ferroelectric memory and manufacturing method of ferroelectric memory - Google Patents

Ferroelectric memory and manufacturing method of ferroelectric memory Download PDF

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JP5088700B2
JP5088700B2 JP2008290708A JP2008290708A JP5088700B2 JP 5088700 B2 JP5088700 B2 JP 5088700B2 JP 2008290708 A JP2008290708 A JP 2008290708A JP 2008290708 A JP2008290708 A JP 2008290708A JP 5088700 B2 JP5088700 B2 JP 5088700B2
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film
insulating film
conductive film
ferroelectric memory
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JP2009038403A (en
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弘 福田
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Seiko Epson Corp
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Description

本発明は、半導体装置の製造方法及び合わせマークの形成方法、半導体装置に関し、特に、合わせマークのサイズが大きい場合でもその異常酸化を防止できるようにした技術に関する。   The present invention relates to a method for manufacturing a semiconductor device, a method for forming an alignment mark, and a semiconductor device, and more particularly to a technique capable of preventing abnormal oxidation even when the size of the alignment mark is large.

半導体装置の製造工程では、ウエーハとフォトマスクとの位置合わせは必須の工程であり、その際に生じる誤差を最小限に抑えることが要求されている。このため、ウエーハ上に設けられたパターンに、次に形成すべきパターンを正しく重ね合わせるため、合わせマークが使用されている（例えば、特許文献１〜３参照。）。合わせマークの形状や大きさには様々なものがあるが、多くのものは平面視での形状が矩形であり、その一辺の長さは下記Ａ〜Ｄマークで例示するように、数μｍから数十μｍ程度である。   In the manufacturing process of a semiconductor device, the alignment between the wafer and the photomask is an indispensable process, and it is required to minimize errors generated at that time. For this reason, alignment marks are used in order to correctly overlay the pattern to be formed next on the pattern provided on the wafer (see, for example, Patent Documents 1 to 3). There are various shapes and sizes of the alignment marks, but many of them have a rectangular shape in plan view, and the length of one side is from several μm as exemplified by the following A to D marks. It is about several tens of μm.

Ａマーク：縦３μｍ×横４μｍ
Ｂマーク：縦４μｍ×横４μｍ
Ｃマーク：縦６μｍ×横７２μｍ
Ｄマーク：縦１５〜２５μｍ×横１５〜２５μｍ A mark: 3 μm long × 4 μm wide
B mark: 4 μm long × 4 μm wide
C mark: 6 μm long × 72 μm wide
D mark: 15-25 μm long × 15-25 μm wide

特開２００２−３７３９７４号公報JP 2002-373974 A 特開２００５−１４２２５２号公報JP 2005-142252 A 特開２００４−３９７３１号公報Japanese Patent Laid-Open No. 2004-37931

ところで、半導体基板上にプラグ電極を形成する場合には、層間絶縁膜にビアホール（「コンタクトホール」とも呼ばれる。）を形成すると共に、ビアホールから離れた位置に合わせマーク用の開口部を形成する。そして、層間絶縁膜上にタングステン（Ｗ）膜を形成してビアホールを埋め込む。Ｗ膜の形成はＣＶＤ（ｃｈｅｍｉｃａｌ ｖａｐｏｒ ｄｅｐｏｓｉｔｉｏｎ）法で行う。その後、半導体基板の上方全面にＣＭＰ（ｃｈｅｍｉｃａｌ ｍｅｃｈａｎｉｃａｌ ｐｏｌｉｓｈｉｎｇ）を施して層間絶縁膜上からＷ膜を取り除き、プラグ電極と合わせマークとを完成させる。   By the way, when a plug electrode is formed on a semiconductor substrate, a via hole (also referred to as a “contact hole”) is formed in the interlayer insulating film, and an opening for a mark is formed at a position away from the via hole. Then, a tungsten (W) film is formed on the interlayer insulating film to fill the via hole. The W film is formed by a CVD (Chemical Vapor Deposition) method. Thereafter, CMP (chemical mechanical polishing) is performed on the entire upper surface of the semiconductor substrate to remove the W film from the interlayer insulating film, thereby completing the plug electrode and the alignment mark.

ここで、合わせマークは単位パターンが数μｍ角以上と、実際の回路で使用されるパターン（＜１μｍ）と比べて大きいため、合わせマークを構成するＷ膜表面には段差が生じる。つまり、ＣＶＤ法では、直径が小さい穴ほど早く埋め込まれる傾向があるため、Ｗ膜によって開口部が完全に埋め込まれる前にビアホールの埋め込みが完了する。開口部を実際に合わせマークとして使用する場合は、ある程度段差がないとマークとして認識できなくなるので、開口部の埋め込みが不完全でも通常は特に問題とならない。   Here, the alignment mark has a unit pattern of several μm square or more, which is larger than the pattern used in an actual circuit (<1 μm), so that a step is generated on the surface of the W film constituting the alignment mark. That is, in the CVD method, a hole having a smaller diameter tends to be filled earlier, so that the filling of the via hole is completed before the opening is completely filled with the W film. When the opening is actually used as an alignment mark, it cannot be recognized as a mark unless there is a level difference to some extent, so even if the opening is not completely filled, there is usually no particular problem.

しかしながら、強誘電体メモリ（ＦｅＲＡＭ：ｆｅｒｒｏｅｌｅｃｔｒｉｃ ＲＡＭ）の製造工程では、プラグ電極と合わせマークとを形成した後でその上に酸化バリア膜を敷いて高温熱処理を施す。このとき、合わせマークの段差が深く（大きく）なり過ぎていると、図３に示すように、開口部Ｈ’内で酸化バリア膜９１のカバレッジが低下してしまう（即ち、図３の破線で囲んだ部分のように、酸化バリア膜９１に局所的に薄い部分ができてしまう。）。その結果、酸化バリア膜９１に求められるバリア性が損なわれ、開口部Ｈ’内のＷ膜９３が異常に酸化してしまうという問題があった。   However, in a manufacturing process of a ferroelectric memory (FeRAM), after forming a plug electrode and a matching mark, an oxidation barrier film is laid on the plug electrode and a high temperature heat treatment is performed. At this time, if the level difference of the alignment mark is too deep (large), the coverage of the oxidation barrier film 91 is lowered in the opening H ′ as shown in FIG. 3 (that is, the broken line in FIG. 3). A locally thin portion is formed in the oxidation barrier film 91 as in the enclosed portion.) As a result, the barrier property required for the oxidation barrier film 91 is impaired, and the W film 93 in the opening H ′ is abnormally oxidized.

本発明の一態様の強誘電体メモリは、基板と、前記基板の上に形成された第１絶縁膜と、前記第１絶縁膜に形成された第１ビアホールと、前記第１ビアホールに形成された第１プラグ電極と、前記第１絶縁膜および前記第１プラグ電極の上に形成された第１導電膜と、前記第１絶縁膜の上であって、前記第１導電膜と離間して形成された第２導電膜と、前記第１絶縁膜、前記第１導電膜および前記第２導電膜の上に形成された第２絶縁膜と、前記第１導電膜の上であって、前記第２絶縁膜に形成された第２ビアホールと、 前記第２ビアホールに形成された第２プラグ電極と、前記第２導電膜の上であって、前記第２絶縁膜に形成された開口部と、前記開口部を埋め込むように形成された合わせマークと、前記合わせマークの上に形成された酸化バリア膜と、を含み、前記上から見たとき、前記開口部は、該開口部の外周の内側の領域を全て含む。
本発明の一態様の強誘電体メモリの製造方法は、基板の上に第１絶縁膜を形成する工程と、前記第１絶縁膜に第１ビアホールを形成する工程と、前記第１ビアホールに第１プラグ電極を形成する工程と、前記第１絶縁膜および前記第１プラグ電極の上に導電膜を形成する工程と、前記導電膜を選択的にエッチングして、前記第１プラグ電極の上に位置する第１導電膜と、前記第１導電膜と離間する第２導電膜を形成する工程と、前記第１絶縁膜、前記第１導電膜および前記第２導電膜の上に第２絶縁膜を形成する工程と、 前記第２絶縁膜を選択的にエッチングして、前記第１導電膜の上に位置する第２ビアホールを形成すると共に、前記第２導電膜の上に位置する開口部を形成する工程と、前記第２ビアホールに前記第２プラグ電極を形成すると共に、前記開口部を埋め込むように合わせマークを形成する工程と、前記第２絶縁膜、前記第２プラグ電極および前記合わせマークの上に酸化バリア膜を形成する工程と、を含み、前記上から見たとき、前記開口部は、該開口部の外周の内側の領域を全て含む、強誘電体メモリの製造方法。
上記の本発明に係る強誘電体メモリは、基板と、前記基板の上に形成された第１絶縁膜と、前記第１絶縁膜に形成された第１ビアホールと、前記第１ビアホールに形成された第１プラグ電極と、前記第１絶縁膜および前記第１プラグ電極の上に形成された第１導電膜と、前記第１絶縁膜の上であって、前記第１導電膜と離間して形成された第２導電膜と、前記第１絶縁膜、前記第１導電膜および前記第２導電膜の上に形成された第２絶縁膜と、前記第１導電膜の上であって、前記第２絶縁膜に形成された第２ビアホールと、 前記第２ビアホールに形成された第２プラグ電極と、前記第２導電膜の上であって、前記第２絶縁膜に形成された開口部と、前記開口部を埋め込むように形成された合わせマークと、前記合わせマークの上に形成された酸化バリア膜と、を含む。
上記の本発明に係る強誘電体メモリの製造方法は、基板の上に第１絶縁膜を形成する工程と、前記第１絶縁膜に第１ビアホールを形成する工程と、前記第１ビアホールに第１プラグ電極を形成する工程と、前記第１絶縁膜および前記第１プラグ電極の上に導電膜を形成する工程と、前記導電膜を選択的にエッチングして、前記第１プラグ電極の上に位置する第１導電膜と、前記第１導電膜と離間する第２導電膜を形成する工程と、前記第１絶縁膜、前記第１導電膜および前記第２導電膜の上に第２絶縁膜を形成する工程と、 前記第２絶縁膜を選択的にエッチングして、前記第１導電膜の上に位置する第２ビアホールを形成すると共に、前記第２導電膜の上に位置する開口部を形成する工程と、前記第２ビアホールに前記第２プラグ電極を形成すると共に、前記開口部を埋め込むように合わせマークを形成する工程と、前記第２絶縁膜、前記第２プラグ電極および前記合わせマークの上に酸化バリア膜を形成する工程と、を含む。
上記の本発明に係る強誘電体メモリは、基板と、前記基板上に形成された第１絶縁膜と、前記第１絶縁膜に形成された第１ビアホールと、前記第１ビアホールに形成された第１プラグ電極と、上であって、前記第１導電膜と離間して形成された第２導電膜と、前記第１絶縁膜、前記第１導電膜および前記第２導電膜上に形成された第２絶縁膜と、前記第１導電膜上であって、前記第２絶縁膜に形成された第２ビアホールと、前記第２ビアホールに形成された第２プラグ電極と、前記第２導電膜上であって、前記第２絶縁膜に形成された開口部と、前記開口部に形成された合わせマークと、前記合わせマーク上に形成された酸化バリア膜と、を含む。
上記の本発明に係る強誘電体メモリは、前記強誘電体メモリにおいて、前記合わせマークは、タングステン膜からなる。
上記の本発明に係る強誘電体メモリは、前記強誘電体メモリにおいて、前記酸化バリア膜は、ＴｉＡｌＮを含む。
上記の本発明に係る強誘電体メモリは、前記強誘電体メモリにおいて、前記第１導電膜は、第１ＴｉＮおよび該第１ＴｉＮ上に形成された第１Ｔｉからなり、前記第２導電膜は、第２ＴｉＮおよび該第２ＴｉＮ上に形成された第２Ｔｉからなる。
上記の本発明に係る強誘電体メモリは、前記強誘電体メモリにおいて、前記開口部の底面は、前記第２導電層の上面である、強誘電体メモリ。
上記の本発明に係る強誘電体メモリは、前記強誘電体メモリにおいて、前記第２絶縁膜上に形成された強誘電体膜を含む、強誘電体メモリ。
上記の本発明に係る強誘電体メモリの製造方法は、基板上に第１絶縁膜を形成する工程と、前記第１絶縁膜に第１ビアホールを形成する工程と、前記第１ビアホールに第１プラグ電極を形成する工程と、前記第１絶縁膜および前記第１プラグ電極上に導電膜を形成する工程と、前記導電膜を選択的にエッチングして、前記第１プラグ電極上に位置する第１導電膜と、該第１導電膜と離間する第２導電膜を形成する工程と、前記第１絶縁膜、前記第１導電膜および前記第２導電膜上に第２絶縁膜を形成する工程と、前記第２絶縁膜を選択的にエッチングして、該第１導電膜上に位置する第２ビアホールを形成すると共に、前記第２導電膜上に位置する開口部を形成する工程と、前記第２ビアホールに前記第２プラグ電極を形成すると共に、前記開口部に合わせマークを形成する工程と、前記第２絶縁膜、前記第２プラグ電極および前記合わせマーク上に酸化バリア膜を形成する工程と、を含む。
上記の本発明に係る強誘電体メモリの製造方法は、前記強誘電体メモリの製造方法において、前記合わせマークは、タングステン膜からなる。
上記の本発明に係る強誘電体メモリの製造方法は、前記強誘電体メモリの製造方法において、前記酸化バリア膜は、ＴｉＡｌＮを含む。
上記の本発明に係る強誘電体メモリの製造方法は、前記強誘電体メモリの製造方法において、前記電膜は、ＴｉＮおよび該ＴｉＮ上に形成されたＴｉからなる。
上記の本発明に係る強誘電体メモリの製造方法は、前記強誘電体メモリの製造方法において、前記開口部の底面は、前記第２導電層の上面である。
上記の本発明に係る強誘電体メモリの製造方法は、前記強誘電体メモリの製造方法において、前記第２絶縁膜上に強誘電体膜を形成する工程と、酸素雰囲気中で熱処理を行う工程と、を含む。
 A ferroelectric memory according to one aspect of the present invention is formed in a substrate, a first insulating film formed on the substrate, a first via hole formed in the first insulating film, and the first via hole. A first plug electrode, a first conductive film formed on the first insulating film and the first plug electrode, and on the first insulating film, separated from the first conductive film. A second conductive film formed; a second insulating film formed on the first insulating film; the first conductive film; and the second conductive film; and the first conductive film, A second via hole formed in the second insulating film; a second plug electrode formed in the second via hole; and an opening formed in the second insulating film on the second conductive film; , An alignment mark formed to fill the opening, and an acid formed on the alignment mark And when viewed from above, the opening includes the entire inner region of the outer periphery of the opening.
The method for manufacturing a ferroelectric memory according to one aspect of the present invention includes a step of forming a first insulating film on a substrate, a step of forming a first via hole in the first insulating film, and a step of forming a first via hole in the first via hole. Forming a plug electrode; forming a conductive film on the first insulating film and the first plug electrode; and selectively etching the conductive film on the first plug electrode. Forming a first conductive film located; a second conductive film spaced apart from the first conductive film; and a second insulating film on the first insulating film, the first conductive film, and the second conductive film. Forming a second via hole located on the first conductive film, and forming an opening located on the second conductive film. And forming the second plug electrode in the second via hole. And forming an alignment mark so as to fill the opening, and forming an oxidation barrier film on the second insulating film, the second plug electrode, and the alignment mark, When viewed from the above, the opening includes the entire inner region of the outer periphery of the opening.
The ferroelectric memory according to the present invention is formed in a substrate, a first insulating film formed on the substrate, a first via hole formed in the first insulating film, and the first via hole. A first plug electrode, a first conductive film formed on the first insulating film and the first plug electrode, and on the first insulating film, separated from the first conductive film. A second conductive film formed; a second insulating film formed on the first insulating film; the first conductive film; and the second conductive film; and the first conductive film, A second via hole formed in the second insulating film; a second plug electrode formed in the second via hole; and an opening formed in the second insulating film on the second conductive film; And an alignment mark formed so as to fill the opening, and formed on the alignment mark An oxidation barrier film.
In the method of manufacturing a ferroelectric memory according to the present invention, a step of forming a first insulating film on a substrate, a step of forming a first via hole in the first insulating film, and a step of forming a first via hole in the first via hole. Forming a plug electrode; forming a conductive film on the first insulating film and the first plug electrode; and selectively etching the conductive film on the first plug electrode. Forming a first conductive film located; a second conductive film spaced apart from the first conductive film; and a second insulating film on the first insulating film, the first conductive film, and the second conductive film. Forming a second via hole located on the first conductive film, and forming an opening located on the second conductive film. Forming and forming the second plug electrode in the second via hole And forming an alignment mark so as to fill the opening, and forming an oxidation barrier film on the second insulating film, the second plug electrode, and the alignment mark.
The ferroelectric memory according to the present invention is formed in a substrate, a first insulating film formed on the substrate, a first via hole formed in the first insulating film, and the first via hole. A first plug electrode, and a second conductive film formed on the first conductive film and spaced apart from the first conductive film; and formed on the first insulating film, the first conductive film, and the second conductive film. A second via hole formed in the second insulating film on the first conductive film, a second plug electrode formed in the second via hole, and the second conductive film. An opening formed in the second insulating film, an alignment mark formed in the opening, and an oxidation barrier film formed on the alignment mark.
In the ferroelectric memory according to the present invention, the alignment mark is made of a tungsten film.
In the ferroelectric memory according to the present invention described above, in the ferroelectric memory, the oxidation barrier film includes TiAlN.
In the ferroelectric memory according to the present invention described above, in the ferroelectric memory, the first conductive film is composed of first TiN and first Ti formed on the first TiN, and the second conductive film is 2TiN and second Ti formed on the second TiN.
The ferroelectric memory according to the present invention is the ferroelectric memory, wherein a bottom surface of the opening is an upper surface of the second conductive layer.
The ferroelectric memory according to the present invention is a ferroelectric memory including the ferroelectric memory including a ferroelectric film formed on the second insulating film.
In the method for manufacturing a ferroelectric memory according to the present invention, a step of forming a first insulating film on a substrate, a step of forming a first via hole in the first insulating film, and a first step in the first via hole. A step of forming a plug electrode; a step of forming a conductive film on the first insulating film and the first plug electrode; and a step of selectively etching the conductive film to locate a first conductive film on the first plug electrode. Forming a first conductive film and a second conductive film spaced apart from the first conductive film; and forming a second insulating film on the first insulating film, the first conductive film, and the second conductive film. And selectively etching the second insulating film to form a second via hole located on the first conductive film and forming an opening located on the second conductive film; Forming the second plug electrode in the second via hole; And forming a mark fit mouth, the second insulating film, and forming a oxide barrier film to the second plug electrode and the alignment mark on.
In the method for manufacturing a ferroelectric memory according to the present invention, the alignment mark is made of a tungsten film.
In the method for manufacturing a ferroelectric memory according to the present invention, the oxidation barrier film includes TiAlN.
In the method for manufacturing a ferroelectric memory according to the present invention, the electric film is made of TiN and Ti formed on the TiN.
In the method for manufacturing a ferroelectric memory according to the present invention, the bottom surface of the opening is the top surface of the second conductive layer.
The method for manufacturing a ferroelectric memory according to the present invention includes the steps of forming a ferroelectric film on the second insulating film and performing a heat treatment in an oxygen atmosphere in the method for manufacturing a ferroelectric memory. And including.

このような構成であれば、開口部を形成する際に第１絶縁膜までエッチングが進行してしまうことを防ぐことができるので、開口部を浅く形成することができる。従って、開口部内への金属膜の埋め込みが容易であり、開口部内での金属膜（即ち、合わせマーク）表面の段差を小さくすることができる。
この発明は、ＦｅＲＡＭ等に適用して極めて好適である。 With such a structure, it is possible to prevent the etching from proceeding to the first insulating film when forming the opening, so that the opening can be formed shallowly. Therefore, the metal film can be easily embedded in the opening, and the step on the surface of the metal film (that is, the alignment mark) in the opening can be reduced.
The present invention is extremely suitable when applied to FeRAM or the like.

以下、本発明の実施の形態を図面を参照しながら説明する。
図１（Ａ）〜図２（Ｃ）は、本発明の実施の形態に係る半導体装置の製造方法を示す工程図である。この実施の形態では、半導体基板から層間絶縁膜の上面に至るプラグ電極を第１プラグ電極と第２プラグ電極とに分け、第１プラグ電極と第２プラグ電極とをローカルインターコネクト（以下、「ＬＩ層という。」）で繋ぐと共に、合わせマークの下にもＬＩ層を敷くことについて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
1A to 2C are process diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In this embodiment, the plug electrode extending from the semiconductor substrate to the upper surface of the interlayer insulating film is divided into a first plug electrode and a second plug electrode, and the first plug electrode and the second plug electrode are connected to a local interconnect (hereinafter referred to as “LI”). It will be described that the LI layer is laid under the alignment mark.

図１（Ａ）に示すように、まず始めに、半導体基板（ウエーハ）１上に第１層間絶縁膜を形成する。半導体基板１は例えばシリコン（Ｓｉ）基板であり、例えば図示しないＭＯＳトランジスタ等が形成されている。また、第１層間絶縁膜３は例えばシリコン酸化膜であり、その厚さは例えば１０００ｎｍ程度である。
次に、フォトリソグラフィ技術及びエッチング技術を用いて第１層間絶縁膜３を選択的にエッチングし、半導体基板１に形成された不純物拡散層２上に第１ビアホールｈ１を形成する。不純物拡散層２は、例えば図示しないＭＯＳトランジスタのソース又はドレインである。 As shown in FIG. 1A, first, a first interlayer insulating film is formed on a semiconductor substrate (wafer) 1. The semiconductor substrate 1 is a silicon (Si) substrate, for example, and is formed with, for example, a MOS transistor (not shown). The first interlayer insulating film 3 is a silicon oxide film, for example, and has a thickness of about 1000 nm, for example.
Next, the first interlayer insulating film 3 is selectively etched using a photolithography technique and an etching technique to form a first via hole h <b> 1 on the impurity diffusion layer 2 formed in the semiconductor substrate 1. The impurity diffusion layer 2 is, for example, a source or drain of a MOS transistor (not shown).

次に、第１ビアホールｈ１が形成された第１層間絶縁膜３上にタングステン（Ｗ）膜を形成して、第１ビアホールｈ１を埋め込む。Ｗ膜の形成は例えばＣＶＤ法で行う。そして、このＷ膜上にＣＭＰ処理を施して第１層間絶縁膜３上からＷ膜を取り除く。これにより、図１（Ａ）に示すように、第１ビアホールｈ１内に第１プラグ電極５を形成する。
次に、図１（Ａ）に示すように、第１プラグ電極５が形成された第１層間絶縁膜３上に導電膜７を形成する。ここで、導電膜７は例えば、下層が窒化チタン（ＴｉＮ）で上層がチタン（Ｔｉ）で構成される膜（即ち、Ｔｉ／ＴｉＮからなる積層構造の膜）である。Ｔｉ膜の膜厚は例えば２０ｎｍであり、ＴｉＮの膜厚は例えば１８０ｎｍである。このような導電膜７の形成は、例えばスパッタリング法によって行う。 Next, a tungsten (W) film is formed on the first interlayer insulating film 3 in which the first via hole h1 is formed, and the first via hole h1 is buried. The W film is formed by, for example, a CVD method. Then, a CMP process is performed on the W film to remove the W film from the first interlayer insulating film 3. Thus, as shown in FIG. 1A, the first plug electrode 5 is formed in the first via hole h1.
Next, as shown in FIG. 1A, a conductive film 7 is formed on the first interlayer insulating film 3 on which the first plug electrode 5 is formed. Here, the conductive film 7 is, for example, a film composed of titanium nitride (TiN) as a lower layer and titanium (Ti) as an upper layer (that is, a film having a laminated structure composed of Ti / TiN). The film thickness of the Ti film is 20 nm, for example, and the film thickness of TiN is 180 nm, for example. Such a conductive film 7 is formed by sputtering, for example.

次に、フォトリソグラフィ技術及びエッチング技術を用いて導電膜７を選択的にエッチングし、図１（Ｂ）に示すように、第１プラグ電極５上に例えばＴｉ／ＴｉＮからなるＬＩ層７ａを形成すると共に、合わせマーク形成領域の第１層間絶縁膜３上に例えばＴｉ／ＴｉＮからなるＬＩ層７ｂを形成する。Ｌｉ層７ａとＬｉ層７ｂは図示しない部分で繋がっていても良いし、繋がっていなくても（即ち、電気的に接続していなくても）良い。
次に、図１（Ｃ）に示すように、第１層間絶縁膜３上に第２層間絶縁膜９を形成して、Ｌｉ層７ａとＬｉ層７ｂとを覆う。第２層間絶縁膜９は例えばシリコン酸化膜であり、その厚さは例えば８００ｎｍ程度である。 Next, the conductive film 7 is selectively etched using a photolithography technique and an etching technique, and an LI layer 7a made of, for example, Ti / TiN is formed on the first plug electrode 5 as shown in FIG. At the same time, an LI layer 7b made of, for example, Ti / TiN is formed on the first interlayer insulating film 3 in the alignment mark formation region. The Li layer 7a and the Li layer 7b may be connected at a portion (not shown) or may not be connected (that is, may not be electrically connected).
Next, as shown in FIG. 1C, a second interlayer insulating film 9 is formed on the first interlayer insulating film 3 to cover the Li layer 7a and the Li layer 7b. The second interlayer insulating film 9 is a silicon oxide film, for example, and has a thickness of about 800 nm, for example.

次に、図１（Ｄ）に示すように、フォトリソグラフィ技術及びエッチング技術を用いて第２層間絶縁膜９を選択的にエッチングし、第２層間絶縁膜９にＬＩ層７ａを底面とする第２ビアホールｈ２を形成すると共に、第２層間絶縁膜９にＬＩ層７ｂを底面とする開口部Ｈを形成する。図示しないが、第１、第２ビアホールｈ１、ｈ２の平面視での形状は例えば円形であり、その直径は例えば０．１〜１μｍ程度である。また、開口部Ｈの平面視での形状は例えば矩形で、その一辺の長さは例えば２〜３０μｍ程度である。   Next, as shown in FIG. 1D, the second interlayer insulating film 9 is selectively etched using a photolithography technique and an etching technique, and the second interlayer insulating film 9 has a LI layer 7a as a bottom surface. In addition to forming the two via holes h2, an opening H having the LI layer 7b as a bottom surface is formed in the second interlayer insulating film 9. Although not shown, the shape of the first and second via holes h1 and h2 in a plan view is, for example, a circle, and the diameter thereof is, for example, about 0.1 to 1 μm. The shape of the opening H in plan view is, for example, a rectangle, and the length of one side is, for example, about 2 to 30 μm.

次に、図２（Ａ）に示すように、第２ビアホールｈ２と開口部Ｈとが形成された第２層間絶縁膜９上にＷ膜１１を形成して、第２ビアホールｈ２と開口部Ｈとを埋め込む。Ｗ膜１１の形成は例えばＣＶＤ法で行う。そして、このＷ膜１１上にＣＭＰ処理を施して第２層間絶縁膜９上からＷ膜１１を取り除く。これにより、図２（Ｂ）に示すように、第２ビアホールｈ２内に第２プラグ電極１３を形成すると共に、ＬＩ層７ｂ上に合わせマーク１５を完成させる。なお、ＣＭＰ処理ではディッシングによって、合わせマーク１５の表面が多少凹んだ形状に形成される。   Next, as shown in FIG. 2A, a W film 11 is formed on the second interlayer insulating film 9 in which the second via hole h2 and the opening H are formed, and the second via hole h2 and the opening H are formed. And embed. The W film 11 is formed by, for example, a CVD method. Then, a CMP process is performed on the W film 11 to remove the W film 11 from the second interlayer insulating film 9. Thereby, as shown in FIG. 2B, the second plug electrode 13 is formed in the second via hole h2, and the alignment mark 15 is completed on the LI layer 7b. In the CMP process, the surface of the alignment mark 15 is formed in a slightly recessed shape by dishing.

次に、図２（Ｃ）に示すように、第２層間絶縁膜９上に酸化バリア膜１７を形成する。開口部Ｈ内のＷ膜（即ち、合わせマーク１５）の表面は、従来例と比べて段差少なく形成されているので、酸化バリア膜１７をカバレッジ性高く形成することができる。酸化バリア膜１７は、例えば、ＴｉＡｌＮ（下層）／Ｉｒ（中層）／ＩｒＯｘ（上層）からなる積層構造の膜である。ＴｉＡｌＮの厚さは例えば１００ｎｍ、Ｉｒの厚さは例えば５０ｎｍ、ＩｒＯｘの厚さは例えば１００ｎｍである。   Next, as shown in FIG. 2C, an oxidation barrier film 17 is formed on the second interlayer insulating film 9. Since the surface of the W film (that is, the alignment mark 15) in the opening H is formed with fewer steps than the conventional example, the oxidation barrier film 17 can be formed with high coverage. The oxidation barrier film 17 is a film having a laminated structure made of, for example, TiAlN (lower layer) / Ir (middle layer) / IrOx (upper layer). The thickness of TiAlN is 100 nm, the thickness of Ir is 50 nm, for example, and the thickness of IrOx is 100 nm, for example.

その後、第２層間絶縁膜９上に、ＳＢＴ、ＰＺＴ等の強誘電体膜（図示せず）を形成する。そして、強誘電体膜が形成された半導体基板１全体を酸素雰囲気中で高温熱処理する。熱処理の温度は例えば６００℃から８００℃程度である。このとき、Ｗ膜からなる合わせマーク１５はその上面が酸化バリア膜１７によってカバレッジ性高く覆われているので、その異常酸化を防止することができる。
このように、本発明の実施の形態によれば、選択的エッチングによって第２層間絶縁膜９に第２ビアホールｈ２と開口部Ｈとを形成する際に、ＬＩ層７ａ、７ｂをエッチングストッパに使用することができるので、第１層間絶縁膜３までエッチングが進行してしまうことを防ぐことができ、開口部Ｈを浅く形成することができる。 Thereafter, a ferroelectric film (not shown) such as SBT or PZT is formed on the second interlayer insulating film 9. Then, the entire semiconductor substrate 1 on which the ferroelectric film is formed is subjected to high temperature heat treatment in an oxygen atmosphere. The temperature of the heat treatment is, for example, about 600 ° C. to 800 ° C. At this time, since the upper surface of the alignment mark 15 made of the W film is covered with the oxide barrier film 17 with high coverage, the abnormal oxidation can be prevented.
Thus, according to the embodiment of the present invention, the LI layers 7a and 7b are used as etching stoppers when the second via hole h2 and the opening H are formed in the second interlayer insulating film 9 by selective etching. Therefore, the etching can be prevented from proceeding to the first interlayer insulating film 3, and the opening H can be formed shallowly.

従って、開口部Ｈ内をＷ膜で埋め込むことが容易であり、合わせマーク１５の表面の段差を小さくすることができる。これにより、合わせマーク１５の表面に酸化バリア膜１７をカバレッジ性高く形成することができるので、酸化バリア膜１７形成後の高温熱処理工程で合わせマーク１５の異常酸化を防止することができる。それゆえ、高温熱処理工程以降の工程への悪影響（例えば、合わせマークの膨張による位置合わせ精度の低下や、合わせマークからのパーティクル発生）を防止することができる。   Therefore, it is easy to fill the opening H with the W film, and the step on the surface of the alignment mark 15 can be reduced. As a result, the oxidation barrier film 17 can be formed on the surface of the alignment mark 15 with high coverage, and abnormal oxidation of the alignment mark 15 can be prevented in the high-temperature heat treatment step after the formation of the oxidation barrier film 17. Therefore, adverse effects on the processes after the high-temperature heat treatment process (for example, a decrease in alignment accuracy due to expansion of alignment marks and generation of particles from alignment marks) can be prevented.

この実施の形態では、半導体基板１が本発明の「基板」に対応し、第１層間絶縁膜３が本発明の「第１絶縁膜」に対応し、第２層間絶縁膜９が本発明の「第２絶縁膜」に対応している。また、ＬＩ層７ａが本発明の「局所配線」に対応し、ＬＩ層７ｂが本発明の「パッド層」に対応している。さらに、Ｗ膜１１が本発明の「金属膜」に対応している。
なお、この実施の形態では、第１層間絶縁膜３を例えば１０００ｎｍの厚さに形成し、第２層間絶縁膜９を例えば８００ｎｍの厚さに形成することについて説明したが、これらの数値はあくまで一例である。合わせマーク１５の表面の段差を小さくするためには、合わせマーク１５のサイズが大きい場合ほど、第１層間絶縁膜３を厚く形成し、第２層間絶縁膜９を薄く形成することが好ましい。 In this embodiment, the semiconductor substrate 1 corresponds to the “substrate” of the present invention, the first interlayer insulating film 3 corresponds to the “first insulating film” of the present invention, and the second interlayer insulating film 9 of the present invention. This corresponds to the “second insulating film”. The LI layer 7a corresponds to the “local wiring” of the present invention, and the LI layer 7b corresponds to the “pad layer” of the present invention. Further, the W film 11 corresponds to the “metal film” of the present invention.
In this embodiment, it has been described that the first interlayer insulating film 3 is formed with a thickness of, for example, 1000 nm and the second interlayer insulating film 9 is formed with a thickness of, for example, 800 nm. It is an example. In order to reduce the step on the surface of the alignment mark 15, it is preferable that the first interlayer insulating film 3 is formed thicker and the second interlayer insulating film 9 is formed thinner as the size of the alignment mark 15 is larger.

また、この実施の形態では、ＴｉＡｌＮ／Ｉｒ／ＩｒＯｘからなる積層構造の膜を酸化バリア膜１７として使用する場合について説明したが、その材質は上記に限られることはない。酸化バリア膜１７として例えば、ＴｉＮや、ＴｉＡｌＮ、Ａｌ2Ｏ3、ＴｉとＴｉＮの積層体等を使用することも可能である。
なお、この実施の形態で説明した合わせマーク１５は、露光機用アライメントマークのほか、ＢＯＸ ｍａｒｋ／ Ｖｅｒｎｉｅｒ ｍａｒｋ（合わせ検査マーク）、Ｌ ｍａｒｋ（マスクメーカが使用する挿入精度測定マーク）、レイヤーに挿入された文字、記号等として使用することも可能である。 In this embodiment, the case where a film having a laminated structure made of TiAlN / Ir / IrOx is used as the oxidation barrier film 17 has been described. However, the material is not limited to the above. For example, TiN, TiAlN, Al 2 O 3 , a laminate of Ti and TiN, or the like can be used as the oxidation barrier film 17.
The alignment mark 15 described in this embodiment is not only an alignment mark for an exposure machine, but also a BOX mark / Vernier mark (alignment inspection mark), L mark (insertion accuracy measurement mark used by a mask manufacturer), and inserted in a layer. It can also be used as a written character, symbol or the like.

実施の形態に係る半導体装置の製造方法を示す工程図（その１）。Process drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment (the 1). 実施の形態に係る半導体装置の製造方法を示す工程図（その２）。Process drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment (the 2). 従来例の問題点を示す図。The figure which shows the trouble of a prior art example.

符号の説明Explanation of symbols

１…半導体基板、３…第１層間絶縁膜、５…第１プラグ電極、７…導電膜、７ａ，７ｂ…ＬＩ層、９…第２層間絶縁膜、１１…Ｗ膜、１３…第２プラグ電極、１５…合わせマーク、１７…酸化バリア膜。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 3 ... 1st interlayer insulation film, 5 ... 1st plug electrode, 7 ... Conductive film, 7a, 7b ... LI layer, 9 ... 2nd interlayer insulation film, 11 ... W film, 13 ... 2nd plug Electrode, 15 ... alignment mark, 17 ... oxidation barrier film.

Claims (12)

基板と、
前記基板の上に形成された第１絶縁膜と、
前記第１絶縁膜に形成された第１ビアホールと、
前記第１ビアホールに形成された第１プラグ電極と、
前記第１絶縁膜および前記第１プラグ電極の上に形成された第１導電膜と、
前記第１絶縁膜の上であって、前記第１導電膜と離間して形成された第２導電膜と、
前記第１絶縁膜、前記第１導電膜および前記第２導電膜の上に形成された第２絶縁膜と、
前記第１導電膜の上であって、前記第２絶縁膜に形成された第２ビアホールと、
前記第２ビアホールに形成された第２プラグ電極と、
前記第２導電膜の上であって、前記第２絶縁膜に形成された開口部と、
前記開口部を埋め込むように形成された合わせマークと、
前記合わせマークの上に形成された酸化バリア膜と、
を含み、
前記上から見たとき、前記開口部は、該開口部の外周の内側の領域を全て含む、強誘電体メモリ。 A substrate,
A first insulating film formed on the substrate;
A first via hole formed in the first insulating film;
A first plug electrode formed in the first via hole;
A first conductive film formed on the first insulating film and the first plug electrode;
A second conductive film formed on the first insulating film and spaced apart from the first conductive film;
A second insulating film formed on the first insulating film, the first conductive film, and the second conductive film;
A second via hole formed on the first conductive film and formed in the second insulating film;
A second plug electrode formed in the second via hole;
An opening formed on the second conductive film and formed in the second insulating film;
An alignment mark formed to embed the opening;
An oxidation barrier film formed on the alignment mark;
Only including,
The ferroelectric memory , wherein when viewed from above, the opening includes the entire region inside the outer periphery of the opening . 請求項１において、
前記合わせマークは、タングステン膜からなる、強誘電体メモリ。 In claim 1,
The alignment mark is a ferroelectric memory made of a tungsten film. 請求項１または２において、
前記酸化バリア膜は、ＴｉＡｌＮを含む、強誘電体メモリ。 In claim 1 or 2,
The oxidation barrier film is a ferroelectric memory including TiAlN. 請求項１ないし３のいずれかにおいて、
前記第１導電膜は、第１ＴｉＮおよび該第１ＴｉＮ上に形成された第１Ｔｉからなり、
前記第２導電膜は、第２ＴｉＮおよび該第２ＴｉＮ上に形成された第２Ｔｉからなる、
強誘電体メモリ。 In any of claims 1 to 3,
The first conductive film is composed of first TiN and first Ti formed on the first TiN,
The second conductive film is composed of second TiN and second Ti formed on the second TiN.
Ferroelectric memory. 請求項１ないし４のいずれかにおいて、
前記開口部の底面は、前記第２導電層の上面である、強誘電体メモリ。 In any of claims 1 to 4,
A ferroelectric memory, wherein a bottom surface of the opening is an upper surface of the second conductive layer. 請求項１ないし５のいずれかにおいて、
前記第２絶縁膜の上に形成された強誘電体膜を含む、強誘電体メモリ。 In any of claims 1 to 5,
A ferroelectric memory comprising a ferroelectric film formed on the second insulating film. 基板の上に第１絶縁膜を形成する工程と、
前記第１絶縁膜に第１ビアホールを形成する工程と、
前記第１ビアホールに第１プラグ電極を形成する工程と、
前記第１絶縁膜および前記第１プラグ電極の上に導電膜を形成する工程と、
前記導電膜を選択的にエッチングして、前記第１プラグ電極の上に位置する第１導電膜と、前記第１導電膜と離間する第２導電膜を形成する工程と、
前記第１絶縁膜、前記第１導電膜および前記第２導電膜の上に第２絶縁膜を形成する工程と、
前記第２絶縁膜を選択的にエッチングして、前記第１導電膜の上に位置する第２ビアホールを形成すると共に、前記第２導電膜の上に位置する開口部を形成する工程と、
前記第２ビアホールに前記第２プラグ電極を形成すると共に、前記開口部を埋め込むように合わせマークを形成する工程と、
前記第２絶縁膜、前記第２プラグ電極および前記合わせマークの上に酸化バリア膜を形成する工程と、
を含み、
前記上から見たとき、前記開口部は、該開口部の外周の内側の領域を全て含む、強誘電体メモリの製造方法。 Forming a first insulating film on the substrate;
Forming a first via hole in the first insulating film;
Forming a first plug electrode in the first via hole;
Forming a conductive film on the first insulating film and the first plug electrode;
Selectively etching the conductive film to form a first conductive film located on the first plug electrode and a second conductive film spaced from the first conductive film;
Forming a second insulating film on the first insulating film, the first conductive film, and the second conductive film;
Selectively etching the second insulating film to form a second via hole located on the first conductive film and forming an opening located on the second conductive film;
Forming the second plug electrode in the second via hole and forming an alignment mark so as to fill the opening;
Forming an oxidation barrier film on the second insulating film, the second plug electrode, and the alignment mark;
Only including,
The method for manufacturing a ferroelectric memory , wherein when viewed from above, the opening includes the entire inner region of the outer periphery of the opening . 請求項７において、
前記合わせマークは、タングステン膜からなる、強誘電体メモリの製造方法。 In claim 7,
The method of manufacturing a ferroelectric memory, wherein the alignment mark is made of a tungsten film. 請求項７または８において、
前記酸化バリア膜は、ＴｉＡｌＮを含む、強誘電体メモリの製造方法。 In claim 7 or 8,
The method for manufacturing a ferroelectric memory, wherein the oxidation barrier film includes TiAlN. 請求項７ないし９のいずれかにおいて、
前記導電膜は、ＴｉＮおよび該ＴｉＮ上に形成されたＴｉからなる、強誘電体メモリの製造方法。 In any of claims 7 to 9,
The method for manufacturing a ferroelectric memory, wherein the conductive film is made of TiN and Ti formed on the TiN. 請求項７ないし１０のいずれかにおいて、
前記開口部の底面は、前記第２導電層の上面である、強誘電体メモリの製造方法。 In any of claims 7 to 10,
The method of manufacturing a ferroelectric memory, wherein a bottom surface of the opening is an upper surface of the second conductive layer. 請求項７ないし１１のいずれかにおいて、
前記第２絶縁膜上に強誘電体膜を形成する工程と、
酸素雰囲気中で熱処理を行う工程と、
を含む、強誘電体メモリの製造方法。 In any of claims 7 to 11,
Forming a ferroelectric film on the second insulating film;
Performing a heat treatment in an oxygen atmosphere;
A method for manufacturing a ferroelectric memory, comprising:
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