JP2012138443A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics of a semiconductor device.SOLUTION: A semiconductor device of the present invention comprises a semiconductor element formed above a semiconductor substrate, a first insulation film formed above the semiconductor element, and a fuse element F formed on the first insulation film and composed of a first conductive film containing aluminium (Al). The semiconductor device further comprises: first wiring formed on the first insulation film and composed of the first conductive film; and a second insulation film formed on the first wiring. A program region of the fuse element F is exposed on an opening OA1 provided in the second insulation film. During a period other than a program period of the fuse element F and a reading period of data programmed in the fuse element, both ends of the fuse element F are kept at ground potential. For example, one end of the fuse element F is connected to a ground potential and the other end is connected to a ground potential via a switching element.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a fuse.

  In a semiconductor device, a trimming technique is used. This trimming is to cut the fuse (a part of the pattern) to improve the characteristics of the device. For example, when a redundant circuit is provided and a connection with the redundant circuit is necessary, the fuse is cut and programming is performed to replace the defective portion. In addition, it is possible to change the connection relationship of various circuits and change the frequency to be used and the corresponding voltage by programming based on whether or not the fuse is cut.

  For example, in the following Patent Document 1 (Japanese Patent Application Laid-Open No. 2007-317882), in a fuse program circuit, program information and fuse selection information are sequentially transferred using a scan flip-flop, and the fuses are selectively electrically connected one by one. A technique for automatically cutting is disclosed. As a result, a fuse program circuit having a fuse element that has a low power consumption and a small occupied area and that can be programmed even after package mounting is realized.

  Further, in the following Patent Document 2 (Japanese Patent Laid-Open No. 2000-57933), the voltage difference applied to both ends of the fuse made of copper is set to 0 (zero), so that the copper regrows after the fuse is blown. A technique for preventing this is disclosed.

Patent Document 3 (Japanese Patent Laid-Open No. 2005-11935) discloses a technique for preventing Al corrosion by covering the side surface of an AlCu alloy film with an Al ₂ O ₃ coating.

JP 2007-317882 A JP 2000-57933 A JP 2005-11935 A

  In the semiconductor device having the fuse as described above, it is preferable to reduce the thickness of the insulating film on the fuse in order to improve the blowability (easy to cut) of the fuse. On the other hand, in order to improve the reliability of the fuse, it is preferable to cover the fuse with an insulating film.

  However, if the insulating film on the fuse is too thick, high energy is required for fusing the fuse, and there is a concern about the influence on other elements. Further, in order to reduce the thickness of the insulating film on the fuse, a high degree of etching control is required. In particular, as will be described later, when the pad region and the opening on the fuse are formed simultaneously, the etching control is further complicated.

  In the next-generation products, in order to cope with miniaturization, there is a great demand for thinning the wiring layer (fuse) itself and thinning the insulating film thereon. That is, as the wiring width and wiring pitch are reduced, the wiring layer (fuse) itself must be thinned. As the wiring width and wiring pitch are reduced, the contact hole diameter is also reduced. In this case, if the thickness of the insulating film on the wiring layer (fuse) is large, the aspect ratio of the contact hole becomes large, and a hole opening defect may occur. In order to improve the processing accuracy of fine contact holes, it is necessary to reduce the thickness of the insulating film on the wiring layer (fuse). As described above, when the insulating film on the wiring layer (fuse) itself is thinned, it becomes increasingly difficult to adjust the insulating film on the fuse so as to be within a predetermined film thickness range.

  Therefore, the present inventor examined the configuration of the semiconductor device capable of exposing the fuse itself. As described in detail later, the alteration of the wiring (Al, Ti, TiN) particularly on the power supply potential (VDD) side. As a result, various studies have been conducted on techniques for reducing characteristic deterioration due to such alteration.

  An object of the present invention is to provide a configuration of a semiconductor device that can improve the characteristics of the semiconductor device.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  Among the inventions disclosed in this application, a semiconductor device shown in a representative embodiment includes a semiconductor element formed above a semiconductor substrate, a first insulating film formed above the semiconductor element, And a fuse element made of a first conductive film containing aluminum (Al) formed on the first insulating film. The fuse element has a first wiring formed on the first insulating film and made of the first conductive film, and a second insulating film formed on the first wiring. Is exposed from the first opening provided in the second insulating film.

  Among the inventions disclosed in the present application, a semiconductor device shown in a typical embodiment includes a fuse element made of a conductive film containing aluminum, and includes a program period of the fuse element and a fuse element. In a period other than the programmed data reading period, both ends of the fuse element are maintained at the ground potential. For example, one end of the fuse element is connected to the ground potential, and the other end is connected to the ground potential via a switching element.

  Among the inventions disclosed in the present application, according to the semiconductor device described in the following representative embodiment, the characteristics of the semiconductor device can be improved.

1 is a main part sectional view showing a configuration of a semiconductor device according to a first embodiment; 3 is a plan view showing a configuration of a fuse element of the semiconductor device of First Embodiment. FIG. 3 is a cross-sectional view showing a configuration of a fuse element of the semiconductor device of First Embodiment. FIG. 3 is a cross-sectional view showing a configuration of a fuse element of the semiconductor device of First Embodiment. FIG. 3 is a circuit diagram showing a circuit to which the fuse element of the semiconductor device of the first embodiment is connected. FIG. 7 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of First Embodiment; FIG. 7 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 6 in the manufacturing process of the semiconductor device; FIG. 8 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 7 in the manufacturing process of the semiconductor device; FIG. 9 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 8 in the manufacturing process of the semiconductor device; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 9 in the manufacturing process of the semiconductor device; FIG. 11 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 10 in the manufacturing process of the semiconductor device; FIG. 12 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 11 in the manufacturing process of the semiconductor device; FIG. 13 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 12 in the manufacturing process of the semiconductor device; It is a top view which shows an example of the semiconductor chip after dicing. It is a top view which shows the structure of the trimming area | region of FIG. 6 is a cross-sectional view showing a manufacturing process (mounting process) of the semiconductor device of First Embodiment; FIG. It is a figure which shows the relationship between an initial setting period and a normal operation period. It is a circuit diagram which shows the 1st example of a determination circuit. It is a circuit diagram which shows the 2nd example of a determination circuit. FIG. 19 is a circuit diagram illustrating an example of a RIN signal generation circuit of the determination circuit illustrated in FIG. 18. It is a timing chart for demonstrating operation | movement of the determination circuit shown in FIG. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 24 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 23 in the manufacturing process of the semiconductor device; FIG. 25 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 24 in the manufacturing process of the semiconductor device; FIG. 26 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 25 in the manufacturing process of the semiconductor device; FIG. 27 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 26 in the manufacturing process of the semiconductor device; FIG. 6 is a circuit diagram showing a circuit to which a fuse element of a semiconductor device according to a third embodiment is connected. It is a photograph of the fuse element of the comparative example which this inventor examined. It is the figure which copied a part of photograph of FIG. It is a circuit diagram of a comparative example.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
Hereinafter, the configuration and manufacturing method of the semiconductor device of the present embodiment will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view of the main part showing the configuration of the semiconductor device of this embodiment. 2 to 4 are plan views or cross-sectional views showing the configuration of the fuse element of the semiconductor device of the present embodiment. 3 corresponds to, for example, the BB cross section of FIG. 2, and FIG. 4 corresponds to, for example, the CC cross section of FIG. FIG. 5 is a circuit diagram showing a circuit to which the fuse element of the semiconductor device of the present embodiment is connected.

[Description of structure]
First, a characteristic configuration of the semiconductor device of the present embodiment will be described with reference to FIGS.

  As shown in FIG. 1, the semiconductor device of the present embodiment includes, for example, a p-channel MISFET Qp and an n-channel MISFET Qn as semiconductor elements formed on a semiconductor substrate (substrate) 1. In addition to the MISFET, other elements such as a resistance element and a memory cell may be included.

  On these MISFETs (Metal Insulator Semiconductor Field Effect Transistors), an interlayer insulating film TH1 is formed. A first layer wiring M1 is formed on the source / drain regions (3n, 3p) of the MISFET via a plug P1. Further, a plurality of wiring layers (second layer wiring M2 to fifth layer wiring M5) are formed on the first layer wiring M1. Each wiring layer is electrically connected by plugs P2 to P5, and other regions are electrically insulated by interlayer insulating films TH2 to TH5. A fuse element (fuse element) F is formed in the same layer as the fifth layer wiring M5. The sixth layer wiring M6 and the fifth layer wiring M5 which are the uppermost layer wirings are electrically connected by the plug P6, and the other regions are electrically insulated by the interlayer insulating film TH6.

  The first layer wiring M1 to the sixth layer wiring M6 are Al wirings (wirings having a conductive film containing aluminum). A barrier film may be provided on the upper layer and the lower layer of the aluminum (Al) film, and the Al film and the upper and lower barrier films may be included in the Al wiring.

  Note that the first-layer wiring M1 to the fourth-layer wiring M4 may be configured using other conductive films (for example, copper (Cu)).

  A first protective film (12, 13) and a second protective film (photosensitive polyimide film 16) are formed on the sixth layer wiring M6, and the second protective film (photosensitive polyimide film 16) is formed from the opening OA2 of these films (12, 13, 16). Six-layer wiring (Al film) M6 is exposed. Further, the fuse element F (Fp) is exposed from the opening OA1 of the first protective film (12, 13), the second protective film (photosensitive polyimide film 16), and the interlayer insulating film TH6. Thus, in the present embodiment, the fuse element F has a bare structure. However, the fuse element F is covered with a sealing resin in a sealing process described later. The exposed portion of the sixth layer wiring M6 becomes a pad region Pd. Electrical connection between the semiconductor device (semiconductor chip) and the external terminals can be achieved via the wire (conductive member) W on the pad region Pd. Further, as will be described later, a part of the exposed portion of the fuse element F becomes a program area (cuttable area) Fp.

  Next, the configuration of the fuse element F will be described in detail. As shown in FIG. 2, one fuse element F is a part of a conductive film (wiring) formed in a line shape. A plurality of fuse elements F (line-shaped conductive films) are arranged at regular intervals.

  As described above, the fuse element F is a part of the wiring (the fifth layer wiring M5 in the present embodiment) and indicates a certain region (length) including the program region (meltable region) Fp. Shall. In other words, the portion other than the region is a wiring (here, the fifth layer wiring M5). The program area (meltable area) Fp is an area that is cut by flowing an overcurrent by a fusing circuit (93) described later (see FIG. 5).

  In the program area (Fp) of the five fuse elements F shown in FIG. 2, an uncut state is indicated as Fa, and a disconnected state is indicated as Fb. FIG. 3 is a cross-sectional view of the fuse element F in a cut state, and the conductive film is disconnected in the program region (Fp). FIG. 4 is a cross-sectional view of the fuse element F in an uncut state, in which the conductive film remains connected in the program region (Fp).

  Different information (data) can be stored (programmed) in the fuse element F depending on whether or not the program area (meltable area) Fp is cut by the fusing circuit (93) connected to the fuse element F (FIG. 5).

  Further, the data stored (programmed) in the fuse element F can be read out by the determination circuit (95) connected to the fuse element F (see FIG. 5). For example, the “disconnected state” is “1” data, and the “uncut state” is “0” data. As shown in FIG. 3, when the fuse elements F arranged from the left in the figure are Fb (cut), Fa (uncut), Fa (uncut), Fb (cut), Fa (uncut), The data of “0”, “1”, “1”, “0”, “1” is output by the determination circuit.

  Next, the configuration of the fuse element F and its peripheral circuits (melting circuit 93, determination circuit 95, etc.) will be described with reference to FIG.

  As shown in FIG. 5, one end (node n1) of the fuse element F is connected to the ground potential (GND, ground potential wiring, ground potential terminal), and the other end (node n2) of the fuse element F is connected to the transistor 91. To the power supply potential (VDD, power supply potential wiring). A determination circuit (read circuit, test circuit) 95 is connected to the other end (node n2) of the fuse element. The gate electrode of the transistor 91 is connected to the fusing circuit 93.

  Here, the other end (node n2) of the fuse element F of the present embodiment is connected to (GND, ground potential wiring, ground potential terminal) via a transistor (switching element) Ts.

  The fusing circuit 93 cuts (fuses) a predetermined fuse element F. Such a process is called a program process. In this programming step, the transistor (switching element) Ts is turned off, the transistor (MISFET) 91 is turned on, an overcurrent is passed through the fuse element F, etc. Perform electrical fusing.

  Further, the data stored in the fuse element F is read by the determination circuit 95. Such a process is called a reading process. In this reading step, the transistor (switching element) Ts is turned off.

  For example, when the fuse element F is cut (Fb), the other end (node n2) of the fuse element F becomes H level (high potential level), and a signal corresponding to this is sent from the determination circuit 95. Output and determine disconnection. That is, when the “cut state” is “0” data, “0” data is recognized. On the other hand, when the fuse element F is not cut (Fa), the other end (node n2) of the fuse element F becomes L level (low potential level), and a signal corresponding to this is output from the determination circuit 95, Judge uncut. That is, when the “uncut state” is “1” data, “1” data is recognized.

  Here, in the present embodiment, in the process (period) other than the program process (period) and the read process (period), the transistor (switching element) Ts is turned on and both ends of the fuse element F are turned on. (Node n1, Node n2) is connected to the ground potential (GND, ground potential wiring, ground potential terminal). Thus, by connecting both ends (node n1, node n2) of the fuse element F to the ground potential (GND, ground potential wiring, ground potential terminal), the fuse element F is protected by the protective film (12, 13, 16) and Even if it is exposed from the interlayer insulating film TH6, alteration of the fuse element F can be reduced.

  Therefore, the characteristics of the semiconductor device can be improved. Specific contents regarding the improvement of the characteristics will be described in detail later (see <1> to <3> below).

[Production method explanation]
Next, the manufacturing process of the semiconductor device of the present embodiment will be described with reference to FIGS. 1 to 13 and the configuration of the semiconductor device will be clarified. 6 to 13 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

  First, semiconductor elements (n-channel MISFET Qn and p-channel MISFET Qp) as shown in FIG. 1 are formed, and a plurality of wirings (M1 to M4) are formed thereon.

  There are no limitations on the method for forming the semiconductor elements (n-channel type MISFETQn and p-channel type MISFETQp) and the plurality of wirings (M1 to M4). For example, these can be formed by the following steps.

[Qn, Qp formation process]
For example, a trench is formed by etching a semiconductor substrate 1 made of p-type single crystal silicon, and an element isolation region 2 is formed by embedding, for example, a silicon oxide film as an insulating film in the trench. The element isolation region 2 defines an active region where the n-channel MISFET Qn is formed and an active region where the p-channel MISFET Qp is formed.

  Next, after ion-implanting p-type impurities into the active region of the semiconductor substrate 1 where the n-channel MISFET Qn is to be formed, the impurities are diffused by heat treatment to form a p-type well. In addition, an n-type well is formed by ion-implanting an n-type impurity into the active region of the semiconductor substrate 1 where the p-channel MISFET Qp is formed, and then diffusing the impurity by heat treatment. Next, for example, the surface of the semiconductor substrate 1 (p-type well and n-type well) is thermally oxidized to form a gate insulating film.

  Next, a polycrystalline silicon film doped with impurities is deposited on the gate insulating film, for example, as a conductive film, and the polycrystalline silicon film is etched to form the gate electrode G.

Next, n ⁻ type semiconductor regions are formed by ion-implanting n-type impurities into the p-type wells on both sides of the gate electrode G, and p-type impurities are ion-implanted into the n-type wells on both sides of the gate electrode G. ^- -type semiconductor regions.

  Next, after depositing, for example, a silicon nitride film as an insulating film on the entire surface of the semiconductor substrate 1, side wall spacers are formed on the side walls of the gate electrode G by anisotropic etching.

Next, an n ⁺ -type semiconductor region having an impurity concentration higher than that of the n ⁻ -type semiconductor region is formed by ion-implanting n-type impurities into the p-type well using the gate electrode G and the side wall spacer as a mask. A p ⁺ type semiconductor region having an impurity concentration higher than that of the p ⁻ type semiconductor region is formed by ion implantation of p type impurities into the n type well using the wall spacer as a mask.

Through the above steps, the source of the LDD (lightly Doped Drain) structure composed of the n ⁻ type semiconductor region and the n ⁺ type semiconductor region, the n channel MISFET Qn having the drain region 3n, and the p ⁻ type semiconductor region and the p ⁺ type semiconductor A p-channel MISFET Qp having a source / drain region 3p having an LDD structure composed of regions is formed.

  Next, after the surface of the semiconductor substrate 1 is cleaned, a metal silicide layer (for example, a salicide (Salicide: Self Aligned Silicide) technique is applied to the gate electrode G and the source and drain regions 3n and 3p as necessary. A cobalt silicide layer (not shown) is formed.

[M1-M4 formation process]
Next, a multilayer wiring is formed above the n-channel MISFET Qn and the p-channel MISFET Qp. Hereinafter, the formation process of the first layer wiring M1 to the fourth layer wiring M4 in the multilayer wiring will be described.

  First, as shown in FIG. 1, for example, a silicon oxide film is deposited as an insulating film on the n-channel MISFET Qn and the p-channel MISFET Qp by a CVD (Chemical Vapor deposition) method. Thereafter, if necessary, the surface of the silicon oxide film is polished by a chemical mechanical polishing (CMP) method to planarize the surface, thereby forming an interlayer insulating film TH1.

  Next, the interlayer insulating film TH1 is etched to form contact holes (connection holes) on the source and drain regions 3n and 3p, respectively. Next, a tungsten (W) film, for example, is deposited as a conductive film on the interlayer insulating film TH1 including the inside of the contact hole by the CVD method, and this W film is polished by the CMP method until the interlayer insulating film TH1 is exposed. Thus, a conductive film is embedded in the contact hole. By this step, a plug (contact plug) P1 is formed. Note that a barrier film made of a single layer film such as a titanium nitride (TiN) film or a titanium (Ti) film or a laminated film thereof may be provided below the W film.

  Next, as a barrier film (not shown) on the interlayer insulating film TH1 and the plug P1, for example, a laminated film of a titanium (Ti) film and a titanium nitride (TiN) film (hereinafter referred to as “TiN / Ti film”) Form.). First, a Ti film is formed by sputtering or the like on the interlayer insulating film TH1 and the plug P1, and a TiN film is formed thereon by sputtering or the like.

  Next, an aluminum (Al) film is formed on the barrier film by a sputtering method. Next, for example, a TiN / Ti film is formed as a barrier film on the Al film by a sputtering method or the like.

  Next, a silicon oxynitride film (SiON film, not shown in FIG. 1) is formed as an antireflection film on the barrier film by a CVD method or the like.

  By the above process, a laminated conductive film in which TiN / Ti / Al / TiN / Ti is laminated in order from the lower side and an antireflection film on the upper part thereof are formed.

  The barrier film may be a single layer film of a Ti film or a TiN film. Further, a TiN film may be used as an antireflection film, and the SiON film may be omitted. Moreover, the Al film said here should just contain 50 weight% or more of Al as a main component, and may contain another metal. For example, an alloy containing about several percent of Cu (copper) may be used.

  Next, a photoresist film (not shown) is applied on the laminated conductive film and the antireflection film, and exposed and developed (photolithography) to leave the photoresist film in the formation region of the first layer wiring M1. Thus, the use of an antireflection film can improve the pattern accuracy. That is, in the photoresist film, irradiation light is reflected from the Al film at the time of exposure, and it is possible to prevent poor resolution due to interference between the irradiation light and the reflected light.

  Next, the first layer wiring (Al wiring) M1 is formed by etching (patterning) the laminated film and the antireflection film using the photoresist film as a mask.

  Next, a silicon oxide film, for example, is deposited as an insulating film on the first layer wiring M1 by the CVD method. Thereafter, if necessary, the surface of the silicon oxide film is polished by a CMP method to planarize the surface, thereby forming an interlayer insulating film TH2.

  Next, by etching the interlayer insulating film TH2, a contact hole (connection hole) is formed on the first layer wiring M1. Next, for example, a TiN / Ti film is formed as a barrier film (not shown) on the interlayer insulating film TH2 including the inside of the contact hole by using a sputtering method, and then a W film is deposited by the CVD method. Next, the conductive film is embedded in the contact hole to form the plug P2 by polishing the W film or the like by CMP until the interlayer insulating film TH2 is exposed.

  A laminated conductive film and an antireflection film in which TiN / Ti / Al / TiN / Ti are sequentially laminated from the lower side are formed on the interlayer insulating film TH2 including the inside of the contact hole, and then the photoresist film is masked. Alternatively, the plug P2 and the second layer wiring (Al wiring) M2 may be formed simultaneously by etching (patterning) the laminated conductive film and the antireflection film.

  Next, an interlayer insulating film TH3 is formed on the second layer wiring M2 in the same manner as the interlayer insulating film TH2, and a plug P3 is formed in the interlayer insulating film TH3 in the same manner as the plug P2. Further, the third layer wiring (Al wiring) M3 is formed on the interlayer insulating film TH3 and the plug P3 in the same manner as the second layer wiring (Al wiring) M2.

  Next, an interlayer insulating film TH4 is formed in the same manner as the interlayer insulating film TH2 on the third layer wiring M3, and a plug P4 is formed in the interlayer insulating film TH4 in the same manner as the plug P2. Further, a fourth layer wiring (Al wiring) M4 is formed on the interlayer insulating film TH4 and the plug P4 in the same manner as the second layer wiring (Al wiring) M2.

  As with the plug P2 and the second layer wiring (Al wiring) M2, the plug P3 and the third layer wiring (Al wiring) M3 may be formed simultaneously, or the plug P4 and the fourth layer wiring (Al wiring). M4 may be formed at the same time.

[M5, F, M6, Pd formation process]
Next, after forming the fifth layer wiring M5 and the fuse element F, the sixth layer wiring (Al wiring) M6 which becomes the uppermost layer wiring is formed through the interlayer insulating film TH6, and the protective film (12, 13) is formed thereon. , 16), and a part thereof is exposed to form a pad region (Al pad, pad, bonding pad, opening) Pd. The process will be described in detail with reference to FIGS. 6 to 11 correspond to a partially enlarged portion in the vicinity of the fuse element and the pad region in FIG.

  First, as shown in FIGS. 1 and 6, an interlayer insulating film TH5 is formed on the fourth-layer wiring M4 in the same manner as the interlayer insulating film TH2, and a plug P5 is formed in the interlayer insulating film TH5 in the same manner as the plug P2. Form. Further, the fifth-layer wiring (Al wiring) M5 is formed on the interlayer insulating film TH5 and the plug P5 in the same manner as the second-layer wiring (Al wiring) M2. At this time, the fuse element F is also formed at the same time. .

  That is, as the barrier film 5a, for example, a TiN / Ti film is formed on the interlayer insulating film TH5 and the plug P5 by a sputtering method or the like. Next, an Al film 5b is formed on the barrier film 5a by a sputtering method, and a TiN / Ti film, for example, is formed thereon as the barrier film 5c by a sputtering method or the like. Next, a silicon oxynitride film (SiON film) is formed as an antireflection film AR on the barrier film 5c by a CVD method or the like. Through the above steps, the laminated conductive films (5a, 5b, 5c) in which TiN / Ti / Al / TiN / Ti are sequentially laminated from the lower side and the antireflection film AR on the upper side thereof are formed.

  Next, a photoresist film (not shown) is applied on the laminated conductive films (5a, 5b, 5c) and the antireflection film AR, and is exposed and developed (photolithography), thereby forming the formation region of the fifth layer wiring M5 and The photoresist film is left in the formation region of the fuse element F. Next, the fifth layer wiring (Al wiring) M5 and the fuse element F are formed by etching (patterning) the laminated conductive films (5a, 5b, 5c) and the antireflection film AR using the photoresist film as a mask. To do.

  The fuse element F is formed in a line shape as described above (see FIG. 2), and both ends thereof are connected to various terminals and circuits (see FIG. 5). This terminal is a wiring (M1 to M6) or a part of the wiring, and the circuit is composed of a wiring and a plurality of elements (for example, Qn, Qp, etc.).

  As described above, the fuse element F is a part of the wiring (fifth layer wiring M5). That is, the upper part and the lower part (parts other than the certain area) of the plurality of fuse elements F shown in FIG. 2 are the fifth layer wiring M5. Needless to say, the fifth layer wiring M5 is connected to the fuse element F as well as to other wirings, elements, and pad regions (Pd) (see FIG. 1).

  Next, a silicon oxide film, for example, is deposited as an insulating film on the fifth layer wiring M5 and the fuse element F by the CVD method. Thereafter, if necessary, the surface of the silicon oxide film is polished by CMP to planarize the surface, thereby forming an interlayer insulating film TH6.

  Next, by etching the interlayer insulating film TH6, a contact hole (connection hole) is formed on the fifth layer wiring M5. Next, for example, a TiN / Ti film is formed as a barrier film (not shown) on the interlayer insulating film TH6 including the inside of the contact hole by using a sputtering method or the like, and then a W film is deposited by the CVD method. Next, by polishing the W film or the like by CMP until the interlayer insulating film TH6 is exposed, the plug P6 is formed by embedding a conductive film in the contact hole.

  Next, as shown in FIG. 7, a TiN / Ti film, for example, is formed as a barrier film 6a on the interlayer insulating film TH6 and the plug P6 by a sputtering method or the like.

  Next, an Al film 6b is formed on the barrier film 6a by a sputtering method. Next, for example, a TiN film (single layer film) is formed as a barrier film 6c on the Al film 6b by a sputtering method or the like.

  Next, a silicon oxynitride film (SiON film) is formed as an antireflection film AR on the barrier film 6c by a CVD method or the like.

  By the above process, a laminated conductive film in which TiN / Ti / Al / TiN is laminated in order from the lower side and an antireflection film AR on the upper side thereof are formed.

  Next, a photoresist film (not shown) is applied on the laminated conductive films (6a, 6b, 6c) and the antireflection film AR, and exposed and developed (photolithography) to form a sixth layer wiring M6 formation region. The photoresist film is left. Next, by using the photoresist film as a mask, the laminated conductive films (6a, 6b, 6c) and the antireflection film AR are etched (patterned) to form a sixth layer wiring (Al wiring) M6.

  The sixth layer wiring (Al wiring) M6 is the uppermost layer wiring, and the film thickness (total film thickness of the laminated conductive film made of TiN / Ti / Al / TiN) is lower than the wiring (M1 to M1). It is larger than the total film thickness of the laminated conductive film made of TiN / Ti / Al / TiN / Ti of M5. In particular, the thickness of the Al film 6b constituting the sixth layer wiring (Al wiring) M6 is larger than the thickness of Al constituting the lower layer wiring. Further, the wiring width of the sixth layer wiring (Al wiring) M6 is larger than the wiring width of the lower layer wirings (M1 to M5).

  Next, as illustrated in FIG. 8, for example, a stacked film of a silicon oxide film 12 and a silicon nitride film 13 is formed as a first protective film (first insulating film) on the sixth layer wiring M <b> 6. Each of these films can be formed by a plasma CVD method.

  Next, as shown in FIG. 9, a photoresist film R is applied on the silicon nitride film 13. Next, as shown in FIG. 6, the photoresist film R in the openings OA1 and OA2 is removed by exposing and developing the photoresist film R. The opening OA1 is, for example, a certain area including the program area (cuttable area) Fp. The opening OA2 corresponds to a pad region Pd described later.

  Next, as shown in FIG. 10, the silicon nitride film 13 of the first protective films (12, 13) is etched using the photoresist film R as a mask. Next, the underlying silicon oxide film 12 is etched. Next, as shown in FIG. 11, the antireflection film AR on the sixth layer wiring M6 is etched to expose the surface of the sixth layer wiring M6, that is, the surface of the barrier film (TiN film) 6c. At this time, the silicon oxide film 12 and the interlayer insulating film (silicon oxide film) TH6 above the fuse element F are etched, and the antireflection film AR on the fuse element F is also etched. Therefore, the surface of the fuse element F, that is, the surface of the barrier film (TiN film) 5c is exposed.

  Next, as shown in FIG. 12, the Al film 6b is exposed by etching the barrier film 6c in the sixth layer wiring (Al wiring) M6. The exposed region of the Al film 6b becomes a pad region Pd. At this time, in the opening OA1, the barrier film 5c in the fuse element F is etched, and the Al film 5b is exposed. A part of the barrier film 5c (for example, the lower Ti film) may remain on the uppermost layer of the fuse element F.

  Here, although only one pad region Pd is shown in FIG. 12 and the like, a plurality of pad regions Pd are formed inside the semiconductor device (semiconductor chip) (see FIG. 14). Therefore, over-etching may be performed to prevent non-opening of the pad region Pd. That is, even after the barrier film 6c is etched and the surface of the Al film 6b is exposed, the etching may be continued to retreat the surface of the Al film 6b in the pad region Pd. Next, the photoresist film R is removed by ashing or the like. Note that after the etching of the silicon nitride film 13, the photoresist film R may be removed, and the lower layer may be etched using the silicon nitride film 13 as a mask.

  Next, as shown in FIG. 13, a photosensitive polyimide film (PIQ film: Polyimide-isoindoloquinazolinedion film) 16 is formed as a second protective film on the first protective film (on the silicon nitride film 13) including the pad region Pd. Apply. Next, the photosensitive polyimide film 16 is exposed and developed to remove the photosensitive polyimide film 16 in the openings OA1 and OA2. By this step, the Al film 6b (pad region Pd) and the surface of the fuse element F are exposed again from the opening OA2.

  In FIG. 13, the opening OA2 of the first protective film (silicon oxide film 12, silicon nitride film 13) and the opening OA2 of the second protective film (photosensitive polyimide film 16) have the same size. The opening of the second protective film may be larger than the opening OA1 of the first protective film. Similarly, the opening OA1 of the first protective film (12, film 13) and the interlayer insulating film and the opening OA1 of the second protective film (photosensitive polyimide film 16) have the same size. The opening may be larger than the opening OA1 of the first protective film. Next, the photosensitive polyimide film (second protective film) 16 is cured by performing heat treatment (curing treatment).

  Through the above process, the semiconductor element (Qn, Qp), the multilayer wiring (M1 to M6) and the fuse element F thereon are substantially completed.

  Next, an operation test of the semiconductor device is performed using the pad region Pd. In this way, determining whether the semiconductor device (integrated circuit) is good or bad in the pre-process (before dicing, wafer state) of the manufacturing process of the semiconductor device is called “wafer test”.

  As this wafer test, for example, an electrical signal can be applied to the pad region Pd via a probe needle, and a signal obtained from the pad region Pd can be detected to test the electrical characteristics of the semiconductor device. (Probe test). From this test result, the quality of the semiconductor device (integrated circuit) can be determined.

  Although there is no limitation on the content of the test, for example, it is possible to check whether data can be written to the memory cell and the data holding time. Thereby, when a defect is confirmed in the memory cell, so-called redundancy repair is performed.

  For example, a redundant circuit is formed in advance, and when connection with the redundant circuit is necessary, the fuse is cut and programming is performed to replace the defective portion. This programming is performed depending on whether or not the fuse is cut. That is, data is stored depending on whether or not a fuse element (fuse ROM; Read Only Memory) F is cut, and whether or not the fuse element F is conductive is determined when the semiconductor element is driven. Thus, information (trimming information) recorded in the fuse element F is read, and a semiconductor device (for example, a memory) is driven based on the read data, whereby a normal redundant circuit can be operated.

  Here, the programming for the fuse element F has been described by taking the redundancy relief as an example. However, the trimming information other than the redundancy relief, such as changing the frequency to be used and the corresponding voltage based on the trimming information. Can also be used.

[Programming process]
Next, the fuse element F is programmed. That is, for example, it is determined which fuse element F is to be cut according to the result of the probe test and the specifications (frequency and corresponding voltage) of the semiconductor device, and the corresponding fuse element F is cut. Information on which fuse element F is to be cut is referred to as test information. Based on this test information, an overcurrent is caused to flow from the aforementioned fusing circuit (93, FIG. 5) to the fuse to be cut, and the program area (cuttable area) Fp of the fuse element F is cut (non-conductive state). As described above, in this programming step, the transistor (switching element) Ts is turned off.

[Mounting process]
After the probe test process, the semiconductor substrate (wafer) 1 is cut (diced) and separated into a plurality of semiconductor chips CHP (divided into individual pieces). Note that the semiconductor substrate 1 may be thinned by performing back surface grinding of the semiconductor substrate (wafer) 1 before dicing. FIG. 14 shows an example of the semiconductor chip after dicing. As illustrated, the semiconductor chip CHP cut into a substantially rectangular shape includes, for example, a CPU (Central Processing Unit) region 50, a memory region 60, an analog circuit region 70, a trimming region 80, and the like. FIG. 15 is a plan view showing the configuration of the trimming region of FIG. As shown in FIG. 15, the trimming region 80 includes a test information circuit TC and a plurality of fuse elements (fuse circuits) F.

  FIG. 16 is a cross-sectional view showing the mounting process of the semiconductor device of the present embodiment. Next, as shown in FIG. 16, the semiconductor chip CHP is mounted (adhered) on the wiring board WB (die bonding). Terminals (external terminals) TE are formed on the chip mounting surface side of the wiring board WB. Next, the pad region Pd formed on the semiconductor chip CHP and the terminal TE formed on the wiring board WB are connected by a wire (conductive member) W made of a gold wire or the like (wire bonding).

  Thereafter, the semiconductor chip CHP and the wire W are sealed with a sealing resin (mold resin) MR. This sealing resin MR is provided to protect the semiconductor chip CHP from external impacts and impurities. Subsequently, solder balls SB serving as external connection terminals are formed on the back surface (surface opposite to the chip mounting surface) of the wiring board WB.

[Description of circuit operation of semiconductor device]
Next, circuit operation of the semiconductor device will be described. The semiconductor device is incorporated into various electronic devices such as a PC (Personal computer) and a mobile phone.

  For example, when power is supplied to these electronic devices, trimming information (various setting information) is read during an initial setting period, and the information is stored in a predetermined area (for example, a memory area shown in FIG. 14). Or analog circuit area). Thereafter, desired operations (normal operation, typically image processing, control processing of various electronic devices in which a semiconductor device is incorporated, analog-digital conversion processing, sensor output processing, and the like) are performed.

  That is, in the initial setting period, the data stored in the fuse element F is read by the above-described determination circuit 95 (see FIG. 5). Hereinafter, the circuit operation of the semiconductor device in the reading process will be described with reference to FIGS. As described above, in this reading process, the transistor (switching element) Ts is in an off state.

  FIG. 17 is a diagram illustrating the relationship between the initial setting period and the normal operation period. FIG. 18 is a circuit diagram illustrating a first example of the determination circuit. FIG. 19 is a circuit diagram illustrating a second example of the determination circuit. FIG. 20 is a circuit diagram showing an example of a RIN signal generation circuit of the determination circuit shown in FIG. FIG. 21 is a timing chart for explaining the operation of the determination circuit shown in FIG.

  As shown in FIG. 17, the operation of the semiconductor device has an initial setting period T1 and a subsequent normal operation period T2. The read operation is performed during the initial setting period T1. That is, the reading period Tr is included in the initial setting period T1.

<First example>
In the determination circuit shown in FIG. 18, one end (node n1) of the fuse element F is connected to the ground potential (GND). The other end (node n2) of the fuse element F is connected to the power supply potential (VDD) via the resistance element Re and the n-channel type MISFET Tn. A connection node between the fuse element F and the resistance element Re is an output unit OUT.

  For example, in the determination circuit shown in FIG. 18, the signal S applied to the gate electrode of the n-channel type MISFET Tn rises, that is, changes from L level to H level, so that the reading period starts.

  As the signal S rises, the n-channel MISFET Tn is turned on. At this time, if the fuse element F is in a cut state, an H level signal is output from the output unit OUT. When the fuse element F is not cut, an L level signal is output from the output unit OUT. After the read data is written (stored) in a predetermined area (for example, a memory area or an analog circuit area shown in FIG. 14), the signal S falls (H level → L level), and the read period Tr is set. finish. After the initial setting such as reading of data recorded in the fuse element F is completed, the normal operation is performed.

  The n-channel MISFET (switching element) Ts is turned off during the readout period (between the rise and fall of the signal S; Tr), and the n-channel MISFET (switching element) is turned off after the readout period ends. Ts is turned on.

<Second example>
In the determination circuit shown in FIG. 19, one end (node n1) of the fuse element F is connected to the ground potential (GND). The other end (node n2) of the fuse element F is connected to the power supply potential (VDD) via the p-channel type MISFETs Tp1, Tp2 and the n-channel type MISFETs Tn3, Tn4. A connection node between the p-channel type MISFET Tp2 and the n-channel type MISFET Tn3 is defined as an output node Nout.

  The other end (node n2) of the fuse element F is connected to the ground potential (GND) via the n-channel type MISFET Ts.

  A TSFIN signal is input to the TSFIN section. The TSFIN section is connected to the gate electrode of the p-channel type MISFET Tp2 through the buffer (buffer circuit) BU1, the inverter (inverter circuit) INV1, and the inverter INV2. The output part of the inverter INV1 is connected to the gate electrode of the n-channel type MISFET Tn3.

  The RIN signal is input to the RIN unit. This RIN portion is connected to the gate electrode of the n-channel type MISFET Tn4 through the buffer BU2 and the inverter INV3. The input part of the inverter INV3 is connected to the gate electrode of the n-channel type MISFET Ts, and the output part of the inverter INV3 is connected to the gate electrode of the p-channel type MISFET Tp1.

  A latch circuit is connected between the output node (first output node) Nout and the FOUT section that is the output section (second output node) of the determination circuit.

  That is, the output node (first output node) Nout and the FOUT unit that is the output unit (second output node) of the determination circuit are connected via the inverters INV4 and INV5. In addition, p-channel MISFETs Tp5 and Tp6 are connected between the node n3 (output node Nout) and the power supply potential VDD. N-channel MISFETs Tn7, Tn8, and Tn9 are connected between the node n3 (output node Nout) and the ground potential GND.

  The gate electrodes of the p-channel type MISFETs Tp5 and Tp6 and the n-channel type MISFETs Tn7 and Tn8 are connected to the output part of the inverter INV4. The gate electrode of the n-channel type MISFET Tn9 is connected to the output part of the inverter INV2.

  The RIN signal and the TSFIN signal are generated by the circuit shown in FIG. As shown in FIG. 20, the buffer BU3 is connected to the SFC unit to which the SFC signal is input, and the output unit of the buffer BU3 is connected to the second input terminal of the NAND circuit. The output part of this NAND circuit is connected to the RIN part. On the other hand, a first delay circuit D1, a second delay circuit D2, and an inverter INV6 are connected between the SFC unit and the first input terminal of the NAND circuit. A connection node between the first delay circuit D1 and the second delay circuit D2 is connected to the TSFIN section via the buffer BU4. The delay time defined by the first delay circuit D1 corresponds to t1 described later, and the delay time defined by the second delay circuit D2 corresponds to t2 described later.

  As shown in FIG. 21, in the read standby state before the read period, the SFC signal is at the L level, and the SFC signal changes from the L level to the H level (time t0, (a)). After t1 period from the time when this SFC signal becomes H level, the TSFIN signal becomes H level (b). After the rise of the SFC signal, the RIN signal becomes H level after the period t2 (c). That is, the RIN signal becomes L level during the period t1 + t2 (reading period Tr) (c).

  As the RIN signal falls (from H level to L level), the n-channel MISFET (switching element) Ts is turned off. Further, when the fuse element F is in a disconnected state with the fall of the RIN signal (H level → L level), the potential of the node n2 becomes H level and the potential of the output node Nout becomes H level. At this time, an H level signal is output from the output unit FOUT (e). On the other hand, when fuse element F is in an uncut state, the potential of node n2 is at L level and the potential of output node Nout is at L level. At this time, an L level signal is output from the output unit FOUT (e).

  At time t1, the TSFIN signal rises (L level → H level). In response to this, Tp2 and Tn3 are turned off, but the potential of the output node Nout is not changed because it is stored by the latch circuit at the subsequent stage. Further, the potential of the output portion (FOUT) does not change.

  After this (after time t1 + t2), the RIN signal rises (L level → H level). Thereby, the node n2 is connected to the ground potential regardless of the state of the fuse element (whether the cut state is the uncut state), so that the potential becomes L level (d). However, as described above, the potentials of the output node Nout and the output unit (FOUT) are maintained by the above-described latch circuit.

  In the above operation, the data of the fuse element F is latched during the first read period (t1), and the node n2 is in the state of the fuse element (the cut state is not cut) after a subsequent read margin period (t2). It is fixed at the ground potential regardless of the state). Here, the sum (t1 + t2 = Tr) of the first reading period (t1) and the reading margin period (t2) is set as the reading period. The latched data is output after t1 + t2. The read period described in the first and second examples is a period (determination storage time) in which data is stored in a latch or the like after fuse information is determined.

  As described above, also in the second example, the n-channel MISFET (switching element) Ts is turned off in the read period, and the n-channel MISFET (switching element) Ts is turned on after the read period ends. (ON) state.

  The effects of the present embodiment described in detail above are shown in <1> to <3> below.

  <1> FIG. 29 is a photograph of a comparative fuse element examined by the present inventors. FIG. 30 is a copy of a part of the photograph of FIG. FIG. 31 is a circuit diagram of a comparative example.

  A comparative example (see FIG. 31) in which the transistor (switching element) Ts is not provided between the other end (node n2) of the fuse element F and the ground potential (GND, ground potential wiring) as in the present embodiment. The present inventor examined. In this case, as shown in FIGS. 29 and 30, alteration of the conductive film was confirmed at the end of the fuse element F. In FIG. 30, the altered region is indicated by z. This altered region z was confirmed on the side to which the power supply potential (VDD, Vcc) was applied, as shown in FIGS.

  Specifically, the alteration is caused by oxidation due to a reaction between the remaining barrier film and moisture in the semiconductor device. Due to the oxidation reaction of Ti in the Ti film or TiN film, TiOx is generated and volume expansion occurs. For this reason, stress is generated on the Ti film, the TiN film itself, and the surrounding film, and cracks are generated. The crack causes peeling of the film. Further, when a crack is generated, it is considered that moisture and impurities are supplied through the crack, further deterioration occurs, and a defect may occur in the semiconductor device (semiconductor chip). As described above, this alteration occurs particularly on the power supply potential (VDD) side. As shown in FIG. 31, in the circuit of the comparative example, a potential difference (bias) is generated between both ends of the fuse element F (between the node n1 and the node n2), and the charge is increased on the high potential side (VDD side). Since it is continuously supplied, it is considered that the oxidation reaction is performed. In the comparative example, since the insulating film and the barrier film are left on the fuse element F, the barrier film is deteriorated as described above. However, when the Al film is exposed, the oxidation of Al is performed. Such alterations may also occur.

  Further, when forming the fuse element F (etching of the Al film), a chlorine (Cl) -based etchant (etching gas or etchant) is often used. For this reason, Cl can remain around the fuse element F even after various cleaning steps. Further, a chlorine (Cl) -based material may be used in various processes, and even when the above-described Cl-based etchant is not used for etching an Al film, Cl may exist around the fuse element F. .

In this case, the potential difference occurs in the Al film, at the anode side, Al juxtamembrane water (hydroxide) is Cl level ^- by reacting with ions, thereby to produce a soluble salt. The reaction at this time becomes Al (OH) ₃ + Cl ⁻ → Al (OH) ₂ Cl + OH ⁻ . Further, the Al film reacts with Cl ⁻ ions to become Al + 4Cl ⁻ → AlCl ₄ ⁻ + 3e ⁻ . This AlCl ₄ ⁻ becomes AlCl ₄ ⁻ + 3H ₂ O → Al (OH) ₃ + 3H ⁺ + 4Cl ⁻ by further reaction with moisture. The production of Al (OH) ₃ causes the volume of the Al film to expand and causes cracks and the like. In addition, since Cl ⁻ ions generated again repeat the reaction, a large amount of alteration can occur even with a small amount of Cl ⁻ ions.

  On the other hand, in the present embodiment, in the steps other than the programming step and the reading step, the transistor (switching element) Ts is turned on and both ends (node n1, node n2) of the fuse element F are connected. Connect to ground potential (GND). Thus, even if the fuse element F is exposed from the protective film (12, 13, 16) by connecting both ends (node n1, node n2) of the fuse element F to the ground potential (GND), the fuse element Alteration of various films (Al, Ti, TiN) constituting F can be reduced. Thus, the reliability of the semiconductor device can be improved.

  <2> Further, the etching control of the insulating film on the fuse element F is facilitated. In the comparative example, the insulating film on the fuse element F is often left in order to minimize the alteration of the fuse element F and improve the quality. However, if the remaining amount of the insulating film is large, the energy required for fusing the fuse element F increases, so that the remaining amount of the insulating film is a predetermined film thickness (for example, a film thickness of about 100 to 400 μm). It is desirable to adjust so that

  On the other hand, as described in the above process, the etching of the insulating film on the fuse element F is performed simultaneously with the opening of the pad region Pd. As described above, in the pad region Pd, a complete opening is required, but the insulating film on the fuse element F must have a predetermined film thickness. Therefore, etching controllability becomes difficult. That is, it is necessary to select an etchant with little etching variation, or to devise measures such as reducing the etching rate and improving its controllability.

  On the other hand, according to this embodiment, since the fuse element F is exposed, it is not necessary to adjust the remaining film of the insulating film on the fuse element F, and the controllability of etching is improved. Thus, a semiconductor device can be formed with a simple manufacturing process. In addition, throughput can be improved in manufacturing a semiconductor device. Further, it is possible to cope with the thinning of the insulating film on the fuse element F.

  In the comparative example, the alteration of the fuse element F may occur after the mounting process. Therefore, at the time of product shipment, even if it is a non-defective product, quality deterioration due to alteration of the fuse element F may occur during subsequent use. On the other hand, in the present embodiment, even during product operation (in use), the transistor (switching element) Ts is turned on (ON) in the processes other than the program process, and both ends of the fuse element F ( Since the nodes n1 and n2) are connected to the ground potential (GND), the reliability of the semiconductor device can be improved.

  <3> In the present embodiment, since at least the program area (cuttable area) Fp of the fuse element F is exposed, the energy required for fusing can be reduced. Moreover, the controllability of energy required for fusing is improved. That is, when the insulating film remains on the fuse element F as in the comparative example described above, the energy required for fusing increases. In addition, the film thickness of the insulating film on the fuse element F is likely to vary, and if the allowable range of the remaining film thickness is increased, the energy at the time of fusing is inevitably increased. In this case, due to variations in the insulating film, extra energy is applied to the portion where the film thickness is small, and the adjacent fuse element F, the underlying wiring or element, etc. are likely to be damaged, causing a defect. Further, the residue of the conductive film in the upper layer portion of the fuse element F is likely to remain, and so-called uncut portions are likely to occur.

  On the other hand, according to the present embodiment, since the fuse element F is exposed, the energy required for fusing can be reduced, and the energy required for fusing can be optimized. Therefore, a necessary site can be accurately cut. In addition, defects due to application of excessive energy can be reduced. Thus, the reliability of the semiconductor device can be improved. In addition, the characteristics of the semiconductor device can be improved.

  As shown in <1> to <3> above, according to the present embodiment, the characteristics of the semiconductor device can be improved.

  In the present embodiment, the fuse element F is programmed in the pre-process of the semiconductor device manufacturing process (before dicing, in the wafer state) (see the column “Programming process” above). The programming process is not limited to such a stage, and may be performed after the mounting process, for example. In particular, as described above, when the fuse element F is cut by electric fusing, the product user can also program the fuse element F.

  In the present embodiment, wire bonding has been described as an example, but face-down bonding may be performed.

  For example, after performing the probe test, a bump electrode may be formed on the pad region Pd, mounted on the wiring board with the bump electrode formation side (face side) facing down, and sealed with resin.

  In the present embodiment, the first to sixth layer wirings (M1 to M6) are formed, but the total number of wirings is not limited. In the present embodiment, the fuse element F is formed in the same layer as the fifth layer wiring M5. However, the present invention is not limited to this. For example, in the same layer as the sixth layer wiring (uppermost layer wiring) M6. A fuse element F may be formed. However, as described above, the uppermost wiring layer has a large width and a thick wiring is often used. When the fuse element F is formed in the same manner as the wiring, the energy required for fusing increases. Therefore, it is preferable to form the fuse element in the same layer as the first to fifth layer wirings (M1 to M5) that are thinner (for example, 250 nm or less) and narrower than the uppermost layer wiring. Further, the fuse element F may be formed in the same layer as the first to fourth layer wirings (M1 to M4). However, when the fuse element F is formed in the same layer as the underlying wiring, the etching amount when the fuse element F is exposed increases. Therefore, it is preferable to form the fuse element F in the same layer as the wiring (here, the fifth layer wiring M5) which is lower than the uppermost layer wiring and positioned as high as possible. In the case of a semiconductor device having rearrangement wiring, this rearrangement wiring is not the uppermost layer wiring.

  In the above process, the MISFET formation process is exemplified as the semiconductor element. However, the present invention is not limited to this, and various elements such as a resistance element and a memory can be formed.

(Embodiment 2)
In the first embodiment, the insulating film above the fuse element F is completely removed and the fuse element F is exposed. However, the insulating film may be left on the fuse element F.

  Hereinafter, the configuration and manufacturing method of the semiconductor device of the present embodiment will be described in detail with reference to the drawings. FIG. 22 is a cross-sectional view showing the configuration of the semiconductor device of this embodiment.

[Description of structure]
First, in the present embodiment shown in FIG. 22, an interlayer insulating film TH6 is formed on the fuse element (laminated conductive film in which TiN / Ti / Al / TiN / Ti are sequentially laminated from the lower side) F by the thickness Y. Only remains. In other words, the film thickness of the interlayer insulating film TH5 on the fuse element F is smaller than the film thickness of the interlayer insulating film TH5 on the fifth layer wiring M5. Since the configuration other than the configuration is the same as that of the first embodiment, detailed description thereof is omitted.

[Production method explanation]
Next, the manufacturing process of the semiconductor device of the present embodiment will be described with reference to FIGS. 22 to 27, and the configuration of the semiconductor device will be clarified. 23 to 27 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

  The semiconductor element (n-channel type MISFET Qn and p-channel type MISFET Qp) shown in FIG. 22 and a plurality of wirings (M1 to M4) formed thereon are the same as those in the first embodiment, and the description thereof is omitted ( (See columns [Qn, Qp forming step] and [M1-M4 forming step] in the first embodiment).

[M5, F, M6, Pd formation process]
A process after forming the fourth layer wiring M4 among the plurality of wirings (M1 to M4) shown in FIG. 22 will be described below. After the formation of the fourth layer wiring M4, the fifth layer wiring M5, the fuse element F and the sixth layer wiring (Al wiring) M6 are formed, and the upper portion thereof is covered with the protective film (12, 13, 16), and then The part is exposed, and a pad region (Al pad, pad, bonding pad, opening) Pd is formed. The process will be described in detail with reference to FIGS. 23 to 27 correspond to a partially enlarged portion in the vicinity of the fuse element and pad region of FIG.

  First, as shown in FIG. 23, an interlayer insulating film TH5 is formed on the fourth layer wiring M4, and a plug P5 is formed in the interlayer insulating film TH5. The interlayer insulating film TH5 is formed in the same manner as the interlayer insulating film TH2 of the first embodiment. The plug P5 is formed in the same manner as the plug P2 of the first embodiment. Further, the fifth layer wiring (Al wiring) M5 is formed on the interlayer insulating film TH5 and the plug P5 in the same manner as the second layer wiring (Al wiring) M2 of the first embodiment. F is also formed at the same time.

  That is, as the barrier film 5a, for example, a TiN / Ti film is formed on the interlayer insulating film TH5 and the plug P5 by a sputtering method or the like. Next, an Al film 5b is formed on the barrier film 5a by a sputtering method, and a TiN / Ti film, for example, is formed thereon as the barrier film 5c by a sputtering method or the like. Next, a silicon oxynitride film (SiON film) is formed as an antireflection film AR on the barrier film 5c by a CVD method or the like. Through the above steps, the laminated conductive films (5a, 5b, 5c) in which TiN / Ti / Al / TiN / Ti are sequentially laminated from the lower side and the antireflection film AR on the upper side thereof are formed.

  Next, a photoresist film (not shown) is applied on the laminated conductive films (5a, 5b, 5c) and the antireflection film AR, and is exposed and developed (photolithography), thereby forming the formation region of the fifth layer wiring M5 and The photoresist film is left in the formation region of the fuse element F. Next, the fifth layer wiring (Al wiring) M5 and the fuse element F are formed by etching (patterning) the laminated conductive films (5a, 5b, 5c) and the antireflection film AR using the photoresist film as a mask. To do.

  The fuse element F is formed in a line shape as in the first embodiment (see FIG. 2), and both ends thereof are connected to various terminals and circuits (see FIG. 5). This terminal is a wiring (M1 to M6) or a part of the wiring, and the circuit is composed of a wiring and a plurality of elements (for example, Qn, Qp, etc.).

  Next, a silicon oxide film, for example, is deposited as an insulating film on the fifth layer wiring M5 and the fuse element F by the CVD method. Thereafter, if necessary, the surface of the silicon oxide film is polished by CMP to planarize the surface, thereby forming an interlayer insulating film TH6.

  Next, by etching the interlayer insulating film TH6, a contact hole (connection hole) is formed on the fifth layer wiring M5. Next, for example, a TiN / Ti film is formed as a barrier film (not shown) on the interlayer insulating film TH6 including the inside of the contact hole by using a sputtering method or the like, and then a W film is deposited by the CVD method. Next, by polishing the W film or the like by CMP until the interlayer insulating film TH6 is exposed, the plug P6 is formed by embedding a conductive film in the contact hole.

  Next, for example, a TiN / Ti film is formed as a barrier film 6a on the interlayer insulating film TH6 and the plug P6 by a sputtering method or the like.

  Next, an Al film 6b is formed on the barrier film 6a by a sputtering method. Next, for example, a TiN film (single layer film) is formed as a barrier film 6c on the Al film 6b by a sputtering method or the like.

  Next, a silicon oxynitride film (SiON film) is formed as an antireflection film AR on the barrier film 6c by a CVD method or the like.

  By the above process, a laminated conductive film in which TiN / Ti / Al / TiN is laminated in order from the lower side and an antireflection film AR on the upper side thereof are formed.

  Next, a photoresist film (not shown) is applied on the laminated conductive films (6a, 6b, 6c) and the antireflection film AR, and exposed and developed (photolithography) to form a sixth layer wiring M6 formation region. The photoresist film is left. Next, by using the photoresist film as a mask, the laminated conductive films (6a, 6b, 6c) and the antireflection film AR are etched (patterned) to form a sixth layer wiring (Al wiring) M6. The sixth layer wiring (Al wiring) M6 is the uppermost layer wiring, and the film thickness (total film thickness of the laminated conductive film made of TiN / Ti / Al / TiN) is lower than the wiring (M1 to M1). It is larger than the total film thickness of the laminated conductive film made of TiN / Ti / Al / TiN / Ti of M5. In particular, the thickness of the Al film 6b constituting the sixth layer wiring (Al wiring) M6 is larger than the thickness of Al constituting the lower layer wiring. Further, the wiring width of the sixth layer wiring (Al wiring) M6 is larger than the wiring width of the lower layer wirings (M1 to M5).

  Next, for example, a stacked film of a silicon oxide film 12 and a silicon nitride film 13 is formed as a first protective film (first insulating film) on the sixth layer wiring M6. Each of these films can be formed by a plasma CVD method.

  Next, a photoresist film R is applied on the silicon nitride film 13. Next, the photoresist film R in the openings OA1 and OA2 is removed by exposing and developing the photoresist film R. The opening OA1 is, for example, a certain area including the program area (cuttable area) Fp. The opening OA2 corresponds to a pad region Pd described later.

  Next, as shown in FIG. 24, the silicon nitride film 13 of the first protective films (12, 13) is etched using the photoresist film R as a mask. Next, the underlying silicon oxide film 12 is etched. At this time, the silicon oxide film 12 above the fuse element F is etched. As shown in FIG. 24, the interlayer insulating film (silicon oxide film) TH6 may be etched. The film thickness of the insulating film (silicon oxide film 12 and interlayer insulating film TH6) remaining above the fuse element F is Y1.

  Next, as shown in FIGS. 25 and 26, the antireflection film AR on the sixth layer wiring M6 and the barrier film 6c in the sixth layer wiring (Al wiring) M6 are simultaneously etched. FIG. 25 is a cross-sectional view when the surface of the sixth layer wiring M6, that is, the surface of the barrier film (TiN film) 6c is exposed. By the etching so far, the insulating film (the silicon oxide film 12 and the interlayer insulating film TH6) remaining above the fuse element F is further etched. The film thickness of the insulating film (interlayer insulating film TH6) remaining above the fuse element F is Y2 <Y1. Thereafter, as shown in FIG. 26, the barrier film 6c in the sixth layer wiring (Al wiring) M6 is continuously etched to expose the Al film 6b. The exposed region of the Al film 6b becomes a pad region Pd. By the etching so far, the insulating film (interlayer insulating film TH6) remaining above the fuse element F can be further etched even in the opening OA1. The film thickness of the insulating film (interlayer insulating film TH6) remaining above the fuse element F after this etching process is defined as Y (Y <Y2 <Y1). As described in the first embodiment, when over-etching is performed in the pad region Pd, the film thickness of the insulating film remaining above the fuse element F is further reduced.

  Next, as shown in FIG. 27, on the first protective film including the pad region Pd (on the silicon nitride film 13), for example, a photosensitive polyimide film (PIQ film: Polyimide-isoindoloquinazolinedion film) 16 is used as the second protective film. Apply. Next, the photosensitive polyimide film 16 is exposed and developed to remove the photosensitive polyimide film 16 in the openings OA1 and OA2. By this step, the Al film 6b (pad region Pd) is exposed again from the opening OA2.

  In FIG. 27, the opening OA2 of the first protective film (silicon oxide film 12, silicon nitride film 13) and the opening OA2 of the second protective film (photosensitive polyimide film 16) have the same size. The opening of the second protective film may be larger than the opening OA2 of the first protective film. Similarly, the opening OA1 of the first protective film (silicon oxide film 12, silicon nitride film 13) and interlayer insulating film TH6 and the opening OA1 of the second protective film (photosensitive polyimide film 16) have the same size. The opening of the second protective film may be larger than the opening OA1 of the first protective film. Next, the photosensitive polyimide film (second protective film) 16 is cured by performing heat treatment (curing treatment).

  Through the above process, the semiconductor element (Qn, Qp), the multilayer wiring (M1 to M6) and the fuse element F thereon are substantially completed.

  Since the subsequent steps are the same as those in the first embodiment, detailed description thereof is omitted. That is, as in the first embodiment, the operation test of the semiconductor device is performed using the pad region Pd, and the fuse element F is programmed. For example, it is determined which fuse element F is to be cut according to the result of the probe test and the specifications (frequency and corresponding voltage) of the semiconductor device, and the corresponding fuse element F is cut. Information on which fuse element F is to be cut is referred to as test information. Based on this test information, an overcurrent is caused to flow from the aforementioned fusing circuit (93, FIG. 5) to the fuse to be cut, and the program area (cuttable area) Fp of the fuse element F is cut (non-conductive state).

  Thereafter, through the same mounting process as that of the first embodiment, the semiconductor device is substantially completed (see the column of [Description of circuit operation of semiconductor device] in the first embodiment). The circuit operation of this semiconductor device is also the same as that of the first embodiment, and thus the description thereof is omitted (see the [Description of circuit operation of semiconductor device] column of the first embodiment).

  In the present embodiment described in detail above, the same effects as in the first embodiment are obtained (see the columns <1> to <3> in the first embodiment).

  That is, <1> In steps other than the program step and the read step, the transistor (switching element) Ts is turned on, and both ends (node n1, node n2) of the fuse element F are set to the ground potential (GND). Connecting. As described above, by connecting both ends (node n1, node n2) of the fuse element F to the ground potential (GND), alteration of various films (Al, Ti, TiN) constituting the fuse element F can be reduced. it can. Thus, the reliability of the semiconductor device can be improved.

  <2> Further, the etching control of the insulating film on the fuse element F is facilitated. In the comparative example described in detail in the first embodiment, the insulating film on the fuse element F is often left in order to minimize the alteration of the fuse element F and improve the quality. However, as described in <1>, in steps other than the program step and the read step, the fuse element F is connected by connecting both ends (node n1, node n2) of the fuse element F to the ground potential (GND). Alteration of various films (Al, Ti, TiN) to be formed can be reduced. Therefore, even if a variation occurs in the remaining film on the fuse element F and a part of the fuse elements F is exposed, it is possible to reduce alteration of various films (Al, Ti, TiN) constituting the fuse element F. it can. In this way, it is not necessary to adjust the residual film of the insulating film on the fuse element F severely, and the controllability of etching is improved. Thus, a semiconductor device can be formed with a simple manufacturing process. In addition, throughput can be improved in manufacturing a semiconductor device. Further, it is possible to cope with the thinning of the insulating film on the fuse element F.

  In the comparative example, the alteration of the fuse element F may occur after the mounting process. Therefore, at the time of product shipment, even if it is a non-defective product, quality deterioration due to alteration of the fuse element F may occur during subsequent use. On the other hand, in the present embodiment, even during product operation (in use), the transistor (switching element) Ts is turned on (ON) in the processes other than the program process, and both ends of the fuse element F ( Since the nodes n1 and n2) are connected to the ground potential (GND), the reliability of the semiconductor device can be improved.

  <3> Further, in this embodiment, as described in <2>, even if the remaining film on the fuse element F varies and a part of the fuse elements F is exposed, the fuse element F Therefore, the insulating film remaining above the fuse element F can be set thin, and the energy required for fusing can be reduced. Moreover, the controllability of energy required for fusing is improved. Therefore, a necessary site can be accurately cut. In addition, defects due to application of excessive energy can be reduced. Thus, the reliability of the semiconductor device can be improved. The characteristics of the semiconductor device can be improved.

  As shown in <1> to <3> above, according to the present embodiment, the characteristics of the semiconductor device can be improved.

  In the present embodiment, the fuse element F is programmed in the pre-process of the semiconductor device manufacturing process (before dicing, in the wafer state) (see the column “Programming process” above). The programming process is not limited to such a stage, and may be performed after the mounting process, for example. In particular, as described above, when the fuse element F is cut by electric fusing, the product user can also program the fuse element F.

  Also in this embodiment, face-down bonding may be performed.

  In the present embodiment, the first to sixth layer wirings (M1 to M6) are formed, but the total number of wirings is not limited. In the present embodiment, the fuse element F is formed in the same layer as the fifth layer wiring M5. However, the present invention is not limited to this. For example, in the same layer as the sixth layer wiring (uppermost layer wiring) M6. A fuse element F may be formed. However, as described above, the uppermost wiring layer has a large width and a thick wiring is often used. When the fuse element F is formed in the same manner as the wiring, the energy required for fusing increases. Therefore, it is preferable to form the fuse element in the same layer as the first to fifth layer wirings (M1 to M5) that are thinner (for example, 250 nm or less) and narrower than the uppermost layer wiring. Further, the fuse element F may be formed in the same layer as the first to fourth layer wirings (M1 to M4). However, when the fuse element F is formed in the same layer as the underlying wiring, the etching amount when the fuse element F is exposed increases. Therefore, it is preferable to form the fuse element F in the same layer as the wiring (here, the fifth layer wiring M5) which is lower than the uppermost layer wiring and positioned as high as possible. In the case of a semiconductor device having rearrangement wiring, this rearrangement wiring is not the uppermost layer wiring.

  In the above process, the MISFET formation process is exemplified as the semiconductor element. However, the present invention is not limited to this, and various elements such as a resistance element and a memory can be formed.

(Embodiment 3)
In the first and second embodiments, the fuse element F is cut using the fusing circuit 93. However, the fuse element F may be cut by laser irradiation.

  Since the processes other than the fuse element F cutting process (programming process) are the same as those in the first and second embodiments, the description of the manufacturing process other than the above [programming process] and the structure description of the semiconductor device are omitted. .

[Programming process]
After the wafer test process described in the first and second embodiments, the fuse element F is programmed. That is, for example, it is determined which fuse element F is to be cut according to the result of the probe test and the specifications (frequency and corresponding voltage) of the semiconductor device, and the corresponding fuse element F is cut. Information on which fuse element F is to be cut is referred to as test information. Based on this test information, the fuse to be cut is irradiated with laser, and the program area (cuttable area) Fp of the fuse element F is cut (non-conductive state). In the present embodiment, it is not necessary to store the test information in the semiconductor chip CHP as in the first and second embodiments (see FIG. 14).

  In this case, the fuse element F and its peripheral circuits have, for example, the configuration shown in FIG. FIG. 28 is a circuit diagram showing a circuit to which the fuse element of the semiconductor device of the present embodiment is connected.

  As shown in FIG. 28, one end (node n1) of the fuse element F is connected to the ground potential (GND, ground potential wiring, ground potential terminal), and the other end (node n2) of the fuse element F is connected to the determination circuit 95. It is connected to the. A determination circuit 95 is connected to the other end (node n2) of the fuse element.

  Here, the other end (node n2) of the fuse element F of the present embodiment is connected to (GND, ground potential wiring, ground potential terminal) via a transistor (switching element) Ts.

  In the present embodiment, a predetermined fuse element F is cut (fused) by laser irradiation. Such a process is called a program process. In the case of performing laser fusing, it is not necessary to turn off the transistor (switching element) Ts. For example, a laser is irradiated to the program area Fp of the fuse element F in the state shown in FIG. 2 to cut the fuse element F (see FIG. 3). Laser fusing is performed in a pre-process (before dicing, wafer state) of the semiconductor device manufacturing process.

[Description of circuit operation of semiconductor device]
Next, circuit operation of the semiconductor device will be described. The semiconductor device is incorporated into various electronic devices such as a PC (Personal computer) and a mobile phone.

  For example, when power is supplied to these electronic devices, trimming information (various setting information) is read during an initial setting period, and the information is stored in a predetermined area (for example, a memory area shown in FIG. 14). Or analog circuit area). Thereafter, desired operations (normal operation, typically image processing, control processing of various electronic devices in which a semiconductor device is incorporated, analog-digital conversion processing, sensor output processing, and the like) are performed.

  That is, in the initial setting period, the data stored in the fuse element F is read by the above-described determination circuit 95 (see FIG. 5). Hereinafter, the circuit operation of the semiconductor device in the reading process will be described with reference to FIGS. As described above, in this reading process, the transistor (switching element) Ts is in an off state.

  FIG. 17 is a diagram illustrating the relationship between the initial setting period and the normal operation period. FIG. 18 is a circuit diagram illustrating a first example of the determination circuit. FIG. 19 is a circuit diagram illustrating a second example of the determination circuit. FIG. 20 is a circuit diagram showing an example of a RIN signal generation circuit of the determination circuit shown in FIG. FIG. 21 is a timing chart for explaining the operation of the determination circuit shown in FIG.

  As shown in FIG. 17, the operation of the semiconductor device has an initial setting period T1 and a subsequent normal operation period T2. The read operation is performed during the initial setting period T1. That is, the reading period Tr is included in the initial setting period T1.

<First example>
In the determination circuit shown in FIG. 18, one end (node n1) of the fuse element F is connected to the ground potential (GND). The other end (node n2) of the fuse element F is connected to the power supply potential (VDD) via the resistance element Re and the n-channel type MISFET Tn. A connection node between the fuse element F and the resistance element Re is an output unit OUT.

  For example, in the determination circuit shown in FIG. 18, the signal S applied to the gate electrode of the n-channel type MISFET Tn rises, that is, changes from L level to H level, so that the reading period starts.

  As the signal S rises, the n-channel MISFET Tn is turned on. At this time, if the fuse element F is in a cut state, an H level signal is output from the output unit OUT. When the fuse element F is not cut, an L level signal is output from the output unit OUT. After the read data is written (stored) in a predetermined area (for example, a memory area or an analog circuit area shown in FIG. 14), the signal S falls (H level → L level), and the read period Tr is set. finish. After the initial setting such as reading of data recorded in the fuse element F is completed, the normal operation is performed.

  The n-channel MISFET (switching element) Ts is turned off during the readout period (between the rise and fall of the signal S; Tr), and the n-channel MISFET (switching element) is turned off after the readout period ends. Ts is turned on.

  In the circuit operation of the semiconductor device, in the reading process (period), the transistor (switching element) Ts is turned on by the signal SF, and, for example, the fuse element F is cut (Fb). The other end (node n2) of the fuse element F becomes H level (high potential level), and a signal corresponding to this is output from the determination circuit 95 to determine disconnection. That is, when the “cut state” is “0” data, “0” data is recognized. On the other hand, when the fuse element F is not cut (Fa), the other end (node n2) of the fuse element F becomes L level (low potential level), and a signal corresponding to this is output from the determination circuit 95, Judge uncut. That is, when the “uncut state” is “1” data, “1” data is recognized.

  Here, in the present embodiment, the transistor (switching element) Ts is turned on in steps other than the reading step in the circuit operation of the semiconductor device, and both ends of the fuse element F (node n1, node n2). ) To the ground potential (GND, ground potential wiring, ground potential terminal). Thus, regardless of the method of cutting the fuse element F, in the reading process, the both ends (node n1, node n2) are connected to the ground potential (GND, ground potential wiring, ground potential terminal), so that the fuse element Even if F is exposed from the protective film (12, 13, 16) or the protective film remains, alteration of the fuse element F can be reduced.

  Therefore, as described in <1> to <3> of the first and second embodiments, the characteristics of the semiconductor device can be improved.

  In particular, when laser fusing is used, a big hole phenomenon is likely to occur.

  This is due to the difference in the laser absorption intensity ratio between the upper part and the lower part of the fuse element F. For example, as the fuse element (wiring) F is thinned, the energy absorption in the lower part becomes larger with respect to the upper part, and the lower part is largely removed with respect to the upper part. Further, when the insulating film on the fuse element F is thick, the energy by the laser tends to be trapped, and the insulating film is cracked or the adjacent fuse element F is damaged. Such a defect is called a big hole.

  However, according to the present embodiment, in the reading process, the both ends (node n1, node n2) are connected to the ground potential (GND, ground potential wiring, ground potential terminal), so that the alteration of the fuse element F is prevented. Can be reduced. Therefore, the fuse element F has a bare structure (Embodiment 1), or the insulating film on the fuse element F can be thinned, so that the laser irradiation energy can be optimized and the generation of the big hole can be prevented. Can be reduced.

  In addition, since the trouble similar to the big hole can also be caused by electric fusing, the occurrence of the big hole can be reduced even in the electric fusing of the first and second embodiments.

  As mentioned above, although the invention made by the present inventor has been specifically described based on the first to third embodiments, the present invention is not limited to the first to third embodiments and does not depart from the gist thereof. Needless to say, various changes can be made.

  The present invention is suitable for application to a semiconductor device, particularly a semiconductor device having a fuse.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3n Source, drain region 3p Source, drain region 5a Barrier film 5b Al film 5c Barrier film 6a Barrier film 6b Al film 6c Barrier film 12 Silicon oxide film 13 Silicon nitride film 16 Photosensitive polyimide film 50 CPU Area 60 memory area 70 analog circuit area 80 trimming area 91 transistor 93 fusing circuit 95 determination circuit 97 resistance element AR antireflection film BU1 buffer BU2 buffer BU3 buffer BU4 buffer CHP semiconductor chip D1 first delay circuit D2 second delay circuit F fuse element FOUT Output part Fp Program area G Gate electrode GND Ground potential INV1 to INV6 Inverter M1 First layer wiring M2 Second layer wiring M3 Third layer wiring M4 Fourth layer wiring M5 Fifth layer wiring M6 Sixth layer wiring MR Sealing resin No t output node OA1 opening OA2 opening OUT output unit P1~P6 plug Pd pad region Qn n-channel type MISFET
Qp p-channel MISFET
R Photoresist film Re Resistance element S Signal SB Solder ball SF Signal T1 Initial setting period T2 Normal operation period TC Test information circuit TE Terminals TH1 to TH6 Interlayer insulating film Tn n-channel type MISFET
Tn3 n-channel MISFET
Tn4 n-channel MISFET
Tn7 n-channel MISFET
Tn8 n-channel MISFET
Tn9 n-channel MISFET
Tp1 p-channel MISFET
Tp2 p-channel MISFET
Tp5 p-channel MISFET
Tp6 p-channel MISFET
Tr readout period Ts n-channel MISFET
VDD power supply potential W wire WB wiring board Y film thickness n1 to n3 node z altered region

Claims (28)

A semiconductor element formed above the semiconductor substrate;
A first insulating film formed above the semiconductor element;
A fuse element formed of a first conductive film containing aluminum (Al) formed on the first insulating film;
A first wiring formed on the first insulating film and made of the first conductive film;
A second insulating film formed on the first wiring,
The semiconductor device according to claim 1, wherein the program region of the fuse element is exposed through a first opening provided in the second insulating film.   2. The semiconductor device according to claim 1, wherein the program area is in a disconnected state.   The semiconductor device according to claim 1, wherein the program area is in an uncut state. A second wiring made of a second conductive film formed above the second insulating film;
A third insulating film formed on the second wiring,
The first opening is also provided in a stacked film of the second insulating film and the third insulating film,
The semiconductor device according to claim 1, wherein a program region of the fuse element is exposed from the first opening provided in the stacked film. The third insulating film has a second opening exposing a pad region of the second wiring;
The semiconductor device according to claim 4, wherein a conductive member is connected to the pad region.   6. The semiconductor device according to claim 5, wherein the first opening and the second opening are formed simultaneously.   6. The semiconductor device according to claim 5, wherein upper portions of the third insulating film and the conductive member are covered with a sealing resin. The fuse element has a first end that is one end of the program area and a second end that is the other end of the program area,
The first end is connected to a ground potential;
The semiconductor device according to claim 1, wherein the second end is connected to the ground potential via a switching element.   The semiconductor device according to claim 8, wherein the fuse element is cut when the switching element is in an OFF state.   9. The semiconductor device according to claim 8, wherein reading whether the program area of the fuse element is in a cut state or an uncut state is performed when the switching element is in an off state.   11. The semiconductor device according to claim 10, wherein the second end is connected to a power supply potential during the reading period. The semiconductor device includes:
A program period for cutting the program region of the fuse element;
A read period for determining whether the program area of the fuse element is in a cut state or an uncut state, and
9. The semiconductor device according to claim 8, wherein the switching element has a period in an on state in a period other than the program period and the read period. In the operation of the semiconductor device,
An initial setting period and an operation period after the initial setting period;
13. The semiconductor device according to claim 12, wherein the read period is included in the initial setting period. The fuse element,
A first fuse element in which the cuttable region is in an uncut state;
The disconnectable region has a second fuse element in a disconnected state,
One end of the breakable region of the first fuse element is connected to a ground potential,
The other end of the breakable region of the first fuse element is connected to the ground potential via the first switching element,
One end of the cuttable region of the second fuse element is connected to a ground potential,
The other end of the severable region of the second fuse element is connected to the ground potential via a second switching element,
In a reading period of program information of the first fuse element and the second fuse element of the semiconductor device,
9. The semiconductor device according to claim 8, wherein the first switching element and the second switching element are in an off state.   9. The semiconductor device according to claim 8, wherein the fuse element is cut by electric fusing.   9. The semiconductor device according to claim 8, wherein the fuse element is cut by laser irradiation.   9. The semiconductor device according to claim 8, wherein the switching element is configured by a MISFET. In a semiconductor device having a fuse element made of a conductive film containing aluminum,
In the operation of the semiconductor device,
An initial setting period and an operation period after the initial setting period;
There is a data read period programmed in the fuse element in the initial setting period,
In the operation period, both ends of the fuse element are maintained at a ground potential.   19. The semiconductor device according to claim 18, wherein one end of the fuse element is connected to a ground potential, and the other end is connected to the ground potential via a switching element.   20. The semiconductor device according to claim 19, wherein a fusing circuit is connected to the other end of the fuse element. In the program period of the fuse element,
Turning off the switching element;
21. The semiconductor device according to claim 20, wherein an overcurrent is passed from the fusing circuit to the fuse element to cut a predetermined portion of the fuse element. In the program period of the fuse element,
20. The semiconductor device according to claim 19, wherein the fuse element is irradiated with a laser to cut a predetermined portion of the fuse element.   The semiconductor device according to claim 19, wherein a reading circuit is connected to the other end of the fuse element. In the readout period,
Turning off the switching element;
The readout circuit is
When the fuse element is in a cut state, a potential at one end of the fuse element is set as a power supply potential,
When the fuse element is in an uncut state, the potential of one end of the fuse element is set to the ground potential,
24. The semiconductor device according to claim 23, wherein a potential corresponding to a potential at one end of the fuse element is output as an output potential. In the operation of the semiconductor device,
An initial setting period, and an operation period after the initial setting period,
19. The semiconductor device according to claim 18, wherein the read period is included in the initial setting period.   The semiconductor device according to claim 19, wherein the switching element is configured by a MISFET. The fuse element is formed on the first insulating film,
A first wiring is formed on the first insulating film,
A second insulating film is formed on the first wiring,
19. The semiconductor device according to claim 18, wherein the program region of the fuse element is exposed from an opening provided in the insulating film. The fuse element is formed on the first insulating film,
A first wiring is formed on the first insulating film,
A second insulating film is formed on the first wiring and the fuse element,
19. The semiconductor device according to claim 18, wherein a film thickness of the second insulating film on the program region of the fuse element is smaller than a film thickness of the second insulating film on the first wiring.